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Author SHA1 Message Date
Ali Saidi
c5fbbf376a Change everything to use the cached virtPort rather than created their own each time. 
This appears to work, but I don't want to commit it until it gets tested a lot more.
I haven't deleted the functionality in this patch that will come later, but one question
is how to enforce encourage objects that call getVirtPort() to not cache the virtual port
since if the CPU changes out from under them it will be worse than useless. Perhaps a null
function like delVirtPort() is still useful in that case.
 2008-07-01 10:24:19 -04:00
Ali Saidi
50e3e50e1a Make the cached virtPort have a thread context so it can do everything that a newly created one can. 2008-07-01 10:24:16 -04:00
Ali Saidi
9bd0bfe559 After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong. 
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
 2008-07-01 10:24:09 -04:00
Steve Reinhardt
96bbccc36b Automated merge after backout. 2008-06-28 13:20:00 -04:00
Steve Reinhardt
caaac16803 Backed out changeset 94a7bb476fca: caused memory leak. 2008-06-28 13:19:38 -04:00
Ali Saidi
3205768ea5 Automated merge with http://repo.m5sim.org/m5-stable 2008-06-24 15:51:12 -04:00
Ali Saidi
57b5de6b9f Checkpoinging/SWIG: Undo part of changeset 5464 since it broke checkpointing. 2008-06-24 15:48:45 -04:00
Gabe Black
18c83be507 SimObject: Add in missing includes of <string> and fix minor style problem. 2008-06-21 14:23:58 -04:00
Steve Reinhardt
1434b86943 Make bus address conflict error more informative 2008-06-21 01:06:27 -04:00
Steve Reinhardt
6b45238316 Generate more useful error messages for unconnected ports. 
Force all non-default ports to provide a name and an
owner in the constructor.
 2008-06-21 01:04:43 -04:00
Nathan Binkert
c1584e4227 imported patch sim_object_params.diff 2008-06-18 12:07:15 -07:00
Nathan Binkert
67a33eed40 AtomicSimpleCPU: Separate data stalls from instruction stalls. 
Separate simulation of icache stalls and dat stalls.
 2008-06-18 10:15:21 -07:00
Nathan Binkert
1099a9838a Ethernet: share statistics between all ethernet devices and apply some 
of those statistics to the e1000 model.
 2008-06-17 22:22:44 -07:00
Nathan Binkert
87d03d00cd inet: initialization fixes. 
Make sure variables are properly initialized and also make sure that
truth testing works properly.
 2008-06-17 22:14:12 -07:00
Nathan Binkert
8042b8f4c7 PacketFifo: Get slack out of the EthPacketData structure. This allows 
a packet to exist in multiple FIFOs if desired.
 2008-06-17 21:34:27 -07:00
Nathan Binkert
163465ac08 ThreadState: Ensure that kernelStats is properly initialized 2008-06-17 21:11:20 -07:00
Nathan Binkert
9dc4e2952c rename MipsConsole to MipsBackdoor 
--HG--
rename : src/dev/mips/MipsConsole.py => src/dev/mips/MipsBackdoor.py
rename : src/dev/mips/console.cc => src/dev/mips/backdoor.cc
rename : src/dev/mips/console.hh => src/dev/mips/backdoor.hh
 2008-06-17 20:39:51 -07:00
Nathan Binkert
934523c3a0 rename AlphaConsole to AlphaBackdoor 
--HG--
rename : src/dev/alpha/AlphaConsole.py => src/dev/alpha/AlphaBackdoor.py
rename : src/dev/alpha/console.cc => src/dev/alpha/backdoor.cc
rename : src/dev/alpha/console.hh => src/dev/alpha/backdoor.hh
 2008-06-17 20:36:39 -07:00
Nathan Binkert
6ff4539901 Change the default output filename for the terminal so it's more obvious. 
--HG--
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
 2008-06-17 20:30:37 -07:00
Nathan Binkert
00df9016fe Rename SimConsole to Terminal since it makes more sense 
--HG--
rename : src/dev/SimConsole.py => src/dev/Terminal.py
rename : src/dev/simconsole.cc => src/dev/terminal.cc
rename : src/dev/simconsole.hh => src/dev/terminal.hh
 2008-06-17 20:29:06 -07:00
Nathan Binkert
fa8f91fdc0 physmem: Add a null option to physical memory so it doesn't store data. 2008-06-15 21:39:29 -07:00
Nathan Binkert
e3c267a3db port: Clean up default port setup and port switchover code. 2008-06-15 21:34:32 -07:00
Nathan Binkert
b429b1759d params: Prevent people from setting attributes on vector params. 2008-06-15 21:26:33 -07:00
Nathan Binkert
6dedc645f7 add compile flags to m5 2008-06-15 20:56:35 -07:00
Nathan Binkert
b2036bfda8 Command line option to print out List of SimObjects and their parameters 2008-06-14 21:51:08 -07:00
Nathan Binkert
bbeb8082a5 main: add .m5/options.py processing. This file is processed before 
arguments are parsed so that they can change the default options for
various config parameters.
 2008-06-14 21:16:00 -07:00
Nathan Binkert
fc48d1dcf5 Add .m5 configuration directory 2008-06-14 21:15:59 -07:00
Nathan Binkert
779c31077c python: Separate the options parsing stuff. Remove options parsing stuff from 
main.py so things are a bit more obvious.
 2008-06-14 21:15:58 -07:00
Nathan Binkert
4afdc40d70 params: Fix the memory bandwidth parameter 2008-06-14 20:42:45 -07:00
Nathan Binkert
3d2e7797cc params: Fix floating point parameters 2008-06-14 20:39:31 -07:00
Nathan Binkert
f82d4e2364 python: Move various utility classes into a new m5.util package so 
they're all in the same place.  This also involves having just one
jobfile.py and moving it into the utils directory to avoid
duplication.  Lots of improvements to the utility as well.

--HG--
rename : src/python/m5/attrdict.py => src/python/m5/util/attrdict.py
rename : util/pbs/jobfile.py => src/python/m5/util/jobfile.py
rename : src/python/m5/util.py => src/python/m5/util/misc.py
rename : src/python/m5/multidict.py => src/python/m5/util/multidict.py
rename : util/stats/orderdict.py => src/python/m5/util/orderdict.py
 2008-06-14 20:19:49 -07:00
Nathan Binkert
fe325c7f43 MemReq: Add option to reset the time on a request. 2008-06-14 19:39:01 -07:00
Nathan Binkert
ce43e46576 Fix various SWIG warnings 2008-06-14 12:57:21 -07:00
Nathan Binkert
7a58b5a38a Add missing dependencies on .i files 2008-06-14 12:10:50 -07:00
Nathan Binkert
2d037682ff scons: proper fix for hg version stuff 2008-06-14 10:30:18 -07:00
Nathan Binkert
fe4fd9f414 scons: fix program_info.cc generation 2008-06-13 17:34:22 -07:00
Steve Reinhardt
dace77dc4a Automated merge with ssh://m5sim.org//repo/m5 2008-06-13 01:59:10 -04:00
Steve Reinhardt
caccbd1edc Get rid of bogus bus assertion. 
It runs out that if a MemObject turns around and does a send in its
receive callback, and there are other sends already scheduled, then
it could observe a state where it's not at the head of the list but
the bus's sendEvent is not scheduled (because we're still in the
middle of processing the prior sendEvent).
 2008-06-13 01:33:49 -04:00
Steve Reinhardt
024ec4c5c3 Get rid of bogus cache assertion. 
I was asserting that the only reason you would defer targets is if
a write came in while you had an outstanding read miss, but there's
another case where you could get a read access after you've snooped
an invalidation and buffered it because it applies to a prior
outstanding miss.
 2008-06-13 01:29:20 -04:00
Ali Saidi
907b28cc62 HG: Add compiled hg revision and date to the standard M5 output. 2008-06-13 01:09:04 -04:00
Gabe Black
2b4874449c Alpha: Get rid of an old include of a non-existant file. 2008-06-12 01:54:21 -04:00
Gabe Black
7be8e671f1 Params: Allow nested namespaces in cxx_namespace 2008-06-12 01:00:29 -04:00
Gabe Black
5b5875341c X86: Make the cpuid processor identifier return a real string. 2008-06-12 01:00:19 -04:00
Gabe Black
c625cf0ae1 X86: Make the code compile as 32 bit. 2008-06-12 01:00:05 -04:00
Gabe Black
23c04b8c66 Params: Remove an unnecessary include. 2008-06-12 00:59:58 -04:00
Gabe Black
bceaa257a3 X86: Make the e820 table manually or automatically configurable from python. 2008-06-12 00:58:36 -04:00
Gabe Black
4f4ff17578 X86: Make the disassembly for halt conform with the other microops. 2008-06-12 00:58:27 -04:00
Gabe Black
31d40ad7c2 X86: Implement and hook up STI and CLI instructions. 2008-06-12 00:58:19 -04:00
Gabe Black
da20c0ec54 X86: Make sure there's something to catch when the kernel messes with ports "behind" the pci config magic ports. 2008-06-12 00:58:13 -04:00
Gabe Black
1f5b992b58 X86: Make the platform object initialize channel 0 of the PIT. 2008-06-12 00:56:54 -04:00
Gabe Black
16e26fbf03 X86: Hook the speaker device to the pit device. 2008-06-12 00:56:17 -04:00
Gabe Black
da7f512067 Timer: Fill out the periodic modes a little. 2008-06-12 00:56:07 -04:00
Gabe Black
4f9a0402f6 Dev: Seperate the 8254 timer from tsunami and use it in that and the PC. 2008-06-12 00:54:48 -04:00
Gabe Black
0368ccdeda BitUnion: Take out namespace declaration so bitunions can be declared inside classes. 2008-06-12 00:54:32 -04:00
Gabe Black
81936ae2ed X86: Add an event for the apic timer timeout. It doesn't get used yet. 2008-06-12 00:54:19 -04:00
Gabe Black
6b8d0363ee X86: Rename the divide count register to divide configuration. 2008-06-12 00:54:12 -04:00
Gabe Black
b10742ee2b X86: Make the apic isr and irr work. 2008-06-12 00:54:05 -04:00
Gabe Black
69000baef3 X86: Make the apic task priority register work. 2008-06-12 00:54:01 -04:00
Gabe Black
e9c481ea4a X86: Make the logical destination and destination format work. 2008-06-12 00:53:50 -04:00
Gabe Black
ed23a4970b X86: Make the apic ID register work. 2008-06-12 00:53:43 -04:00
Gabe Black
8a6723e038 X86: Make the apic version register work. 2008-06-12 00:53:37 -04:00
Gabe Black
8d2416c6e9 X86: Implement a partial, sort of correct version of the protected mode variant of iret. 2008-06-12 00:53:01 -04:00
Gabe Black
66f54a6037 X86: Change how segment loading is performed. 2008-06-12 00:52:12 -04:00
Gabe Black
129831c116 X86: Make pushes and pops use the stack size instead of the data size. 2008-06-12 00:51:57 -04:00
Gabe Black
b05299253f X86: In non 64bit mode, throw a fault when a NULL segment is accessed. 2008-06-12 00:51:50 -04:00
Gabe Black
a8384311d5 X86: Take advantage of the new meta register. 2008-06-12 00:51:14 -04:00
Gabe Black
d4e7c7edd3 X86: Keep handy values like the operating mode in one register. 2008-06-12 00:50:25 -04:00
Gabe Black
fa7c81c6df X86: Change what the microop chks does. 
Instead of computing the segment descriptor address, this now checks if a
selector value/descriptor are legal for a particular purpose.
 2008-06-12 00:50:10 -04:00
Gabe Black
6bd9cf3594 X86: Add a microop to read a segments attribute register. 2008-06-12 00:50:05 -04:00
Gabe Black
e0c20386ac X86: Add microops and supporting code to manipulate the whole rflags register. 2008-06-12 00:49:50 -04:00
Gabe Black
2bb8933f78 X86: Add microops which panic, fatal, warn, and warn_once. 2008-06-12 00:49:25 -04:00
Gabe Black
bbc1f394ff X86: Truncate descriptors to 16 bits. 2008-06-12 00:49:16 -04:00
Gabe Black
6106b05b6e X86: Redo BSF. 2008-06-12 00:48:58 -04:00
Gabe Black
dfc2d44ea3 X86: Flesh out 3dnow instruction decoding a bit and grab the byte immediate. 2008-06-12 00:48:46 -04:00
Gabe Black
de6eeaaa27 X86: Make string instructions work when rcx=0. 2008-06-12 00:48:15 -04:00
Gabe Black
8688ef3fe5 X86: Have all 8 machine check registers since the kernel assumes they're there. 2008-06-12 00:48:02 -04:00
Gabe Black
a8e3001df8 X86: Bypass unaligned access support for register addressed MSRs. 2008-06-12 00:47:25 -04:00
Gabe Black
b3e55339f9 X86: Remove enforcement of APIC register access alignment. Panic if more than one register is accessed at a time. 2008-06-12 00:46:22 -04:00
Gabe Black
8e2991b529 X86: Fix the implementation of BSF. 2008-06-12 00:46:04 -04:00
Gabe Black
16e189fad2 X86: Bit scan forward/reverse were accidentally transposed. 2008-06-12 00:45:52 -04:00
Gabe Black
254cc07650 X86: Fix a byte register indexing issue in the sign extending move from memory microcode. 2008-06-12 00:45:22 -04:00
Gabe Black
8501a90f59 X86: Add in some support for the tsc register. 2008-06-12 00:39:10 -04:00
Gabe Black
d093fcb079 CPU: Make the simple cpu trace data for loads/stores. 2008-06-12 00:35:50 -04:00
Ali Saidi
5797ff1016 X86: Fix building on *BSD hosts 2008-06-11 10:54:12 -04:00
Ali Saidi
fd3e661cd3 SCons: Fix more SCons version issues 2008-06-11 10:54:08 -04:00
Ali Saidi
f5e36d156d IGbE: Implement sending packet that is contained in more than 2 descriptors. 
--HG--
extra : convert_revision : 8fb7d5fad5cb840f69c31aa8b331dbe09e46ee9d
 2008-05-20 16:06:56 -04:00
Stephen Hines
b7af65f414 SCons: Fixing SCons bug 2006 issues for non-alpha ISAs 
--HG--
extra : convert_revision : 26e3edef06d6f82aaf162825c151d18faadd6e72
 2008-05-20 14:04:53 -04:00
Ali Saidi
e71a5270a2 Make sure that output files are always checked success before they're used. 
Make OutputDirectory::resolve() private and change the functions using
resolve() to instead use create().

--HG--
extra : convert_revision : 36d4be629764d0c4c708cec8aa712cd15f966453
 2008-05-15 19:10:26 -04:00
Ali Saidi
4a4317ae18 SCons: More scons fixing for SCons bug 2006 
--HG--
extra : convert_revision : d3656ab1e3c18251d4bcf6f5a31103d4b2dfdc43
 2008-05-06 16:22:14 -04:00
Ali Saidi
8af6dc118c SCons: add comments to SConscript documenting bug workaround 
--HG--
extra : convert_revision : e6cdffe953d56b96c76c7ff14d2dcc3de3ccfcc3
 2008-04-10 15:38:10 -04:00
Ali Saidi
fe12f38353 PhysicalMemory: Add parameter for variance in memory delay. 
--HG--
extra : convert_revision : b931472e81dedb650b7accb9061cb426f1c32e66
 2008-04-10 14:44:52 -04:00
Ali Saidi
ed27c4c521 SCons: Manually specifying header only directories with Dir() works around the problem 
--HG--
extra : convert_revision : d9713228d934cf4a45114a972603b8bca2bd27d3
 2008-04-08 11:08:26 -04:00
Ali Saidi
1605fbebc8 IGbE: Fix bug that limits wire performance a bit 
--HG--
extra : convert_revision : 3f93c17f647a6955dab861da211174de856ee02c
 2008-03-25 15:58:54 -04:00
Steve Reinhardt
ba1f7d31e0 Automated merge with ssh://daystrom.m5sim.org//repo/m5 
--HG--
extra : convert_revision : 7922848bb1145bcb2ee07d672d21cfe2dd98fc03
 2008-03-25 10:04:52 -04:00
Steve Reinhardt
29be31ce31 Fix handling of writeback-induced writebacks in atomic mode. 
--HG--
extra : convert_revision : 4fa64f8a929f1aa36a9d5a71b8d1816b497aca4c
 2008-03-25 10:01:21 -04:00
Gabe Black
93dd1978a7 X86: Put an RTC into the CMOS part of the southbridge. 
--HG--
extra : convert_revision : a614373236fe75db6e6181fc152a02b541a131f3
 2008-03-25 02:15:23 -04:00
Gabe Black
e5bdae15f3 Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it. 
--HG--
extra : convert_revision : 1e7f5185654ed0845678c2169c702d3b977159ed
 2008-03-25 02:15:06 -04:00
Gabe Black
af9a57566a X86: Turn #defines into consts. 
--HG--
extra : convert_revision : c0416de5d88ca39f54494418768e68a93aa4f2aa
 2008-03-25 02:09:18 -04:00
Gabe Black
48409ca512 X86: Start implementing the south bridge stuff. 
--HG--
extra : convert_revision : 92918c05eb3363155d78889bdab17baa8eae9dca
 2008-03-25 02:08:54 -04:00
Gabe Black
b0c52885ce X86: Change the Opteron platform to be the PC platform. 
--HG--
extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37
 2008-03-25 02:06:53 -04:00