and importing stuff to avoid some confusion.
sim/pyconfig/SConscript:
Split the string importer from the rest of the importer code.
The importer.py code can be embedded like m5config.py
sim/pyconfig/m5config.py:
import what we need from importer
--HG--
extra : convert_revision : 9d57f43381b55e717b5b10adfb8f0a522280ac57
dev/etherlink.cc:
- The EtherLink::Link object is no lonver serializable, so it is now
necessary to prepend the object's name (as determined by the parent)
to all parameters.
- Fix the serialization of the LinkDelayEvent so it actually works
- Rename some variables to make serialization simpler
dev/etherlink.hh:
- Make the EtherLink::Link object *not* derive from serializeable.
Instead, the serialize function will take a base name from
the parent EtherLink object and prepend that base name to each of
its variable names when serializing. This is similar to the
PacketData and PacketFifo classes.
- Make the EtherLink::Link object keep a pointer to its parent and its
link number so the LinkDelayEvent can be properly serialized.
- Rename some variables to make serialization simpler.
--HG--
extra : convert_revision : e5aa54cd9e07b5e033989809100e1640abfb8bed
benchmark begins properly.
configs/boot/nat-netperf-maerts-client.rcS:
Fix the echo message
configs/boot/nat-netperf-server.rcS:
Wait a second before signalling the natbox to make sure it's
had time to boot.
Fix echo message.
--HG--
extra : convert_revision : f9d32c98f24b9617ebf917790a4ca554b7b02bba
of Param structs.
objects/CoherenceProtocol.mpy:
objects/Ide.mpy:
Update for new Enum syntax.
sim/pyconfig/m5config.py:
More modest restructuring heading for auto-generating
of param structs.
- Revamped Enum handling: Enums are regular classes so they
know their names now (makes it easier for generating C++
equivalents).
- Created MetaSimObject class and moved some SimObject-specific
stuff there (i.e. does not apply to ConfigNodes in general).
--HG--
extra : convert_revision : a93b40dda3b038ebe8bffecac97e9079c22af561
to make it easier to diff output from modified versions.
sim/pyconfig/m5config.py:
Sort .ini outputs for repeatable results across versions.
--HG--
extra : convert_revision : fa918f2c53635eca3a02ce02af9b320eacd1f057
1) Add fault_handler_delay param to FullCPU to wait N cycles after
committing faulting instruction before fetching fault handler.
2) Make hw_rei a serializing instruction (flushes pipe, basically).
arch/alpha/isa_desc:
Make hw_rei a serializing instruction (guarantees previous insts
complete before hw_rei will issue).
--HG--
extra : convert_revision : 704cef65b3869be9eee724055cedb22114a78359
sim/pyconfig/m5config.py:
Add some comments to indicate what the decorators mean.
--HG--
extra : convert_revision : fbcbcbe4ad8cd62f2bd12af6b1f141c66752b870
base/statistics.hh:
Get rid of operator%... g++ 3.4 complains that this isn't defined
for doubles (which makes sense). We never use it anyway.
--HG--
extra : convert_revision : 3ca724e1cc42559226549835f6cd3509308e02ca
instructions use it (instead of IntALU, as before). Default config
has a single non-pipelined 3-cycle unit. A bit conservative for the
ev6 (some are 1, some are 3).
arch/alpha/isa_desc:
Make hw_mfpr and hw_mtpr use IprAccessOp op class.
cpu/full_cpu/op_class.hh:
Add IprAccess.
--HG--
extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442
particular binary machine instruction and should be immutable after
they are constructed.
cpu/simple_cpu/simple_cpu.hh:
Make StaticInst parameters const.
--HG--
extra : convert_revision : e535fa10c842ce173336323f39d9108c1847f8ba
a faulting instruction is the fault handler, which appears as an independent
instruction to the timing model. New code will stall fetch and not fetch the
fault handler as long as there's a faulting instruction in the pipeline (i.e.,
the faulting inst has to commit first).
Also fix Ali's bad-address assertion that doesn't apply to full system.
Added some more debugging support in the process. Hopefully we'll move to the new
cpu model soon and we won't need it anymore.
arch/alpha/alpha_memory.cc:
Reorganize lookup() so we can trace the result of the lookup as well.
arch/alpha/isa_traits.hh:
Add NoopMachInst (so we can insert them in the pipeline on ifetch faults).
base/traceflags.py:
Replace "Dispatch" flag with "Pipeline" (since I added similar
DPRINTFs in other pipe stages).
cpu/exetrace.cc:
Change default for printing mis-speculated instructions to true (since
that's often what we want, and right now you can't change it from the
command line...).
--HG--
extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc
from Python object descriptions. Mostly cleanup of Python
code based on things I encountered trying to figure out
what's going on. Main reason I'm committing this now is
to transfer work from my laptop to zizzer.
sim/pyconfig/m5config.py:
Small steps toward param struct generation: all param
objects should now have a _cppname attribute that holds
their corresponding C++ type name.
Made Param ptype attribute an actual type instead of a
string. String is still stored in ptype_string.
Get rid of AddToPath() and Import() (redundant copies
are in importer, and that seems to be the more logical
place for them).
Add a few comments, delete some unused code.
test/genini.py:
A few fixes to make the environment more compatible
with what really happens when configs are executed
from the m5 binary.
--HG--
extra : convert_revision : 9fc8f72cd0c22ba3deada02f37484787342534f2
cpu/base_cpu.cc:
cpu/base_cpu.hh:
Convert the CPU stuff to use a params struct
cpu/memtest/memtest.cc:
The memory tester is really not a cpu, so don't derive from
BaseCPU since it just makes things a pain in the butt. Keep
track of max loads in the memtest class now that the base class
doesn't do it for us.
Don't have any default parameters.
cpu/memtest/memtest.hh:
The memory tester is really not a cpu, so don't derive from
BaseCPU since it just makes things a pain in the butt. Keep
track of max loads in the memtest class now that the base class
doesn't do it for us.
cpu/simple_cpu/simple_cpu.cc:
Convert to use a params struct.
remove default parameters
cpu/simple_cpu/simple_cpu.hh:
convert to use a params struct
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
this isn't really a cpu. don't derive from BaseCPU
objects/MemTest.mpy:
we only need one max_loads parameter
sim/main.cc:
Don't check for the number of CPUs since we may be doing something
else going on. If we don't have anything to simulate, the
simulator will exit anyway.
--HG--
extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5
it makes more sense and is less confusing.
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
width is a better name than multiplier
--HG--
extra : convert_revision : ea2fa4faa160f5657aece41df469bbc9f7244b21
sim/main.cc:
For some unknown reason linux's basename doesn't take a const char *
--HG--
extra : convert_revision : 30289195881e16a05429f7025abab7914a9e3eb6
configuration so that we can always have binning on.
base/statistics.cc:
If we're binning, and there is no bin active at the time
we check all stats stuff, create a bin.
base/statistics.hh:
FS_MEASURE doesn't exist anymore
base/stats/text.cc:
don't print out bin names if there is only one bin
sim/process.cc:
don't zero stats. It happens automatically.
Don't activate the context at the time it is registered,
instead activate the first context in a startup callback.
sim/process.hh:
Add startup callback to initialize the first exec context
--HG--
extra : convert_revision : bcb23cdb184b0abf7cecd79902f8a59b50f71fe4
outside of the loop so we get all of the jobs, not just the
last one.
util/pbs/send.py:
fix indent
--HG--
extra : convert_revision : eee9546b4945ff949fdfdf339fc95a23603b47d3
add dprintf on alignment faults
fix RR benchmark rcS script name
Add Dual test without rcS script
Update Monet to be closer to the real thing
Fix p4/monet configs
Add a way to read the DRIR register with at 32bit access for validation
SConscript:
build/SConstruct:
always use mysql if the libraries are installed
arch/alpha/alpha_memory.cc:
Add a DPRINTF to print alignment faults when they happen
dev/tsunami_cchip.cc:
Add a way to read the DRIR for validation.
--HG--
extra : convert_revision : 8c112c958f36b785390c46e70a889a79c6bea015
output files and the output directory are are handled. Make
the output directory configuration via a command line parameter,
or an environment variable.
SConscript:
Add new output file stuff
base/misc.cc:
dev/simconsole.cc:
use new output file code
cpu/base_cpu.cc:
use new output file code to generate output streams
dev/etherdump.cc:
use the output file code to find the output directory
use a real stream instead of a pointer
dev/etherdump.hh:
use a real stream instead of a pointer
objects/Root.mpy:
output_dir and config_output_file are not longer configured here.
sim/main.cc:
- Completely rework the command line argument passing to deal with
changes in python and output files.
- Update help output to reflect changes.
- Remove all direct support for .ini files. They are strictly
for intermediate representation.
- Remove the --foo:bar=blah syntax for .ini files and add --foo.bar=blah
syntax for python. This will generate: foo.bar = 'blah' in the python
script.
- Add '-d' to set the output directory.
- Use new output file code to access the output stream.
sim/serialize.cc:
use the new code to find the output directory
sim/universe.cc:
Get rid of makeOutputStream. Use the new output file code.
Remove output_dir and config_output_file as parameters.
--HG--
extra : convert_revision : df2f0e13d401c3a60cae1239aa1ec3511721544d
sim/pyconfig/m5config.py:
When getting all values, make sure we get the ones that are
parameter defaults as well.
--HG--
extra : convert_revision : 2b1c4b2f27dfab17ef9df18d7e5936e4a00bb12e
