Commit graph

1378 commits

Author SHA1 Message Date
Kevin Lim 64b4572c3e Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head

--HG--
extra : convert_revision : a250eed999be9b8acd6f420fdfe8f1b02905beb1
2007-04-09 14:30:49 -04:00
Kevin Lim 0cc343d41d Fix bug when blocking due to no free registers.
--HG--
extra : convert_revision : a1a218d3294515184689041487057495223360b7
2007-04-09 14:29:59 -04:00
Gabe Black f53d2ccbfc Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 1396ed5b264d29377ef9793a763225a93181f65f
2007-04-09 07:59:57 +00:00
Gabe Black 85f9213b8a Accidentally didn't save when moving the specialization code out of here.
--HG--
extra : convert_revision : 1ffe0c497e10fef1eb84b3c97c00b98d820fbb97
2007-04-09 01:08:05 +00:00
Gabe Black c7bb106886 Take into account that the flattened integer register space is a different size than the architected one. Also fixed some asserts.
--HG--
extra : convert_revision : 26e7863919d1b976ba8cad747af475a6f18e9440
2007-04-08 23:31:11 +00:00
Gabe Black d29979b043 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : dba3542ab73cc8ae46347a14ae4c133f1276011c
2007-04-08 01:54:08 +00:00
Gabe Black 3bb5fd8c44 Get the "hard" SPARC instructions working in o3. I don't like that the IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
--HG--
extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
2007-04-08 01:42:42 +00:00
Gabe Black 5d52cd6409 Move the instruction specialization stuff out of the microassembler file, and added some comments to main.isa
--HG--
extra : convert_revision : 1534ae7d5a9e95bf662d79a04f9286c227541c6c
2007-04-06 16:55:56 +00:00
Gabe Black a3ed19f82a Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 8e624bb95cb9f478ca7ac1dbbd64e20674e3e224
2007-04-06 16:39:47 +00:00
Gabe Black 59df95c7e6 Consolidated the microcode assembler to help separate it from more x86-centric stuff.
--HG--
extra : convert_revision : 5e7e8026e24ce44a3dac4a358e0c3e5560685958
2007-04-06 16:39:25 +00:00
Gabe Black 2a1c102f25 Refactored the x86 isa description some more. There should be more seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.
--HG--
rename : src/arch/x86/isa/formats/macroop.isa => src/arch/x86/isa/macroop.isa
extra : convert_revision : 5ab40eedf574fce438d9fe90e00a496dc95c8bcf
2007-04-06 16:00:56 +00:00
Gabe Black 75e8838ba4 Clean up the code a little, fix (I think) a perceived problem with immediate sizes, and sign extend the 32-bit-acting-like-64-bit-immediates.
--HG--
extra : convert_revision : e59b747198cc79d50045bd2dc45b2e2b97bbffcc
2007-04-06 15:19:23 +00:00
Gabe Black e633e23a3a Add in a stub merging function
--HG--
extra : convert_revision : 15e3cdb4ebcd31bc44204687ba59dde00c56c6be
2007-04-06 15:16:36 +00:00
Gabe Black 47c24ff07a Clean up the macroop code.
--HG--
extra : convert_revision : 3cf83c3e038fece6190dbb91f56deb0498c9a70d
2007-04-06 15:15:36 +00:00
Gabe Black 3c9768e644 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : b7e89d32df946ea24c438292308f5fc8248f8bd9
2007-04-06 14:37:46 +00:00
Gabe Black 077183f7ec Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : efdbf9787383dc1df544b7276f8120285e69bf69
2007-04-05 11:35:31 +00:00
Gabe Black ff7b89beee The process of going from an instruction definition to an instruction to be returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst.
1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter.
2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number.
3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM.
4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s.
5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it.

In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/base.isa:
    Implemented polymorphic microops and changed around the microcode assembler syntax.

--HG--
extra : convert_revision : e341f7b8ea9350a31e586a3d33250137e5954f43
2007-04-04 23:35:20 +00:00
Gabe Black ab2bed349b Fix a regular expression problem when recognizing labels for string substitution.
--HG--
extra : convert_revision : ba398e1b434efda28882f159d5a4419302276371
2007-04-04 23:19:32 +00:00
Gabe Black a664017c2a Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : 81269f094834f43b4e908321bfce2e031b39d2a4
2007-04-04 20:50:49 +00:00
Kevin Lim 3d2a434e42 Updates for other ISA cpu_builders.
--HG--
extra : convert_revision : b02736c627bb9dcf87463a9133e04369b9f8fae2
2007-04-04 16:50:48 -04:00
Kevin Lim b247e02f6e Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head

--HG--
extra : convert_revision : 7181d8c2ee673322372484cf288a94ebd91b5265
2007-04-04 15:39:13 -04:00
Kevin Lim 6ff6621f20 Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
src/cpu/o3/alpha/cpu_impl.hh:
    Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.

--HG--
extra : convert_revision : 74f4b1f5fb6f95a56081f367cce7ff44acb5688a
2007-04-04 15:38:59 -04:00
Ali Saidi d9ab45d066 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : be37463ea3ca38ef02ae0b82da0752f240a530d0
2007-04-04 13:57:23 -04:00
Ali Saidi d0ea8ff088 The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter.
In this way a MemoryObject can keep a functional port around and give it to anyone who wants to do functional accesses rather
than creating a new one each time.

src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/cache_impl.hh:
    only keep around one func port we give to anyone who wants it. Otherwise we can run out of port ids reasonably quickly if
    a lot of functional accesses are happening (e.g. remote debugging, dprintk, etc)

--HG--
extra : convert_revision : 6a9e3e96f51cedaab6de1b36cf317203899a3716
2007-04-04 13:56:38 -04:00
Gabe Black 4285990a96 Reworking how x86's isa description works. I'm adopting the following definitions to make figuring out what's what a little easier:
MicroOp: A single operation actually implemented in hardware.
MacroOp: A collection of microops which are executed as a unit.
Instruction: An architected instruction which can be implemented with a macroop or a microop.

--HG--
extra : convert_revision : 1cfc8409cc686c75220767839f55a30551aa6f13
2007-04-04 14:31:59 +00:00
Gabe Black 7f5409f2ba Make "Name" really be the same as "name" with only the first letter capitalized. Before, it had the first letter capitalized but all the others lower case
--HG--
extra : convert_revision : bcbb28f2bf268765c1d37075a4417a4a6c1b9588
2007-04-04 14:28:43 +00:00
Gabe Black 65fedeb5a7 Made x86 ExtMachInsts distinguishable from each other by defining a real == and a real hash function.
--HG--
extra : convert_revision : 30f29a36f6ab44e67e62aaf81b685fbe1267c746
2007-04-04 14:27:00 +00:00
Gabe Black 6010c6ded4 Added all the different variations of the register names.
--HG--
extra : convert_revision : ff06bdca556a5e1a0dfe7978575c2277c30c002a
2007-04-04 14:25:36 +00:00
Kevin Lim 9e1f3bc11a Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head

--HG--
extra : convert_revision : 4a8cbb65b19636c31b5c6fd5f24c90f8f2148ed1
2007-04-04 00:14:44 -04:00
Gabe Black 10fe8b05db Made the "data" field of store queue entries into a character array. It's sized to match an IntReg which was what it used to be, but we might want to make it something architecture independent. All data is now endian converted before entering the store queue entries which simplifies store to load forwarding in "trans endian" simulations, and makes twin memory ops work.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
    fixed twin memory operations.

--HG--
extra : convert_revision : 8fb97f98e285cd22413e06e146fa82392ac2a590
2007-04-03 22:53:26 +00:00
Kevin Lim 98c8cd0b36 Fix a memory leak. Hopefully this fixes the longer running benchmarks.
--HG--
extra : convert_revision : 89eff82642ff181a9b95c77c4d2bf620ca837113
2007-04-03 14:25:24 -04:00
Gabe Black 93d4c624c5 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 7be8ebe55a7b11552d78701520f93aa86db1e501
2007-04-03 15:01:36 +00:00
Gabe Black 61c56ffeaf A batch of changes and fixes. Macroops are now generated automatically, multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.
--HG--
extra : convert_revision : 518059f47e11df50aa450d4a322ef2ac069c99c9
2007-04-03 15:01:09 +00:00
Gabe Black 0ce6936e7d Zero out ModRM if the byte isn't there, and fix some displacement size stuff.
--HG--
extra : convert_revision : f43abf33a223a665b30098c63011fb162200d5e6
2007-04-03 14:56:24 +00:00
Kevin Lim ec09e5ad6f Remove/comment out DPRINTFs that were causing a segfault.
The removed ones were unnecessary.  The commented out ones could be useful in the future, should this problem get fixed.  See flyspray task #243.

src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
    Remove/comment out DPRINTFs that were causing a segfault.

--HG--
extra : convert_revision : b5aeda1c6300dfde5e0a3e9b8c4c5f6fa00b9862
2007-04-02 13:55:45 -04:00
Kevin Lim 24cc5227af Fix up SPARC's CPU builder to match changes to Alpha's CPU builder.
--HG--
extra : convert_revision : ec2a739f1da07f0922c772e6998017995115ce80
2007-04-02 13:28:17 -04:00
Ali Saidi c46e946c94 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 2f7f50f4ad31f741c0c67db96e49d30ca078fc94
2007-03-29 22:01:34 -04:00
Ali Saidi 528694817f make serialization at least seem to work
--HG--
extra : convert_revision : cbfdb64f9a204670b8dd0294c74a17044b9f330c
2007-03-29 22:00:01 -04:00
Ali Saidi 8ca218cab5 get rid of CWP bounds warning...
--HG--
extra : convert_revision : 74df09341c091c2d6ca9b46c6a3521f22b48acf4
2007-03-29 15:57:11 -04:00
Gabe Black 7fcc9d2106 Made the MultiOp format do a little more. It now sets up single microop instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support.
--HG--
extra : convert_revision : 1a0a4b36afce8255e23e3cdd7a85c1392dda5f72
2007-03-29 17:57:19 +00:00
Gabe Black e67a207ad3 Add a microcode assembler. A microcode "program" is a series of statements. Each statement has an optional label at the beginning, a capitilized microcode class name which is roughly equivalent to a mnemonic in a regular ISA, and then an optional series of operands seperated by white space. The operands are either a decimal constant, a label, or a code fragment surrounded by non nested {}s. Labels are a letter or underscore followed by letters, underscores, or digits. The syntax for describing code segments might need to be changed if a need arrises to have {}s in the code itself.
--HG--
extra : convert_revision : 8e5cfdd1a3c9a7e3731fdf6acd615ee82ac2b9b7
2007-03-29 17:57:18 +00:00
Kevin Lim 5c3f724174 Override addPrivateSplitL1Caches function in order to automatically set the tgts_per_mshr of the caches to 20. This is needed otherwise things will potentially lock up when using the O3CPU because the caches can run out of targets, and then not respond.
Remove this hack once the caches eventually get fixed.

--HG--
extra : convert_revision : 8c61ac1b6182f57ebbe3bcfeddb5a4f4334d7bc0
2007-03-29 12:25:47 -04:00
Kevin Lim 80af6530f6 Update code so that the O3 CPU can handle not initially having anything hooked up to its ports. This fixes the segfault Ali recently found when using sampling.
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
    Update code so that the O3 CPU can handle not initially having anything hooked up to its ports.

--HG--
extra : convert_revision : 04bcef44e754735d821509ebd69b0ef9c8ef8e2c
2007-03-29 12:02:57 -04:00
Gabe Black 14a7cda195 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 849b63ae1300e240082da19dfeb283cdeeb80aef
2007-03-29 00:51:34 -07:00
Gabe Black 77ce05f478 Fidget with the syntax of the MultiOp format in anticipation of making it actually work.
--HG--
extra : convert_revision : f62a1f035cc11677df8eb5a839ca1247d819fab3
2007-03-29 00:50:54 -07:00
Gabe Black fd77212b72 Add code to generate register and immediate based integer op microop classes.
--HG--
extra : convert_revision : 718f941da74dd3b4557cd21e1772879ac21aa9c6
2007-03-29 00:49:53 -07:00
Gabe Black 0d5f6167ff Allow "let" blocks to add code to the output files.
--HG--
extra : convert_revision : 0ffddb2b40dccbf2a3790464c843cfc1b43eaa02
2007-03-29 00:47:46 -07:00
Ron Dreslinski 8a674bed5c Call compare and Swap on the target, not the response.
--HG--
extra : convert_revision : 522805fe2c9abaa5ba0d9262ad98f841d90f6452
2007-03-28 14:38:11 -05:00
Ali Saidi e95bc9d8f9 some more fixes... non-tso stuff seems to work
--HG--
extra : convert_revision : da604d20443376d04826397d0aaff0bdd744053b
2007-03-27 20:44:21 -04:00
Ron Dreslinski 55614caecc Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head

--HG--
extra : convert_revision : 45b64b1564f0e4958d8441455f87b2b185324d55
2007-03-27 17:06:07 -05:00