Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 8e624bb95cb9f478ca7ac1dbbd64e20674e3e224
This commit is contained in:
Gabe Black
commit
a3ed19f82a
11 changed files with 167 additions and 148 deletions
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|
@ -79,6 +79,13 @@ output header {{
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void printReg(std::ostream &os, int reg) const;
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void printSrcReg(std::ostream &os, int reg) const;
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void printDestReg(std::ostream &os, int reg) const;
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inline uint64_t merge(uint64_t into, uint64_t val, int size) const
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{
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//FIXME This needs to be significantly more sophisticated
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return val;
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}
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};
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}};
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@ -95,9 +95,6 @@
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//malfunction of the decode mechanism.
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##include "error.isa"
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//Include code to build up macro op instructions
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##include "macroop.isa"
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//Include a format which implements a batch of instructions which do the same
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//thing on a variety of inputs
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##include "multi.isa"
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@ -55,16 +55,20 @@
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//
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// Authors: Gabe Black
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////////////////////////////////////////////////////////////////////
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//
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// Instructions that do the same thing to multiple sets of arguments.
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//
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// Execute method for macroops.
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def template MacroExecPanic {{
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Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
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{
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panic("Tried to execute macroop directly!");
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M5_DUMMY_RETURN
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}
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}};
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output header {{
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// Base class for most macroops, except ones that need to commit as
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// they go.
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class X86MacroInst : public X86StaticInst
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class X86MacroInst : public StaticInst
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{
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protected:
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const uint32_t numMicroOps;
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@ -72,7 +76,7 @@ output header {{
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//Constructor.
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X86MacroInst(const char *mnem, ExtMachInst _machInst,
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uint32_t _numMicroOps)
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: X86StaticInst(mnem, _machInst, No_OpClass),
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: StaticInst(mnem, _machInst, No_OpClass),
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numMicroOps(_numMicroOps)
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{
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assert(numMicroOps);
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@ -85,9 +89,6 @@ output header {{
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delete [] microOps;
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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StaticInstPtr * microOps;
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StaticInstPtr fetchMicroOp(MicroPC microPC)
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@ -96,21 +97,7 @@ output header {{
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return microOps[microPC];
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}
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%(BasicExecPanic)s
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};
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// Base class for macroops which commit as they go. This is for
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// instructions which can be partially completed like those with the
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// rep prefix. This prevents those instructions from overflowing
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// buffers with uncommitted microops.
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class X86RollingMacroInst : public X86MacroInst
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{
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protected:
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//Constructor.
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X86RollingMacroInst(const char *mnem, ExtMachInst _machInst,
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uint32_t _numMicroOps)
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: X86MacroInst(mnem, _machInst, numMicroOps)
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{}
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%(MacroExecPanic)s
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};
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}};
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@ -121,34 +108,24 @@ def template MacroConstructor {{
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{
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%(constructor)s;
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//alloc_micro_ops is the code that sets up the microOps
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//array in the parent class. This hook will hopefully
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//allow all that to be automated.
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//array in the parent class.
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%(alloc_micro_ops)s;
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setMicroFlags();
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}
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}};
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let {{
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def genMacroOp(name, Name, ops, rolling = False):
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def genMacroOp(name, Name, opSeq):
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baseClass = 'X86MacroInst'
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if rolling:
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baseClass = 'X86RollingMacroInst'
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numMicroOps = len(ops)
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numMicroOps = len(opSeq.ops)
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allocMicroOps = ''
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micropc = 0
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allocMicroOps += \
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"microOps[0] = %s;\n" % \
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op.getAllocator(True, not rolling, True, False)
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micropc += 1
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if numMicroOps > 2:
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for op in ops[1:-1]:
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allocMicroOps += \
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"microOps[%d] = %s;\n" % \
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(micropc, op.getAllocator(True, not rolling, False, False))
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micropc += 1
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allocMicroOps += \
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"microOps[%d] = %s;\n" % \
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op.getAllocator(True, not rolling, False, True)
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for op in opSeq.ops:
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allocMicroOps += \
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"microOps[%d] = %s;\n" % \
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(micropc, op.getAllocator(True, op.delayed,
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micropc == 0,
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micropc == numMicroOps - 1))
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micropc += 1
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iop = InstObjParams(name, Name, baseClass,
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{'code' : '', 'num_micro_ops' : numMicroOps,
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'alloc_micro_ops' : allocMicroOps})
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@ -72,26 +72,34 @@
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namespace X86ISA;
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//Include the simple microcode assembler
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//Include the simple microcode assembler. This will hopefully stay
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//unspecialized for x86 and can later be made available to other ISAs.
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##include "microasm.isa"
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//Include the bitfield definitions
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##include "bitfields.isa"
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//Include the operand_types and operand definitions
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##include "operands.isa"
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//Include code to build macroops.
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##include "macroop.isa"
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//Include the base class for x86 instructions, and some support code
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//Code in this file should be general and useful everywhere
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##include "base.isa"
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//Include the instruction definitions
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##include "insts/insts.isa"
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//Include the definitions for the instruction formats
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##include "formats/formats.isa"
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//Include the definitions of the micro ops
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//Include the operand_types and operand definitions. These are needed by
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//the microop definitions.
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##include "operands.isa"
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//Include the definitions of the micro ops.
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//These are StaticInst classes which stand on their own and make up an
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//internal instruction set.
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##include "microops/microops.isa"
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//Include the instruction definitions which are microop assembler programs.
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##include "insts/insts.isa"
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//Include the bitfield definitions
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##include "bitfields.isa"
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//Include the decoder definition
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##include "decoder/decoder.isa"
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@ -61,23 +61,6 @@
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// variety of operands
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//
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let {{
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# This builds either a regular or macro op to implement the sequence of
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# ops we give it.
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def genInst(name, Name, ops):
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# If we can implement this instruction with exactly one microop, just
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# use that directly.
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newStmnt = ''
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if len(ops) == 1:
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decode_block = "return (X86StaticInst *)(%s);" % \
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ops[0].getAllocator()
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return ('', '', decode_block, '')
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else:
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# Build a macroop to contain the sequence of microops we've
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# been given.
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return genMacroOp(name, Name, ops)
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}};
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let {{
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# This code builds up a decode block which decodes based on switchval.
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# vals is a dict which matches case values with what should be decoded to.
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@ -187,14 +170,8 @@ let {{
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# At this point, we've built up "code" to have all the necessary extra
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# instructions needed to implement whatever types of operands were
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# specified. Now we'll assemble it it into a microOp sequence.
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ops = assembleMicro(code)
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# Build a macroop to contain the sequence of microops we've
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# constructed. The decode block will be used to fill in our
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# inner decode structure, and the rest will be concatenated and
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# passed back.
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return genInst(name, Name, ops)
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# specified. Now we'll assemble it it into a StaticInst.
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return assembleMicro(name, Name, code)
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}};
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////////////////////////////////////////////////////////////////////
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@ -202,6 +179,13 @@ let {{
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// The microcode assembler
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//
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let {{
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# These are used when setting up microops so that they can specialize their
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# base class template properly.
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RegOpType = "RegisterOperand"
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ImmOpType = "ImmediateOperand"
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}};
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let {{
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class MicroOpStatement(object):
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def __init__(self):
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@ -242,19 +226,9 @@ let {{
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return 'new %s%s(machInst%s%s)' % (self.className, signature, self.microFlagsText(microFlags), args)
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}};
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let {{
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def buildLabelDict(ops):
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labels = {}
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micropc = 0
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for op in ops:
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if op.label:
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labels[op.label] = count
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micropc += 1
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return labels
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}};
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let{{
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def assembleMicro(code):
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def assembleMicro(name, Name, code):
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# This function takes in a block of microcode assembly and returns
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# a python list of objects which describe it.
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@ -341,7 +315,13 @@ let{{
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lineMatch = lineRe.search(code)
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# Decode the labels into displacements
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labels = buildLabelDict(statements)
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labels = {}
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micropc = 0
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for statement in statements:
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if statement.label:
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labels[statement.label] = count
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micropc += 1
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micropc = 0
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for statement in statements:
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for arg in statement.args:
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@ -353,5 +333,15 @@ let{{
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# micropc + 1 + displacement.
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arg["operandImm"] = labels[arg["operandLabel"]] - micropc - 1
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micropc += 1
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return statements
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# If we can implement this instruction with exactly one microop, just
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# use that directly.
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if len(statements) == 1:
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decode_block = "return %s;" % \
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statements[0].getAllocator()
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return ('', '', decode_block, '')
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else:
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# Build a macroop to contain the sequence of microops we've
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# been given.
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return genMacroOp(name, Name, statements)
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}};
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|
|
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@ -63,12 +63,15 @@ output header {{
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};
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}};
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//A class which is the base of all x86 micro ops it provides a function to
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//A class which is the base of all x86 micro ops. It provides a function to
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//set necessary flags appropriately.
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output header {{
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class X86MicroOpBase : public X86StaticInst
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{
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protected:
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uint8_t opSize;
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uint8_t addrSize;
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X86MicroOpBase(bool isMicro, bool isDelayed,
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bool isFirst, bool isLast,
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const char *mnem, ExtMachInst _machInst,
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@ -94,6 +97,7 @@ def template BaseMicroOpTemplateDeclare {{
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let {{
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def buildBaseMicroOpTemplate(Name, numParams):
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assert(numParams > 0)
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signature = "<"
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signature += "int SignatureOperandTypeSpecifier0"
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for count in xrange(1,numParams):
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@ -102,10 +106,9 @@ let {{
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signature += ">"
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subs = {"signature" : signature, "class_name" : Name}
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return BaseMicroOpTemplateDeclare.subst(subs)
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}};
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RegOpType = "RegisterOperand"
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ImmOpType = "ImmediateOperand"
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let {{
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def buildMicroOpTemplateDict(*params):
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signature = "<"
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if len(params):
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|
|
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@ -117,37 +117,33 @@ namespace X86ISA
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//Operand size override prefixes
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case OperandSizeOverride:
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DPRINTF(Predecoder, "Found operand size override prefix.\n");
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emi.legacy.op = true;
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break;
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case AddressSizeOverride:
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DPRINTF(Predecoder, "Found address size override prefix.\n");
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emi.legacy.addr = true;
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break;
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//Segment override prefixes
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case CSOverride:
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DPRINTF(Predecoder, "Found cs segment override.\n");
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break;
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case DSOverride:
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DPRINTF(Predecoder, "Found ds segment override.\n");
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break;
|
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case ESOverride:
|
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DPRINTF(Predecoder, "Found es segment override.\n");
|
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break;
|
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case FSOverride:
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DPRINTF(Predecoder, "Found fs segment override.\n");
|
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break;
|
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case GSOverride:
|
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DPRINTF(Predecoder, "Found gs segment override.\n");
|
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break;
|
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case SSOverride:
|
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DPRINTF(Predecoder, "Found ss segment override.\n");
|
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DPRINTF(Predecoder, "Found segment override.\n");
|
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emi.legacy.seg = prefix;
|
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break;
|
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case Lock:
|
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DPRINTF(Predecoder, "Found lock prefix.\n");
|
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emi.legacy.lock = true;
|
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break;
|
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case Rep:
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DPRINTF(Predecoder, "Found rep prefix.\n");
|
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emi.legacy.rep = true;
|
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break;
|
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case Repne:
|
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DPRINTF(Predecoder, "Found repne prefix.\n");
|
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emi.legacy.repne = true;
|
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break;
|
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case RexPrefix:
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DPRINTF(Predecoder, "Found Rex prefix %#x.\n", nextByte);
|
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|
|
@ -198,16 +194,36 @@ namespace X86ISA
|
|||
displacementCollected = 0;
|
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emi.displacement = 0;
|
||||
|
||||
//Figure out the effective operand size. This can be overriden to
|
||||
//a fixed value at the decoder level.
|
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if(/*FIXME long mode*/1)
|
||||
{
|
||||
if(emi.rex && emi.rex.w)
|
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emi.opSize = 3; // 64 bit operand size
|
||||
else if(emi.legacy.op)
|
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emi.opSize = 1; // 16 bit operand size
|
||||
else
|
||||
emi.opSize = 2; // 32 bit operand size
|
||||
}
|
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else if(/*FIXME default 32*/1)
|
||||
{
|
||||
if(emi.legacy.op)
|
||||
emi.opSize = 1; // 16 bit operand size
|
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else
|
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emi.opSize = 2; // 32 bit operand size
|
||||
}
|
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else // 16 bit default operand size
|
||||
{
|
||||
if(emi.legacy.op)
|
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emi.opSize = 2; // 32 bit operand size
|
||||
else
|
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emi.opSize = 1; // 16 bit operand size
|
||||
}
|
||||
|
||||
//Figure out how big of an immediate we'll retreive based
|
||||
//on the opcode.
|
||||
int immType = ImmediateType[
|
||||
emi.opcode.num - 1][nextByte];
|
||||
if(0) //16 bit mode
|
||||
immediateSize = ImmediateTypeToSize[0][immType];
|
||||
else if(!(emi.rex & 0x4)) //32 bit mode
|
||||
immediateSize = ImmediateTypeToSize[1][immType];
|
||||
else //64 bit mode
|
||||
immediateSize = ImmediateTypeToSize[2][immType];
|
||||
int immType = ImmediateType[emi.opcode.num - 1][nextByte];
|
||||
immediateSize = SizeTypeToSize[emi.opSize - 1][immType];
|
||||
|
||||
//Determine what to expect next
|
||||
if (UsesModRM[emi.opcode.num - 1][nextByte]) {
|
||||
|
|
@ -351,6 +367,16 @@ namespace X86ISA
|
|||
|
||||
if(immediateSize == immediateCollected)
|
||||
{
|
||||
//XXX Warning! The following is an observed pattern and might
|
||||
//not always be true!
|
||||
|
||||
//Instructions which use 64 bit operands but 32 bit immediates
|
||||
//need to have the immediate sign extended to 64 bits.
|
||||
//Instructions which use true 64 bit immediates won't be
|
||||
//affected, and instructions that use true 32 bit immediates
|
||||
//won't notice.
|
||||
if(immediateSize == 4)
|
||||
emi.immediate = sext<32>(emi.immediate);
|
||||
DPRINTF(Predecoder, "Collected immediate %#x.\n",
|
||||
emi.immediate);
|
||||
emiIsReady = true;
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ namespace X86ISA
|
|||
static const uint8_t Prefixes[256];
|
||||
static const uint8_t UsesModRM[2][256];
|
||||
static const uint8_t ImmediateType[2][256];
|
||||
static const uint8_t ImmediateTypeToSize[3][10];
|
||||
static const uint8_t SizeTypeToSize[3][10];
|
||||
|
||||
protected:
|
||||
ThreadContext * tc;
|
||||
|
|
|
|||
|
|
@ -141,7 +141,7 @@ namespace X86ISA
|
|||
}
|
||||
};
|
||||
|
||||
enum ImmediateTypes {
|
||||
enum SizeType {
|
||||
NoImm,
|
||||
NI = NoImm,
|
||||
ByteImm,
|
||||
|
|
@ -158,19 +158,19 @@ namespace X86ISA
|
|||
VW = VWordImm,
|
||||
ZWordImm,
|
||||
ZW = ZWordImm,
|
||||
Pointer,
|
||||
PO = Pointer,
|
||||
//The enter instruction takes -2- immediates for a total of 3 bytes
|
||||
Enter,
|
||||
EN = Enter
|
||||
EN = Enter,
|
||||
Pointer,
|
||||
PO = Pointer
|
||||
};
|
||||
|
||||
const uint8_t Predecoder::ImmediateTypeToSize[3][10] =
|
||||
const uint8_t Predecoder::SizeTypeToSize[3][10] =
|
||||
{
|
||||
// noimm byte word dword qword oword vword zword enter
|
||||
{0, 1, 2, 4, 8, 16, 2, 2, 3, 4}, //16 bit
|
||||
{0, 1, 2, 4, 8, 16, 4, 4, 3, 6}, //32 bit
|
||||
{0, 1, 2, 4, 8, 16, 4, 8, 3, 0} //64 bit
|
||||
// noimm byte word dword qword oword vword zword enter pointer
|
||||
{0, 1, 2, 4, 8, 16, 2, 2, 3, 4 }, //16 bit
|
||||
{0, 1, 2, 4, 8, 16, 4, 4, 3, 6 }, //32 bit
|
||||
{0, 1, 2, 4, 8, 16, 4, 8, 3, 0 } //64 bit
|
||||
};
|
||||
|
||||
//This table determines the immediate type. The first index is the
|
||||
|
|
|
|||
|
|
@ -70,25 +70,31 @@ namespace X86ISA
|
|||
typedef uint64_t MachInst;
|
||||
|
||||
enum Prefixes {
|
||||
NoOverride = 0,
|
||||
CSOverride = 1,
|
||||
DSOverride = 2,
|
||||
ESOverride = 3,
|
||||
FSOverride = 4,
|
||||
GSOverride = 5,
|
||||
SSOverride = 6,
|
||||
//The Rex prefix obviously doesn't fit in with the above, but putting
|
||||
//it here lets us save double the space the enums take up.
|
||||
RexPrefix = 7,
|
||||
NoOverride,
|
||||
CSOverride,
|
||||
DSOverride,
|
||||
ESOverride,
|
||||
FSOverride,
|
||||
GSOverride,
|
||||
SSOverride,
|
||||
RexPrefix,
|
||||
OperandSizeOverride,
|
||||
AddressSizeOverride,
|
||||
Lock,
|
||||
Rep,
|
||||
Repne
|
||||
};
|
||||
|
||||
BitUnion8(LegacyPrefixVector)
|
||||
Bitfield<7> repne;
|
||||
Bitfield<6> rep;
|
||||
Bitfield<5> lock;
|
||||
Bitfield<4> addr;
|
||||
Bitfield<3> op;
|
||||
//There can be only one segment override, so they share the
|
||||
//first 3 bits in the legacyPrefixes bitfield.
|
||||
SegmentOverride = 0x7,
|
||||
OperandSizeOverride = 8,
|
||||
AddressSizeOverride = 16,
|
||||
Lock = 32,
|
||||
Rep = 64,
|
||||
Repne = 128
|
||||
};
|
||||
Bitfield<2,0> seg;
|
||||
EndBitUnion(LegacyPrefixVector)
|
||||
|
||||
BitUnion8(ModRM)
|
||||
Bitfield<7,6> mod;
|
||||
|
|
@ -118,7 +124,7 @@ namespace X86ISA
|
|||
struct ExtMachInst
|
||||
{
|
||||
//Prefixes
|
||||
uint8_t legacy;
|
||||
LegacyPrefixVector legacy;
|
||||
Rex rex;
|
||||
//This holds all of the bytes of the opcode
|
||||
struct
|
||||
|
|
@ -140,6 +146,10 @@ namespace X86ISA
|
|||
//Immediate fields
|
||||
uint64_t immediate;
|
||||
uint64_t displacement;
|
||||
|
||||
//The effective operand size.
|
||||
uint8_t opSize;
|
||||
//The
|
||||
};
|
||||
|
||||
inline static std::ostream &
|
||||
|
|
|
|||
|
|
@ -78,7 +78,8 @@ namespace __hash_namespace {
|
|||
((uint64_t)emi.opcode.prefixA << 16) |
|
||||
((uint64_t)emi.opcode.prefixB << 8) |
|
||||
((uint64_t)emi.opcode.op)) ^
|
||||
emi.immediate ^ emi.displacement;
|
||||
emi.immediate ^ emi.displacement ^
|
||||
emi.opSize;
|
||||
};
|
||||
};
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue