if Tru64 is to continue to be supported on Turbolaser) and fixed
translation of physical addresses by clearing PA<42:35> when the real
uncachable bit (43) is set
arch/alpha/ev5.hh:
Change to support 256 ASNs and seperate VA_SPACE checks for EV5 and EV6
also add support proper translation of uncacheable physical addresses
dev/ide_ctrl.cc:
Fix to work with real address translation
--HG--
extra : convert_revision : aa3d1c284b8271d4763a8da2509c91bbcf83189a
out CPU model. ISA description now generates multiple
output source files to (in theory) reduce compilation time.
arch/alpha/isa_desc:
Update for parser changes. Move most constructors
out of class declarations (which are now in decoder.hh)
and into decoder.cc. Move all execute() methods into
exec output.
arch/isa_parser.py:
Significant changes to make ISA description completely
independent of CPU model, and isolate model-dependent parts
of parser into one little class (CpuModel). Also split up code
output into multiple files (a header, a main source file, and
per-cpu execute() method files).
Noticeable changes to language as a result. See updated Doxygen
documentation.
cpu/simple_cpu/simple_cpu.hh:
SimpleCPUExecContext typedef no longer needed.
Add forward declaration of Process.
cpu/static_inst.hh:
SimpleCPUExecContext and FullCPUExecContext typedefs no longer needed.
Make eaCompInst() and memAccInst() return const refs.
--HG--
extra : convert_revision : 71471f267804fafd0a881bac7445677e76334daf
a pointer to an object that lives inside simulated memory.
Useful for doing a bit of analysis of what's going on in
the running kernel.
--HG--
extra : convert_revision : d78089cce5ec4334483a710ba512eaf18d9b0319
arch/alpha/isa_desc:
remove the annotation junk
Move some code to AlphaPseudo where it belongs
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
remove the annotation junk
add pseudo instruction code that was previously misplaced
--HG--
extra : convert_revision : 97db8402aa34e0bdf044b138c52331fc9e714986
switches. (Makes other uncommitted code easier to merge.)
arch/alpha/ev5.cc:
pass the address of both the old an new pcbb on context
switches
--HG--
extra : convert_revision : bff8c8d1b532ad5f9af6270169bbfb1b5c05256a
arch/alpha/alpha_memory.cc:
change to the main m5 tree convention for naming
base/traceflags.py:
add ide and pciconfigall traceflags
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kill some old binning styled stuff
--HG--
extra : convert_revision : 0558878906817975a714b1c7c08f9ee405468535
(Still not perfect though.)
arch/alpha/isa_desc:
Do a better job of factoring out CPU model. (Still not perfect though.)
Pull execute() methods out of class declarations into separate section
of file, allowing (1) easier replication for different CPU models and
(2) a path to putting them all in a separate file. Force all instruction
execution context into a single model-dependent class (SimpleCPU itself
for SimpleCPU, DynInst for FullCPU).
arch/isa_parser.py:
Do a better job of factoring out CPU model. (Still not perfect though.)
Pull execute() methods out of class declarations into separate section
of file, allowing (1) easier replication for different CPU models and
(2) a path to putting them all in a separate file.
Also restructure top level to allow parser to run under interactive
interpreter session for easier debugging.
cpu/exec_context.hh:
Add a few new methods to clean up isa_desc.
cpu/simple_cpu/simple_cpu.cc:
cpu/static_inst.hh:
StaticInst::execute no longer takes a CPU and an ExecContext,
just a unified FooCPUExecContext.
cpu/simple_cpu/simple_cpu.hh:
Add methods to redirect calls to ExecContext so SimpleCPU
can act as sole instruction execution context for itself.
Typedef SimpleCPU to SimpleCPUExecContext.
--HG--
extra : convert_revision : ecc445503bc585585da5663fe61796580e744da6
Added function to skip determine_cpu_caches(). We may have to update this in the
future: see note below.
arch/alpha/alpha_memory.cc:
dev/ide_ctrl.cc:
dev/tsunamireg.h:
Added ULL for 64bit ints
kern/linux/linux_system.cc:
Added a function to skip determine_cpu_caches, right now it is only used for
printing in proc, however in the future we may either want to implement the SC_CTL
IPR register or manually set alpha_l1i_cacheshape, alpha_l1d_cacheshape,
alpha_l2_cacheshape, alpha_l3_cacheshape to ((size << 10) | (linesize>>1)<<4 | way)
kern/linux/linux_system.hh:
added event to skip determine_cpu_caches()
--HG--
extra : convert_revision : 1065f2091bbe6832b730af490f5b4672c2afedce
arch/alpha/vtophys.cc:
Removed buggy code that tries to fix PAL addresses (may cause problems
while trying to debug in PAL code, but that should do this fix outside
of vtophys)
base/loader/symtab.cc:
base/loader/symtab.hh:
cpu/exetrace.cc:
Changed InstExec traces to always print a symbol name
dev/ide_ctrl.cc:
dev/ide_disk.cc:
Tabs
dev/ide_disk.hh:
Change buffer size
dev/tsunami_pchip.cc:
Fix translatePciToDma to support scatter gather mapping
kern/linux/linux_system.cc:
Force simulator to wait until remote debugger attaches (should be removed
or turned on/off with a flag)
--HG--
extra : convert_revision : 1d08aebe3f448c87a963dd613de3e2e0cff0d48d
Add support for generic visitors for stats and use them
to implement independent output functions.
Support for mysql output and some initial code for hacking
on mysql output with python
arch/alpha/pseudo_inst.cc:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/sat_counter.cc:
base/sat_counter.hh:
cpu/simple_cpu/simple_cpu.cc:
kern/tru64/tru64_events.cc:
sim/main.cc:
sim/process.cc:
sim/process.hh:
sim/sim_events.cc:
sim/sim_object.cc:
sim/system.hh:
update for changes in stats package
base/statistics.cc:
move the python output code to base/stats/puthon.(cc|hh)
and reimplement it as a visitor.
move the text output code to base/stats/text.(cc|hh) and
reimplement it as a visitor.
move the database stuff into base/stats/statdb.(cc|hh) and
get rid of the class. Put everything as globals in the
Statistics::Database namespace.
allocate unique ids for all stats.
directly implement the check routine and get rid of the
various dumping routines since they're now in separate files.
make sure that no two stats have the same name
clean up some loops
base/statistics.hh:
major changes to the statistics package again
lots of code was factored out of statistics.hh into several
separate files in base/stats/ (this will continue)
There are now two Stat package types Result and Counter that
are specified to allow the user to keep the counted type
separate from the result type. They are currently both doubles
but that's an experiment. There is no more per stat ability to
set the type. Statistics::Counter is not the same as Counter!
Implement a visitor for statistics output so that new output
types can be implemented independently from the stats package
itself.
Add a unique id to each stat so that it can be used to keep
track of stats more simply. This number can also be used in
debugging problems with stats.
Tweak the bucket size stuff a bit to make it work better.
fixed VectorDist size bug
cpu/memtest/memtest.cc:
Fix up for changes in stats package
Don't use value() since it doesn't work with binning. If you
want a number as a stat, and to use it in the program itself,
you really want two separate variables, one that's a stat,
and one that's not.
cpu/memtest/memtest.hh:
Fix up for changes in stats package
test/Makefile:
Try to build stuff now that directories matter
test/stattest.cc:
test all new output types
choose which one with command line options
--HG--
extra : convert_revision : e3a3f5f0828c67c0e2de415d936ad240adaddc89
Also missed renames in a bunch of config files somehow.
(See previous changeset for list of renames.)
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/faults.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).
--HG--
extra : convert_revision : b2c6ca0916b72b59895520fcacaf028667560a0d
configuration unnecessarily awkward. Biggest changes are:
- External and internal object names now match in all cases. The
macros still allow them to be different; the only reason I didn't
get rid of that is that the macros themselves should be going away
soon. In the few conflicting cases, I sometimes renamed the C++ object
and sometimes renamed the config object. The latter sets of substitions
are:
s/BaseBus/Bus/;
s/MemoryObject/FunctionalMemory/;
s/MemoryControl/MemoryController/;
s/FUPool/FuncUnitPool/;
- SamplingCPU is temporarily broken... we need to change the model
of how this works in the .ini file. Having it as a CPU proxy is
really awkward.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/simple_cpu/simple_cpu.cc:
sim/process.cc:
Rename objects to match config name.
cpu/base_cpu.cc:
Uncomment SimObject define since SamplingCPU no longer
does this for us.
dev/ethertap.cc:
Use unsigned instead of uint16_t for params.
kern/tru64/tru64_system.cc:
Use unsigned instead of uint64_t for init_param param.
test/paramtest.cc:
Fix old SimObjectParam.
--HG--
extra : convert_revision : 378ebbc6a71ad0694501d09979a44d111a59e8dc
arch/alpha/isa_desc:
Need to return fault for copy operations.
cpu/exec_context.hh:
Add temporary storage to pass source address from copy load to copy store
cpu/simple_cpu/simple_cpu.cc:
Implement copy functions.
cpu/simple_cpu/simple_cpu.hh:
Return fault
--HG--
extra : convert_revision : 98e5ce563449d6057ba45c70eece9235f1649a90
arch/alpha/isa_desc:
Just to make sure, remove the new copy instructions until everything works.
--HG--
extra : convert_revision : cdd3d4c8fa415175aaee04f4a99340dcf82dbc3a
arch/alpha/ev5.cc:
actually implement the cycle count register
arch/alpha/isa_desc:
the rpcc instruction really just reads the cycle count
register
--HG--
extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1
arch/alpha/ev5.cc:
Handle writing IPR_CC and IPR_CC_CTL slightly more intelligently.
(Very slightly).
arch/alpha/isa_desc:
Upper half of rpcc result comes from value written
to IPR_CC, not actual cycle counter.
--HG--
extra : convert_revision : 7161989db8a3f040d0558e2e5a1a162ed1cb4125
arch/alpha/isa_desc:
Add copy_load and copy_store insts (ldf and stf respectively)
cpu/simple_cpu/simple_cpu.hh:
Add copy functions to SimpleCPU as well
--HG--
extra : convert_revision : 1fa041da582b418c47d4eefc22dabba978a50e2d
arch/alpha/osfpal.cc:
Add a string for copypal.
arch/alpha/osfpal.hh:
Add a code for copypal.
cpu/static_inst.hh:
Add an IsCopy flag.
--HG--
extra : convert_revision : 19e3d90368454806029ad492eace19cd0924fe9f
it actually do something on FullCPU. Still disabled, as it
causes detailed-boot to hang when you turn it on.
arch/alpha/isa_desc:
Add EAComp and MemAcc pseudo-instructions to prefetch StaticInst.
cpu/simple_cpu/simple_cpu.hh:
Changed prefetch() return type from Fault to void.
--HG--
extra : convert_revision : c7cb42682bfea6af117c87d4dfdb06176b6fe6b7
physical addressing. This has the uncacheable bit as bit 40 as opposed
to bit 39. Additionally, we now support (at least superficially) a 44-bit
physical address. To deal with superpage access in this scheme, any super
page access with either bit 39 or 40 set is sign extended.
--HG--
extra : convert_revision : 05ddbcb9a6a92481109a63b261743881953620ab
tlb index calls that are called from ExecContext::readIpr
arch/alpha/ev5.cc:
Fix misspeculation bugs for misspeculated IPR accesses
--HG--
extra : convert_revision : c9ffcf9ef8123dfcaee1606c05aee8ad60d893d7
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
Fix to remote debugger while in PAL code
dev/pcidev.cc:
Remove extra debug printf
--HG--
extra : convert_revision : e64988846ad05cd3ddf47034d72d99dae3501591
arch/alpha/vtophys.cc:
fix up vtophys to deal with translations if there
is no ptbr, and to deal with PAL addresses
add ptomem which is just a wrapper for dma_addr
arch/alpha/vtophys.hh:
add ptomem which is a wrapper for dma_addr with the
same usage as vtomem
--HG--
extra : convert_revision : 1ae22073d400e87b708a4a7ef501124227fc6c39
benchmarks for alpha-linux.
arch/alpha/alpha_linux_process.cc:
Added some more ioctl commands to ignore.
Set unlink and rename to the new functions.
Ignore setrlimit, times and rt_sigaction.
Should eventually provide a function for times.
arch/alpha/alpha_tru64_process.cc:
Added some more ioctl commands to ignore.
Set unlink and rename to the new functions.
Ignore setrlimit.
sim/syscall_emul.cc:
Added implementations for unlink and rename.
sim/syscall_emul.hh:
Added unlink and rename functions.
Added a couple more ioctl requests to ignore.
Print out the PC of any ioctl commands that fail.
--HG--
extra : convert_revision : 8af21c7fa7d0645d3f9324c9ce70ad33590c3c8e
execution pipeline (Alpha trapb & excb).
Add support for write memory barriers (mostly impacts
store buffer).
Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.
arch/alpha/isa_desc:
Implement trapb, excb, mb, and wmb as insts with
no execution effect (empty execute() function) but
with flags that indicate their side effects.
Also make sure every instruction that needs to go to
the execute stage has a real opClass value, since we
are now using No_OpClass to signal insts that can get
dropped at dispatch.
StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
Add flags to indicate serializing insts (trapb, excb) and
memory and write barriers.
Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
Make name() return value const.
--HG--
extra : convert_revision : 39520e71469fa20e0a7446b2e06b494eec17a02c
arch/alpha/isa_desc:
Add missing branchTarget() method for indirect branches.
cpu/static_inst.hh:
Add comment clarifying when branchTarget() can be used
on indirect branches.
--HG--
extra : convert_revision : 0dcfb36a9792a338cefceb3d1501825abace7ac5
This avoids incrementing and decrementing the MemReq
reference counters on every call and return.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
Change MemReqPtr parameters to references.
--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
arch/alpha/isa_desc:
don't say warn: Warning:
base/misc.cc:
avoid printing two newlines in a row
sim/main.cc:
print out a message just before we enter the event queue
--HG--
extra : convert_revision : 2a824d4b67661903fc739a0fb0759aa91d72382c
arch/alpha/isa_traits.hh:
Add a constant for the maximum address value called MaxAddr.
--HG--
extra : convert_revision : 1371e8b713cc6ed134093e9c208db35dc9741ac7
Move global checkpoint-related functions and vars into Checkpoint class (as statics).
arch/alpha/pseudo_inst.cc:
dev/disk_image.cc:
Move global checkpoint-related functions and vars
into Checkpoint class (as statics).
sim/serialize.cc:
Move global checkpoint-related functions and vars
into Checkpoint class (as statics).
Checkpoint constructor now takes checkpoint directory name instead
of file name.
Make serialize:dir parameter actually set checkpoint directory name
instead of directory in which checkpoint directory is created. If
the value contains a '%', the curTick value is sprintf'd into the
format to create the directory name. The default is backwards compatible
with the old fixed name ("m5.%012d").
sim/serialize.hh:
Move global checkpoint-related functions and vars
into Checkpoint class (as statics).
Checkpoint constructor now takes checkpoint directory name instead
of file name.
--HG--
extra : convert_revision : d0aa87b62911f405a4f5811271b9e6351fdd9fe4
arch/alpha/alpha_tru64_process.cc:
So, I don't know why linux uses an off_t here.
I'm also not sure why linux defines an off_t to be a long
Let's just use long here since it works for linux, and that's
what bsd does
base/inifile.cc:
correct #include for OpenBSD
dev/disk_image.cc:
the correct type for this is streampos
--HG--
extra : convert_revision : f3ac3a3b8515d66e07ffb9780d8a9e387297b6a0
