Gabe Black
c3381167c9
ARM: Make the MPUIR register report that 1 unified data region is supported.
2010-06-02 12:58:10 -05:00
Gabe Black
3aa8faf177
ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.
2010-06-02 12:58:10 -05:00
Gabe Black
68f2908a70
ARM: Ignore/warn when CSSELR or CCSIDR are accessed.
...
These registers provide information about the caches. Since we can't provide
that information, these will be harmlessly inert.
2010-06-02 12:58:09 -05:00
Gabe Black
741b243260
ARM: Ignore/warn access to the bpimva registers.
2010-06-02 12:58:09 -05:00
Gabe Black
8a7f60194e
ARM: Ignore/warn on accesses to the dccmvac register.
2010-06-02 12:58:09 -05:00
Gabe Black
a483d44d9f
ARM: Ignore/warn on accesses to icimvau.
2010-06-02 12:58:09 -05:00
Gabe Black
630f309a77
ARM: Ignore/warn on iciallu.
2010-06-02 12:58:09 -05:00
Gabe Black
d618121670
ARM: Ignore/warn on ICIALLUIS.
2010-06-02 12:58:09 -05:00
Gabe Black
e658b6fed4
ARM: Add support for the clidr register.
...
This register will always report 0 caches as implemented. It's not clear how
to find out how many there really are when dealing with an arbitrary
hierarchy.
2010-06-02 12:58:09 -05:00
Gabe Black
896c7617c4
ARM: Decode the unimplemented data barrier CP15 accesses.
...
These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory
Barrier).
2010-06-02 12:58:09 -05:00
Gabe Black
af6b1667e9
ARM: Implement a stub of CPACR.
...
This register controls access to the coprocessors. This doesn't actually
implement it, it allows writes which don't turn anything off. In other words,
it allows the simulated program to ask for what it already has.
2010-06-02 12:58:09 -05:00
Gabe Black
35f0c01fea
ARM: Decode the unimplemented cp15 instruction barrier.
2010-06-02 12:58:08 -05:00
Gabe Black
7932b86298
ARM: Ignore accesses to DCCIMVAC.
2010-06-02 12:58:08 -05:00
Gabe Black
6ae4d34a12
ARM: Allow accesses to the software thread id registers.
2010-06-02 12:58:08 -05:00
Gabe Black
54850e4d23
ARM: Allow accesses to the contextidr register.
2010-06-02 12:58:08 -05:00
Gabe Black
221e0ac523
ARM: Warn about and ignore accesses to DCCISW.
...
This register is supposed to "Clean and invalidate data or unified cache line
by set/way." Since there isn't a good way to do that, we'll just ignore these
and warn about it.
2010-06-02 12:58:08 -05:00
Gabe Black
6aa229386d
ARM: Implement a function to decode CP15 registers to MiscReg indices.
2010-06-02 12:58:08 -05:00
Gabe Black
bd8812cf99
ARM: Replace the "never" condition with the "unconditional" condition.
2010-06-02 12:58:00 -05:00
Gabe Black
9ef82c0bc4
ARM: Track the current ISA mode using the PC.
2010-06-02 12:57:59 -05:00
Gabe Black
e2ab64543b
ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.
2009-11-14 19:22:30 -08:00
Gabe Black
2e28da5583
ARM: Implement fault classes.
...
Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
2009-11-10 20:34:38 -08:00
Gabe Black
d188821d37
ARM: Add in more bits for the mon mode.
2009-11-08 02:01:02 -08:00
Gabe Black
4079792f2b
ARM: Add in spots for the VFP control registers.
2009-07-27 00:53:10 -07:00
Gabe Black
38d8bc64ba
ARM: Fill out the printReg function.
2009-06-26 22:01:34 -07:00
Gabe Black
71e0d1ded2
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 09:21:07 -07:00
