Commit graph

3486 commits

Author SHA1 Message Date
Gabe Black
c77cb31473 Reorganized SPARC binaries
--HG--
rename : configs/test/hello_sparc => configs/test/sparc_tests/hello_sparc
extra : convert_revision : d8f36fc9b346f0e89dc8406403576e88bb2dc139
2006-07-22 17:30:50 -04:00
Gabe Black
14b11a9734 Fixed subtract with carry, and started some work with floating point.
src/arch/sparc/isa/decoder.isa:
    fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point.
src/arch/sparc/isa/operands.isa:
    Added in floating point operands, and changed the numbering of operands.
src/arch/sparc/regfile.hh:
    Fixed some memory errors related to floating point.

--HG--
extra : convert_revision : fa0aef2021a5cf99f175fceeb533fe63eb5f805c
2006-07-22 15:50:40 -04:00
Kevin Lim
7ccdb7accc Last minute check in. Very few functional changes other than some minor config updates. Also include some recently generated stats.
SConstruct:
    Make test CPUs option non-sticky.
configs/common/FSConfig.py:
    Be sure to set the memory mode.
configs/test/fs.py:
    Wrong string.
tests/SConscript:
    Only test valid CPUs that have been compiled in.
tests/test1/ref/alpha/atomic/config.ini:
tests/test1/ref/alpha/atomic/config.out:
tests/test1/ref/alpha/atomic/m5stats.txt:
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/config.ini:
tests/test1/ref/alpha/detailed/config.out:
tests/test1/ref/alpha/detailed/m5stats.txt:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/config.ini:
tests/test1/ref/alpha/timing/config.out:
tests/test1/ref/alpha/timing/m5stats.txt:
tests/test1/ref/alpha/timing/stdout:
    Update output.

--HG--
extra : convert_revision : 6eee2a5eae0291b5121b41bcd7021179cdd520a3
2006-07-22 15:50:39 -04:00
Kevin Lim
db5f710a7b Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
    Hand merge.

--HG--
extra : convert_revision : 78f7c46084f66d52ddfe0386fd7c08de8017331e
2006-07-21 16:08:17 -04:00
Kevin Lim
a6c2e5cca0 Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.
configs/test/fs.py:
    Pull out a lot of common code and put it into configs/common/FSConfig.py.

--HG--
extra : convert_revision : 175b18d75f82ddecbcc9a6418fe40df314db55d5
2006-07-21 15:56:35 -04:00
Kevin Lim
acf9cf21a2 Missed some files in a previous check-in. Also check-in the SMT tests. Reference stats will be coming soon.
--HG--
extra : convert_revision : c2f7ea613f350e62395f2b50e4c8cc21c6960a22
2006-07-21 15:53:07 -04:00
Kevin Lim
bf90e1dbde Minor functionality updates.
SConstruct:
    Include an option to specify the CPUs being tested.
src/cpu/SConscript:
    Checker isn't SMT right now, so don't do SMT tests with the O3CPU if we're using the checker.
src/python/m5/objects/O3CPU.py:
    Include default options.  Unfortunately FullO3Config.py is still needed because it specifies which FUPool is being used.
tests/SConscript:
    Several minor updates (sorry for one commit).  Updated the copyright and fixed some m5 style issues.  Also added the ability to specify which CPUs to run the tests on.

--HG--
extra : convert_revision : b0b801115705544ea02e572e31314f7bb8b5f0f2
2006-07-21 15:46:12 -04:00
Kevin Lim
bd33d8d4ac Some reorganization. Options are all handled at the user level script. Move createCpus function (now called connectCpu) to Util.py, where it can be used by other configs.
--HG--
rename : configs/test/SysPaths.py => configs/common/SysPaths.py
extra : convert_revision : 2b1b95c5f29e7ade08b1abd6f24c129d600fe2e8
2006-07-21 15:42:44 -04:00
Gabe Black
8bbe925192 Fixed a glitch in the disassembly output.
--HG--
extra : convert_revision : 833aa358b12ac987e0ab467708425c17e5a8fdb7
2006-07-20 21:01:57 -04:00
Gabe Black
419acd31cb Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 0c696374b19b27c0bd50ffa7f75117b1e211e4bc
2006-07-20 19:04:09 -04:00
Ali Saidi
0850c3dedb Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c7fedc68996f2f6cbfb70baebf7c87e0736da883
2006-07-20 19:04:08 -04:00
Ali Saidi
851f91f245 Move PioPort timing code into Simple Timing Port object
Make PioPort use it
Make Physical memory use it as well

src/SConscript:
    Add timing port to sconscript
src/dev/io_device.cc:
src/dev/io_device.hh:
    Move simple timing pio port stuff into a simple timing port class so it can be used by the physical memory
src/mem/physical.cc:
src/mem/physical.hh:
    use a simple timing port stuff instead of rolling our own here

--HG--
extra : convert_revision : e5befbd295a572568cfdca533efb5ed1984c59d1
2006-07-20 19:03:47 -04:00
Ali Saidi
e8a3295075 Enforce the timing cpu ticking at it's clock rate
Add a max time option in seconds and a single system root clock be 1THz

configs/test/fs.py:
    Add a max time option in seconds and a single system root clock be 1THz
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Enforce the timing cpu ticking at it's clock rate

--HG--
extra : convert_revision : a1b0de27abde867f9c3da5bec11639e3d82a95f5
2006-07-20 19:00:40 -04:00
Ali Saidi
15e5ce96c7 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 8c747208d72ffbb0160a2ad4a75383420debdf83
2006-07-19 17:59:04 -04:00
Ali Saidi
6175f712b3 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c5dbee4ba46fae1edba732f4bd05ef984a46d088
2006-07-19 17:24:45 -04:00
Ali Saidi
a50c5cc999 Change the device latency here to a latency rather than a Tick
src/python/m5/objects/Device.py:
src/python/m5/objects/Pci.py:
    Change the default here to a latency rather than a Tick

--HG--
extra : convert_revision : b9366dd89646cea27a836baf249ac2da38c1809f
2006-07-19 17:24:20 -04:00
Kevin Lim
87d4859458 Minor changes to reflect state used for regression stats.
src/cpu/checker/cpu.hh:
    Don't count checker's instructions towards total instructions committed.
src/python/m5/objects/Root.py:
    Set default clock to 1 THz.

--HG--
extra : convert_revision : 0b5eaa197c860c361a3b00087e45ddc249ff1918
2006-07-19 16:09:34 -04:00
Kevin Lim
4bd025742d Put regression tests back into m5. They are located in the "tests" directory. The directory output and reference outputs have changed slightly. Now the directory is ALPHA_SE/test/<test>/<cpu_model>/, and for the reference stats <test>/ref/<arch>/<cpu_model>
Right now only non-SMT SE regression tests have been added back in.  The rest are pending getting SMT working, and consolidating the FS configuration files.

Eventually support for different OSs can be added so you can specify which versions of the binary you want to run from one config file.

Note: mp-test1 doesn't have any reference stats because MP mode doesn't currently work.  The test itself should probably work once the code is fixed.

SConstruct:
    Updates to allow for regression tests to work via the command line "scons build/ALPHA_SE/test/debug/quick" and such once again.
src/cpu/SConscript:
    Keep a list of SMT supporting CPUs so that the regression tests can easily specify which CPUs to use if they are SMT only.

--HG--
extra : convert_revision : 34e6286150aae8f316ae694f6c00be8f510522f2
2006-07-19 16:07:25 -04:00
Kevin Lim
660ea2b176 Get the path to load the ini file from. I'm not sure if this fix is needed in other places as well.
src/sim/main.cc:
    Get the path to load the ini file from.

--HG--
extra : convert_revision : aa38fc9b1bc99cd74d095cbfc67253e4549f91d3
2006-07-19 15:28:53 -04:00
Kevin Lim
85515c4976 O3CPU fixes.
src/cpu/o3/lsq_unit.hh:
    LSQ needs to decrement the WB counter if the load is going to be replayed.
src/cpu/o3/lsq_unit_impl.hh:
    LSQ needs to decrement the WB counter if the load is squashed.

--HG--
extra : convert_revision : 20a10baf0d6ab46065e561ddba231251865ebdbd
2006-07-19 15:28:02 -04:00
Kevin Lim
0cedb23d3c Some minor compiling fixes.
src/cpu/o3/iew.hh:
    Non-debug compile fixes.
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
    Merge fix.

--HG--
extra : convert_revision : 38081925d2b74d8f64acdb65dba94b2bf465b16a
2006-07-19 15:26:48 -04:00
Kevin Lim
1fdf14dd5a Update configs.
configs/test/test.py:
    Update for changes to SEConfig.

--HG--
extra : convert_revision : a089a7db4035889db01d543d9a18ea6526f832ca
2006-07-19 15:24:22 -04:00
Kevin Lim
82b1a278ec Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 06cb509fbbce882793997db275ff7c54058ae619
2006-07-19 14:46:05 -04:00
Gabe Black
b7b603f9a7 Cleaned things up a little.
--HG--
extra : convert_revision : 7091b0d02e5b7c80be43b5ab1ac003dc89c4c136
2006-07-19 02:07:00 -04:00
Gabe Black
44974a4462 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 516c357f98c7a571c70362babd3fa162fbc2ed5a
2006-07-18 18:23:23 -04:00
Korey Sewell
fe9e851e8c update test3
--HG--
extra : convert_revision : e41feeee87d1da348604a37f7349900dcbd3a4d9
2006-07-17 16:50:20 -04:00
Kevin Lim
31ac8e7337 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
configs/test/test.py:
    SCCS merged

--HG--
extra : convert_revision : 7b2dbcd5881fac01dec38001c4131e73b5be52b5
2006-07-14 17:54:43 -04:00
Kevin Lim
138a4faf28 Minor updates.
src/python/m5/config.py:
    Formatting.
src/python/m5/main.py:
    Slightly more useful output when you don't enter in a valid script file.

--HG--
extra : convert_revision : 5a71a6c94dbedeb000f83f57b0b575c2df924509
2006-07-14 17:53:16 -04:00
Kevin Lim
40ebf0811a Fix the CheckerCPU being included via python.
src/arch/SConscript:
    Fixes for including the CheckerCPU if it's specified via command line.  Previously the env variable was actually being modified.
src/cpu/SConscript:
    Copy the CPU_MODELS from the env, don't create a proxy to it.

--HG--
extra : convert_revision : 7d069bd93a6834ccaa1c378b2bc76dce76745c19
2006-07-14 17:51:29 -04:00
Korey Sewell
07186de5a1 forgot tid
--HG--
extra : convert_revision : 272ef8f9cd0802770edc4dcef2c26dc44de71e47
2006-07-14 13:22:35 -04:00
Korey Sewell
b2c51d064b For now, halt context is the same as deallocating.
suspend context will now take the thread off the activeThread list.

src/arch/mips/isa_traits.cc:
    add in copy MiscRegs unimplemented function

--HG--
extra : convert_revision : 3ed5320b3786f84d4bb242e3a32b6f415339c3ba
2006-07-14 13:06:37 -04:00
Korey Sewell
f1a7e0d3b3 MIPS specific fixes ... the main thing is that SMT threads get their own stack space instead of all stacks start to space
src/arch/mips/isa_traits.hh:
    MaxAddr is defined in config.py now
src/arch/mips/process.cc:
    adjust process so SMT threads get their own stack space
src/arch/mips/process.hh:
    add stack_start static variable

--HG--
extra : convert_revision : 73fdf3da9831d86536651835d209806c7f0d59da
2006-07-14 04:52:08 -04:00
Ali Saidi
efc06d0545 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

src/python/m5/main.py:
    merge two help fixes

--HG--
extra : convert_revision : b5c4a88bb84b726bebd3e357a4ef29acc0d95600
2006-07-13 15:50:09 -04:00
Ali Saidi
e1b8e71500 fix help when no arguments are passed to m5
--HG--
extra : convert_revision : ee6614166fd5814654309298abe5a706ff02c4c2
2006-07-13 15:48:41 -04:00
Ali Saidi
c368ff0bd8 add system.mem_mode = ['timing', 'atomic']
update scripts acordingly

configs/test/SysPaths.py:
    new syspaths from nate, this one allows you to set script, binary, and disk paths like
    system.dir = 'aouaou' in your script
configs/test/fs.py:
    update for system mem_mode
    Put small checkpoint example
    Make clock 1THz
configs/test/test.py:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/system.cc:
src/arch/alpha/tru64/system.cc:
src/arch/sparc/system.cc:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
    update for system mem_mode
src/dev/io_device.cc:
    Use time returned from sendAtomic to delay

--HG--
extra : convert_revision : 67eedb3c84ab2584613faf88a534e793926fc92f
2006-07-13 15:48:17 -04:00
Kevin Lim
1e4acb8e01 Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recent changes, and using the O3CPU in SMT mode.
src/cpu/o3/lsq.hh:
    Update to have LSQ work with only one dcache port for all LSQ Units.  LSQ has the dcache port, and the LSQ Units must tell the LSQ if the cache has become blocked.
src/cpu/o3/lsq_impl.hh:
    Updates to have the LSQ work with only one dcache port for all LSQUnits.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Update for LSQ to create dcache port instead of LSQUnits.  Now LSQUnits are given the dcache port from the LSQ, and also must check the LSQ if the cache is blocked prior to accessing the cache.

--HG--
extra : convert_revision : 2708adbf323f4e7647dc0c1e31ef5bb4596b89f8
2006-07-13 13:12:51 -04:00
Kevin Lim
2af213022c Fix for bug when squashing and the fetching. Now fetch checks if the cache data is valid.
--HG--
extra : convert_revision : 07b8eda3e90bbbb3ed470c8cc3cf1b63371ab529
2006-07-13 13:09:29 -04:00
Kevin Lim
a0a952d5ff Update for changes to draining.
--HG--
extra : convert_revision : 5038dd8be72827f40cf89318db0b2bb4f9bbd864
2006-07-13 13:08:58 -04:00
Kevin Lim
63c999edef Fix help message printing. Might need to clean up the handling of the sys.exit() call, as right now it prints out "None" at the end (not sure why).
src/python/m5/main.py:
    Fix help message printing.

--HG--
extra : convert_revision : 6906234101eb7ff7df7933e9aede0362b5a991bd
2006-07-13 12:21:21 -04:00
Ali Saidi
2bc9229ea7 memory mode information now contained in system object
States are now running, draining, or drained. memory state information moved into system object
system parameter is not fs only for cpus
Implement drain() support in devices
Update for drain() call that returns number of times drain_event->process() will be called

Break O3 CPU! No sense in putting in a hack change that kevin is going to remove in a few minutes i imagine

src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
    Since se mode has a system, allow access to it
    Verify that the atomic cpu is connected to an atomic system on resume
src/cpu/simple/base.cc:
    Since se mode has a system, allow access to it
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Update for new drain() call that returns number of times drain_event->process() will be called and memory state being moved into the system
    Since se mode has a system, allow access to it
    Verify that the timing cpu is connected to an timing system on resume
src/dev/ide_disk.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
src/dev/sinic.cc:
src/dev/sinic.hh:
    Implement drain() support in devices
src/python/m5/config.py:
    Allow drain to return number of times drain_event->process() will be called. Normally 0 or 1 but things like O3 cpu or devices with multiple ports may want to call it many times
src/python/m5/objects/BaseCPU.py:
    move system parameter out of fs to everyone
src/sim/sim_object.cc:
src/sim/sim_object.hh:
    States are now running, draining, or drained. memory state information moved into system object
src/sim/system.cc:
src/sim/system.hh:
    memory mode information now contained in system object

--HG--
extra : convert_revision : 1389c77e66ee6d9710bf77b4306fb47e107b21cf
2006-07-12 20:22:07 -04:00
Kevin Lim
6dfaf06edf Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/test.py:
    Hand merge.

--HG--
extra : convert_revision : e3fce9cf50a65a9400cd3ec887b13e4765274ec2
2006-07-12 17:21:25 -04:00
Kevin Lim
6f81ae5cad Be sure to include the EIO sources as well so we can run regression tests.
src/SConscript:
    It's no longer "ALPHA_ISA".  I don't think we meant to leave out the EIO sources.

--HG--
extra : convert_revision : 1ca63ffb571d9021f1ced0bf0df1816b0b798edc
2006-07-12 17:20:01 -04:00
Kevin Lim
e758c1fc04 Serialization changes to make O3CPU consistent with the other models.
src/cpu/o3/commit_impl.hh:
    Always set instruction.  This is necessary for serialization as the instruction is also serialized.
src/cpu/o3/cpu.cc:
    Change serialization so it matches other CPU's output.  Also fix up some indexing.

--HG--
extra : convert_revision : 52f6e183132d177bed6e29dd7cf0c10aed6d8534
2006-07-12 17:18:34 -04:00
Kevin Lim
a9ca36639f Initial try of consolidating configuration files so they can be shared more easily, especially across regression tests and simple examples.
configs/test/fs.py:
    Pull a lot of the default options out of the config file now that they are in the Python objects themselves.  Also merge this file with the single_fs.py, allowing one file to be used for both.  Previously they differed only by the system they instantiated.
configs/test/test.py:
    Initial stab at consolidating configuration files so they aren't redundant between the regression tests and the simple examples.

--HG--
extra : convert_revision : e8ae3de5a6d8864831f21089d4fdb8ec690e4731
2006-07-12 17:17:17 -04:00
Kevin Lim
35ab2296d3 Push more default options to the Python object level as they are rarely changed. These are the changes that Steve was working on.
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/Tsunami.py:
    Push more default options to the Python object level as they are rarely changed.

--HG--
extra : convert_revision : 963eb7a34cd04529b3c5f24b92904ab725c93efb
2006-07-12 17:16:00 -04:00
Kevin Lim
807afe8292 Updates for serialization. As long as the tickEvent doesn't need to be serialized (I don't believe it does because we drain all CPUs prior to checkpointing), it should be feasible to start up from other CPU's checkpoints.
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.cc:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
    Updates for serialization.

--HG--
extra : convert_revision : 0f150de75d4bc833e4c9b83568e7fd22688d5727
2006-07-12 17:11:57 -04:00
Kevin Lim
bbfe1db6b3 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

src/cpu/o3/fetch_impl.hh:
    Hand merge.

--HG--
extra : convert_revision : 820dab2bc921cbadecaca51cd069327f984f5c74
2006-07-12 15:25:34 -04:00
Kevin Lim
6d120b7912 Track the PC of the cache data stored in fetch so it doesn't access memory multiple times if information is already in fetch.
--HG--
extra : convert_revision : 00b160b255e998cf99286bcc21894110c7642624
2006-07-12 15:24:27 -04:00
Nathan Binkert
bf4fdbe25a Add --pdb
src/python/m5/main.py:
    Add a command line option to invoke pdb on your script

--HG--
extra : convert_revision : ef5a2860bd3f6e479fa80eccaae0cb5541a20b50
2006-07-12 15:21:23 -04:00
Nathan Binkert
10a8769d6d Merge m5.eecs.umich.edu:/bk/newmem
into  iceaxe.:/Volumes/work/research/m5/current

--HG--
extra : convert_revision : 842a23da034c40c75364b76ca75de076da776ac6
2006-07-12 15:19:08 -04:00