Commit graph

169 commits

Author SHA1 Message Date
Korey Sewell
b3ff137c8e configs: missed spot progress-interval change 2011-05-23 14:36:22 -04:00
Korey Sewell
9f1b60e05c configs: cleanup redundant/unused options
maxinsts & max_inst redundant
prog_intvl and profile seem redundant, but profile looks to be unused
add -p option for progress intervals
2011-05-20 14:49:06 -04:00
Ali Saidi
cefd6960e5 ARM: Configure bootloader parameters 2011-05-04 20:38:28 -05:00
Nathan Binkert
09064ea552 python: fix another bug from changes to main.py 2011-04-20 19:07:44 -07:00
Ali Saidi
d6289507d8 ARM: Include IDE/CF controller by default in PBX model.
Frame buffer and boot linux:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit
Linux from a CF card:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit
Run Android
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android
Run MP
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
2011-04-04 11:42:31 -05:00
Anthony Gutierrez
332adcdd1a Sim: Fix Simulation.py to allow more than 1 core for standard switching.
This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1,
switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are
assigned only once, after switch_cpus and switch_cpus_1 are constructed.
2011-04-04 11:42:31 -05:00
Ali Saidi
887e9e2b99 ARM: Bare metal system should have 256MB of RAM. 2011-03-17 19:20:20 -05:00
Ali Saidi
a432d8e085 Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.
This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
2011-03-17 19:20:19 -05:00
Gabe Black
aa0cd52504 Configs: Explicitly import env in Benchmarks.py
env was being implicitly imported into Benchmarks.py through SysPaths.py.
This change brings it in explicitly in the file where it's used.
2011-02-24 02:14:45 -08:00
Ali Saidi
79dac89552 ARM: Clarifies creation of Linux and baremetal ARM systems.
makeArmSystem creates both bare-metal and Linux systems more cleanly.
machine_type was never optional though listed as an optional argument; a system
such as "RealView_PBX" must now be explicitly specified.  Now that it is a
required argument, the placement of the arguments has changed slightly
requiring some changes to calls that create ARM systems.
2011-02-23 15:10:48 -06:00
Korey Sewell
981e1dd7ee configs: cache: add cache line size option 2011-02-23 14:26:55 -05:00
Korey Sewell
fb92578415 configs: set default cache params
It's confusing (especially to new users), when you are setting some standard
parameters (as defined in Options.py) and they aren't reflected in the simulations
so we might as well link the settings in CacheConfig.py to those in Options.py
2011-02-23 01:01:46 -05:00
Ali Saidi
d33c1d9592 VNC: Add VNC server to M5 2011-02-11 18:29:35 -06:00
Brad Beckmann
6ebd7c390b config: fixed minor bug connecting dma devices to ruby 2011-02-08 15:52:44 -08:00
Gabe Black
f8fc0419c5 X86, Config: Move the setting of work count options to a separate function.
This way things that don't care about work count options and/or aren't called
by something that has those command line options set up doesn't have to build
a fake object to carry in inert values.
2011-02-07 01:22:15 -08:00
Brad Beckmann
dfa8cbeb06 m5: added work completed monitoring support 2011-02-06 22:14:19 -08:00
Brad Beckmann
17b4ef52bb ruby: x86 fs config support 2011-02-06 22:14:18 -08:00
Gabe Black
00f24ae92c Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
2011-02-03 20:23:00 -08:00
Gabe Black
c4b81d311e X86: Change how the default disk image gets set up.
The disk image to use was always being forced to a particular value. This
change changes what disk image is selected as the default based on the
architecture being built. In the future, a more sophisticated system might be
used that selected a path based on certain rules instead of relying on one off
file names.
2011-02-02 18:03:58 -08:00
Gabe Black
119f5f8e94 X86: Add L1 caches for the TLB walkers.
Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.
2011-02-01 18:28:41 -08:00
Gabe Black
4876e0c92b Config: Change misleading "cycle" message to say "tick".
Most of the messages in the config scripts that report a time value already
print "@ tick" followed by the current tick value, but a few were printing
"@ cycle". Since this is a distinction that's frequently confusing to new
users, this changes those message to the more accurate and consistent "@ tick".
2010-11-17 23:16:19 -05:00
Ali Saidi
d7b8efa0df ARM: Add support for a dumb IDE controller 2010-11-15 14:04:03 -06:00
Ali Saidi
c779af4e12 Mem: Finish half-baked support for mmaping file in physmem.
Physmem has a parameter to be able to mem map a file, however
it isn't actually used. This changeset utilizes the parameter
so a file can be mmapped.
2010-11-08 13:58:24 -06:00
Brad Beckmann
8572d8fd91 config: fixed ruby dma device connections 2010-08-24 13:20:31 -07:00
Ali Saidi
330fada1aa ARM: Add configuration for Linux/Full System 2010-08-23 11:18:40 -05:00
Brad Beckmann
29c45ccd23 ruby: Reduced ruby latencies
The previous slower ruby latencies created a mismatch between the faster M5
cpu models and the much slower ruby memory system.  Specifically smp
interrupts were much slower and infrequent, as well as cpus moving in and out
of spin locks.  The result was many cpus were idle for large periods of time.

These changes fix the latency mismatch.
2010-08-20 11:46:12 -07:00
Brad Beckmann
5c801090a3 config: reorganized how ruby specifies command-line options 2010-08-20 11:44:09 -07:00
Steve Reinhardt
e0754c0f6c misc: add some AMD copyright notices
Meant to add these with the previous batch of csets.
2010-08-17 05:49:05 -07:00
Steve Reinhardt
2519d116c9 sim: fold checkpoint restore code into instantiate()
The separate restoreCheckpoint() call is gone; just pass
the checkpoint dir as an optional arg to instantiate().
This change is a precursor to some more extensive
reworking of the startup code.
2010-08-17 05:17:06 -07:00
Steve Reinhardt
cfaddd5fd3 configs: clean up checkpoint code in Simulation.py
Small change to clean up some redundant code.
Should not have any functional impact.
2010-08-17 05:17:06 -07:00
Steve Reinhardt
1fbe466345 sim: make Python Root object a singleton
Enforce that the Python Root SimObject is instantiated only
once.  The C++ Root object already panics if more than one is
created.  This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists).  It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone.  Users who use
configs/common/Simulate.py should not notice.
2010-08-17 05:06:22 -07:00
Nathan Binkert
2e9e75447a None, not none 2010-08-08 22:57:16 -07:00
Steve Reinhardt
cbd65e95db util: add a script for testing checkpointing
See comments in util/checkpoint-tester.py for details.
2010-07-05 21:39:38 -07:00
Ali Saidi
3dc6a8070e ARM: fix sizes of structs for ARM Linux 2010-06-02 12:58:17 -05:00
Nathan Binkert
90820ddf02 config: fix assertion for x86 in FSConfig.py 2010-04-18 21:33:59 -07:00
Brad Beckmann
898f1fc4a4 ruby: Reorganized Ruby topology and protocol files
--HG--
rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/protocols/MESI_CMP_directory.py
rename : configs/ruby/MI_example.py => configs/ruby/protocols/MI_example.py
rename : configs/ruby/MOESI_CMP_directory.py => configs/ruby/protocols/MOESI_CMP_directory.py
rename : configs/ruby/MOESI_CMP_token.py => configs/ruby/protocols/MOESI_CMP_token.py
rename : configs/ruby/MOESI_hammer.py => configs/ruby/protocols/MOESI_hammer.py
rename : configs/ruby/networks/MeshDirCorners.py => src/mem/ruby/network/topologies/MeshDirCorners.py
2010-03-21 21:22:22 -07:00
Brad Beckmann
4f044605e8 ruby: Adds configurable bit selection for numa mapping 2010-03-21 21:22:21 -07:00
Brad Beckmann
92cfd1cac7 ruby: Ruby support for sparse memory
The patch includes direct support for the MI example protocol.
2010-03-21 21:22:21 -07:00
Brad Beckmann
d8e1e5abd0 ruby: fixed how ruby_fs creates phsyical memory
Now ruby_fs creates physical memory of the right size.
2010-03-21 21:22:20 -07:00
Lisa Hsu
a70f70ccbf configs: pull out cache configuration code from se.py and fs.py.
Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.
2010-02-25 10:13:40 -08:00
Brad Beckmann
8dd45674ae ruby: Converted Garnet to M5 configuration 2010-01-29 20:29:32 -08:00
Brad Beckmann
6c867f8263 ruby: Added a mesh topology 2010-01-29 20:29:27 -08:00
Brad Beckmann
d77a9df3c1 ruby: MOESI_CMP_token updates to use the new config system 2010-01-29 20:29:25 -08:00
Brad Beckmann
ce2d13195b ruby: FS support using the new configuration system 2010-01-29 20:29:21 -08:00
Brad Beckmann
dc758641c9 ruby: reorganized ruby python configuration
Reorganized ruby python configuration so that protocol and ruby memory system
configuration code can be shared by multiple front-end configuration files
(i.e. memory tester, full system, and hopefully the regression tester).  This
code works for memory tester, but have not tested fs mode.
2010-01-29 20:29:20 -08:00
Gabe Black
93d89b288f X86: Record the memory mode when building an X86 system. 2009-12-19 01:49:34 -08:00
Brad Beckmann
70a261c0ae m5: Added option to take a checkpoint at the end of simulation 2009-11-18 13:55:58 -08:00
Brad Beckmann
b8c413e993 m5: Moved profile option since Simulation depends on it. 2009-11-18 13:55:58 -08:00
Brad Beckmann
3cf24f9716 ruby: Support for merging ALPHA_FS and ruby
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers.  Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
2009-11-18 13:55:58 -08:00
Nathan Binkert
9a8cb7db7e python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.

--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-22 15:24:16 -07:00