virtual function in alphaaccess.cc
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_io.hh:
Removed dynamic cast to get interrupt frequency and replaced with a
virtual function
--HG--
extra : convert_revision : 01f514a33d8f76c6527ab25a713d5c86f9fd646e
PIO writes. This was mainly related to not shadowing the status register
properly, and also not setting some of the status bits expected by the
operating system for the PIO write protocol.
--HG--
extra : convert_revision : fcdfd588be6e4f237aa6057889f0b3bdf4ea7631
way a Tru64 system can be either Tlaser (by default) or Tsunami.
Added debugSymbolTable to Tru64 for symbol printing in InstExec Trace
cpu/exetrace.cc:
Fixed bug if debugSymbolTable doesn't exist, we shouldn't try to
look something up in it.
kern/tru64/tru64_system.hh:
Added ability to specify system type/revision in config file. This
way a Tru64 system can be either Tlaser (by default) or Tsunami.
--HG--
extra : convert_revision : c69a7411f0aa118ca5a766e43b7ceb7a5bb04cdf
dev/tsunami_cchip.hh:
clean up some comments
kern/linux/linux_syscalls.cc:
Cleaned up spacing of syscall numbers
kern/linux/linux_system.hh:
Added doxygen comments
--HG--
extra : convert_revision : 23ecdaa92a208458dd5c5d3c68ac9012ce2690da
Got rid of two inconsistent sets of strings that corresponded
to this enum, and replaced with a single set that clearly
matches the enum names.
arch/alpha/isa_desc:
arch/isa_parser.py:
cpu/full_cpu/op_class.hh:
Renamed OpClass enum members.
--HG--
extra : convert_revision : bf596f7568a20b2e77c07ac349f253135141aef4
base/stats/mysql.hh:
Rename of Statsistics namespace to stats... merge from head
--HG--
extra : convert_revision : a5a7f6268b35e75fba1b1800a74fcd6dbd09d974
dev/baddev.hh:
dev/pcidev.hh:
dev/tsunami.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
Added doxygen comments
dev/pciconfigall.hh:
Added doxygen comments. Made the hlist of devices private and provided
members to modify the data.
dev/pcidev.cc:
updated for change in pciconfigall
dev/tsunami_pchip.cc:
Deleted commented out code we don't need
kern/linux/linux_syscalls.cc:
Simplified the number -> name conversion.
kern/linux/linux_syscalls.hh:
Removed StandardNumber and replaced with Number.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
LinuxSkipIdeDelay50msEvent was simply the same as the SkipFunc event,
so I removed it. Same with with LinuxSkipFuncEvent.
--HG--
extra : convert_revision : 1508c335f87d90373f5772f3a0407ea13e858d7e
arch/alpha/ev5.cc:
Updated to support new forms of setIntReg and setFloatRegDouble. Will need to be cleaned up in the future.
arch/isa_parser.py:
Added in FastCPU model.
--HG--
extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
arch/alpha/ev5.cc:
Added templatized processInterrupts() function that can be used by all of the CPU models.
arch/alpha/isa_desc:
Merged in changes to remove CPU dependence.
arch/isa_parser.py:
Merged in changes.
cpu/static_inst.hh:
Includes FastCPU execute methods.
--HG--
extra : convert_revision : fcaa1dca35a9b316c73982bec8680df564f50bd8
Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile.
arch/alpha/alpha_memory.cc:
The regfile has been changed so it no longer has the opcode and ra. Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
Moved code that once existed within simpleCPU to ev5, and templatized it.
This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
Removed opcode and ra from the regfile. The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
Added in a more generic trap function so "ev5_trap" doesn't need to be called. It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
Exec context now has the instruction within it. Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
Added declaration for execute() using FastCPUExecContext.
--HG--
extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
Removed bootloader and just wrote command line into linux kernel
base/inifile.cc:
the forked process should not return, it should exit.
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
The serial port in reality has some delay and linux expects it. This
schedules an interrupt 300 cycles after the transmit instead of
immediately
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
removed boot loader and stuck boot command line in the kernel manually
--HG--
extra : convert_revision : 68aa54f8ca4e8391789f7a4c1ae227e6f8b94e13
dev/ns_gige.cc:
remove some useless DPRINTF's and add some useful ones. fix the missing RXDESC interrupt.
--HG--
extra : convert_revision : 17142480db1eaafa24f88640f8c7b8e7e077de1a
dev/ide_disk.cc:
Fix to PIO writes and also add command needed for shutdown
dev/pcidev.cc:
Change the panic on write to read-only registers to a debug print. The
kernel tries to write back over all of the PCI registers to restore
the saved SRM state, so we need to let it do this without panicing.
sim/system.cc:
Add back increment of number of running systems to allow trap of halt
work correctly.
--HG--
extra : convert_revision : 84aba4effbec14545f3610c19a8e321d7e7f7cf2
doesn't conflict with the old ethernet driver name.
Added config file to try to boot Tru64 with Tsunami
Cleaned up kern/linux a bit more and fixed bug where we were using
Tru64 system calls
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/tsunami.hh:
Changed name of lisa's device to NSgigE instead of Etherdev so it
doesn't conflict with the old ethernet driver name.
kern/linux/linux_syscalls.hh:
the Syscalls still used the Tru64 calls, oops.. fixed.
--HG--
extra : convert_revision : dedd20686cc367ed37f31920f753566afbc69045
database work better.
base/stats/events.cc:
properly connect to the database
base/stats/mysql.cc:
cleanup the event stuff too
--HG--
extra : convert_revision : f05fd6456decc9c4f95beff5c12497439e45f886
arch/alpha/ev5.cc:
Add an event for faults
cpu/simple_cpu/simple_cpu.cc:
add events for uncached reads/writes
--HG--
extra : convert_revision : 747bdf12761e2de6ebbf54fecc9e0b71915b3a02
of events into the database for a given run.
base/stats/mysql.cc:
base/stats/mysql.hh:
reorganize mysql stat stuff so that other stuff can use
the same database connection
base/traceflags.py:
Trace flag to print out events
--HG--
extra : convert_revision : 4d502532ed0ba40b42baefee46b2c99defcc620c
if Tru64 is to continue to be supported on Turbolaser) and fixed
translation of physical addresses by clearing PA<42:35> when the real
uncachable bit (43) is set
arch/alpha/ev5.hh:
Change to support 256 ASNs and seperate VA_SPACE checks for EV5 and EV6
also add support proper translation of uncacheable physical addresses
dev/ide_ctrl.cc:
Fix to work with real address translation
--HG--
extra : convert_revision : aa3d1c284b8271d4763a8da2509c91bbcf83189a
instruction execute methods. Register i now means the instruction's
i'th src (or dest) operand, not architectural register i. Current
models that use the architectural reg index can look that up easily
in the instruction object. Future models that do register renaming
should find this much simpler to deal with.
arch/isa_parser.py:
Generate register accessors with an extra level of indirection.
cpu/simple_cpu/simple_cpu.hh:
Modify register accessors to use an extra level of indirection.
--HG--
extra : convert_revision : f4c7d6bfa92fb2ea6251f31ee368809c3643f08f
with an IsNonSpeculative flag.
No effect on results of non-full-system or SimpleCPU.
Very small impact on full-system FullCPU runs since old wrong-path
call_pal insts used to change the PC, where now they're treated
as no-ops.
arch/alpha/isa_desc:
Get rid of xc->misspeculating() checks, use IsNonSpeculative flag instead.
cpu/static_inst.hh:
Add IsNonSpeculative flag and isNonSpeculative() method to test it.
--HG--
extra : convert_revision : 7ec536bfc28b905c429c09eb920ed73ef2beeeba
dev/ns_gige.cc:
clear the device interrupts
dev/ns_gige_reg.h:
Add a new mask
--HG--
extra : convert_revision : ce3617315677cbee577ed8893821a8abc5a1a10d
kern/linux/linux_system.cc:
add binned_fns parameter to System, remove nonLinux events from LinuxSystem, fix ~LinuxSystem() by adding delete of some things that need to be deleted.
kern/linux/linux_system.hh:
fix header file to go with linux_system.cc, removing nonLinux events and adding binned_fns param.
kern/tru64/tru64_system.cc:
add somme consistency by having having binned_fns be _binned_fns in the Tru64System arg list.
--HG--
extra : convert_revision : b2ec0c1614e185aafa177c220b91d1f6a4fe6876
kern/tru64/tru64_system.cc:
make binned_fns a parameter for System in addition to Tru64System. Do all the fnEvents setting at the System level, since that is system-independent.
kern/tru64/tru64_system.hh:
deal with FnEvents in the System, and move some fns over to System.
sim/system.cc:
sim/system.hh:
lift binning stuff into System out of Tru64System
--HG--
extra : convert_revision : 591dee6f2013f5c43037726c529a00682b5cf82e
out CPU model. ISA description now generates multiple
output source files to (in theory) reduce compilation time.
arch/alpha/isa_desc:
Update for parser changes. Move most constructors
out of class declarations (which are now in decoder.hh)
and into decoder.cc. Move all execute() methods into
exec output.
arch/isa_parser.py:
Significant changes to make ISA description completely
independent of CPU model, and isolate model-dependent parts
of parser into one little class (CpuModel). Also split up code
output into multiple files (a header, a main source file, and
per-cpu execute() method files).
Noticeable changes to language as a result. See updated Doxygen
documentation.
cpu/simple_cpu/simple_cpu.hh:
SimpleCPUExecContext typedef no longer needed.
Add forward declaration of Process.
cpu/static_inst.hh:
SimpleCPUExecContext and FullCPUExecContext typedefs no longer needed.
Make eaCompInst() and memAccInst() return const refs.
--HG--
extra : convert_revision : 71471f267804fafd0a881bac7445677e76334daf
