Commit graph

10721 commits

Author SHA1 Message Date
Nilay Vaish 85c29973a3 ruby: remove sparse memory.
In my opinion, it creates needless complications in rest of the code.
Also, this structure hinders the move towards common set of code for
physical memory controllers.
2014-11-06 05:42:20 -06:00
Nilay Vaish 95a0b18431 ruby: single physical memory in fs mode
Both ruby and the system used to maintain memory copies.  With the changes
carried for programmed io accesses, only one single memory is required for
fs simulations.  This patch sets the copy of memory that used to reside
with the system to null, so that no space is allocated, but address checks
can still be carried out.  All the memory accesses now source and sink values
to the memory maintained by ruby.
2014-11-06 05:41:44 -06:00
Nilay Vaish 8ccfd9defa ruby: dma sequencer: remove RubyPort as parent class
As of now DMASequencer inherits from the RubyPort class.  But the code in
RubyPort class is heavily tailored for the CPU Sequencer.  There are parts of
the code that are not required at all for the DMA sequencer.  Moreover, the
next patch uses the dma sequencer for carrying out memory accesses for all the
io devices.  Hence, it is better to have a leaner dma sequencer.
2014-11-06 00:55:09 -06:00
Ali Saidi ae82551496 tests: Update stats no match.
Bootloader I had on my sytem was an older version with a couple of
instruction differences.
2014-11-03 10:14:42 -06:00
Ali Saidi 2c2c3a4ce9 arm, tests: Forgot the system.terminal files for the new regressions. 2014-10-30 00:04:12 -05:00
Ali Saidi 29cd50e14e arm, tests: Add 64-bit ARM regression tests 2014-10-29 23:50:15 -05:00
Ali Saidi 7a0bf814b6 automated merge 2014-10-29 23:22:26 -05:00
Ali Saidi 93c0307d41 tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-29 23:18:29 -05:00
Ali Saidi f2db2a96d1 arm, tests: Update config files to more recent kernels and create 64-bit regressions.
This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.

In addition a set of 64-bit ARM regressions have been added to the regression system.
2014-10-29 23:18:27 -05:00
Mitch Hayenga 5bfa521c46 cpu: Add writeback modeling for drain functionality
It is possible for the O3 CPU to consider itself drained and
later have a squashed instruction perform a writeback.  This
patch re-adds tracking of in-flight instructions to prevent
falsely signaling a drained event.
2014-10-29 23:18:27 -05:00
Mitch Hayenga 6847bbf7ce cpu: Add drain check functionality to IEW
IEW did not check the instQueue and memDepUnit to ensure
they were drained.  This caused issues when drainSanityCheck()
did check those structures after asserting IEW was drained.
2014-10-29 23:18:26 -05:00
Ali Saidi b31d9e93e2 arm, mem: Fix drain bug and provide drain prints for more components. 2014-10-29 23:18:26 -05:00
Ali Saidi baf88e908d arm: Fix multi-system AArch64 boot w/caches.
Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.
2014-10-29 23:18:26 -05:00
Ali Saidi 3a5c975fd7 arm: fix bare-metal memory setup.
The bare-metal configuration option still configured memory with the old scheme
that no-longer works. This change unifies the code so there aren't any differences.
2014-10-29 23:18:26 -05:00
Ali Saidi 9900629f83 arm: Mark some miscregs (timer counter) registers at unverifiable.
The checker can't verify timer registers, so it should just grab the version
from the executing CPU, otherwise it could get a larger value and diverge
execution.
2014-10-29 23:18:24 -05:00
Ali Saidi e3ee27c7b4 cpu: Add support to checker for CACHE_BLOCK_ZERO commands.
The checker didn't know how to properly validate these new commands.
2014-10-29 23:18:24 -05:00
Andrew Bardsley 536c72333f cpu: Fix barrier push to store buffer when full bug in Minor
This patch fixes a bug where a completing load or store which is also a
barrier can push a barrier into the store buffer without first checking
that there is a free slot.

The bug was not fatal but would print a warning that the store buffer
was full when inserting.
2014-10-29 23:18:24 -05:00
Curtis Dunham 4024fab7fc mem: don't inhibit WriteInv's or defer snoops on their MSHRs
WriteInvalidate semantics depend on the unconditional writeback
or they won't complete.  Also, there's no point in deferring snoops
on their MSHRs, as they don't get new data at the end of their life
cycle the way other transactions do.

Add comment in the cache about a minor inefficiency re: WriteInvalidate.
2014-10-21 17:04:41 -05:00
Curtis Dunham 46f9f11a55 mem: have WriteInvalidate obsolete MSHRs
Since WriteInvalidate directly writes into the cache, it can
create tricky timing interleavings with reads and writes to the
same cache line that haven't yet completed.  This patch ensures
that these requests, when completed, don't overwrite the newer
data from the WriteInvalidate.
2014-10-29 23:18:24 -05:00
Steve Reinhardt 6ab4eddb9f syscall_emul: add retry flag to SyscallReturn
This hook allows blocking emulated system calls to indicate
that they would block, but return control to the simulator
so that the simulation does not hang.  The actual retry
functionality requires additional support, to be provided
in a future changeset.
2014-09-02 16:07:50 -05:00
Steve Reinhardt 9ac7f14fc0 syscall_emul: minor style fix to LiveProcess constructor 2014-10-22 15:53:34 -07:00
Steve Reinhardt df7f0892ed syscall_emul: devirtualize BaseBufferArg methods
Not clear why they were marked virtual to begin with,
but that doesn't appear to be necessary.
2014-10-22 15:53:34 -07:00
Steve Reinhardt 44af2c6a69 syscall_emul: Put BufferArg classes in a separate header.
Move the BufferArg classes that support syscall buffer args
(i.e., pointers into simulated user space) out of syscall_emul.hh
and into a new header syscall_emul_buf.hh so they are accessible
to emulated driver implementations.

Take the opportunity to add some comments as well.
2014-10-22 15:53:34 -07:00
Steve Reinhardt 44ec1d2124 syscall_emul: add EmulatedDriver object
Fake SE-mode device drivers can now be added by
deriving from this abstract object.
2014-10-22 15:53:34 -07:00
Nilay Vaish 6523aad25c sim: revert 6709bbcf564d
The identifier SYS_getdents is not available on Mac OS X.  Therefore, its use
results in compilation failure.  It seems there is no straight forward way to
implement the system call getdents using readdir() or similar C functions.
Hence the commit 6709bbcf564d is being rolled back.
2014-10-22 15:59:57 -05:00
Andreas Hansson d6f1c6ce89 x86: Fixes to avoid LTO warnings
This patch fixes a few minor issues that caused link-time warnings
when using LTO, mainly for x86. The most important change is how the
syscall array is created. Previously gcc and clang would complain that
the declaration and definition types did not match. The organisation
is now changed to match how it is done for ARM, moving the code that
was previously in syscalls.cc into process.cc, and having a class
variable pointing to the static array.

With these changes, there are no longer any warnings using gcc 4.6.3
with LTO.
2014-10-20 18:03:56 -04:00
Andreas Hansson 6290f98194 misc: Use gmtime for conversion to UTC to avoid getenv/setenv
This patch changes how we turn time into UTC. Previously we
manipulated the TZ environment variable, but this has issues as the
strings that are manipulated could be tainted (see e.g. CERT
ENV34-C). Now we simply rely on the built-in gmtime function and avoid
touching getenv/setenv all together.
2014-10-20 18:03:55 -04:00
Omar Naji a4a8568bd2 mem: Fix DRAM activationlLimit bug
Ensure that we do the proper event scheduling also when the activation
limit is disabled.
2014-10-20 18:03:55 -04:00
Andreas Hansson 77f8f5d94c base: Fix for stats node on gcc < 4.6.3
This patch adds an explicit function to get the underlying node as gcc
4.6.1 and 4.6.2 have issues otherwise.
2014-10-20 18:03:54 -04:00
Andreas Hansson b976496a34 ext: Bump DRAMPower to avoid compilation issues
This patch bumps DRAMPower to commit
19433a6897ede4bbb19b06694faa8589b5a6569a which contains a small fix
for clang, and a work-around for LTO with gcc 4.6.
2014-10-20 18:03:53 -04:00
Omar Naji 29dd2887f4 mem: Add DRAM device size and check against config
This patch adds the size of the DRAM device to the DRAM config. It
also compares the actual DRAM size (calculated using information from
the config) to the size defined in the system. If these two values do
not match gem5 will print a warning. In order to do correct DRAM
research the size of the memory defined in the system should match the
size of the DRAM in the config. The timing and current parameters
found in the DRAM configs are defined for a DRAM device with a
specific size and would differ for another device with a different
size.
2014-10-20 18:03:52 -04:00
Nilay Vaish d2a0f60b69 stats: updates due to previous mmap and exit_group patches. 2014-10-20 16:48:19 -05:00
Nilay Vaish 922a9d8ed2 cpu: o3: corrects base FP and CC register index in removeThread() 2014-10-20 16:47:55 -05:00
Tom Jablin c6731e331a sim: invalid alignment checks in mmap and mremap
Presently, the alignment checks in the mmap and mremap implementations
in syscall_emul.hh are wrong. The checks are implemented as:

if ((start % TheISA::PageBytes) != 0 ||
        (length % TheISA::PageBytes) != 0) {
    warn("mmap failing: arguments not page-aligned: "
            "start 0x%x length 0x%x",
            start, length);
    return -EINVAL;
}

This checks that both the start and the length arguments of the mmap
syscall are checked for page-alignment. However, the POSIX specification says:

The off argument is constrained to be aligned and sized according to the value
returned by sysconf() when passed _SC_PAGESIZE or _SC_PAGE_SIZE. When MAP_FIXED
is specified, the application shall ensure that the argument addr also meets
these constraints. The implementation performs mapping operations over whole
pages. Thus, while the argument len need not meet a size or alignment
constraint, the implementation shall include, in any mapping operation, any
partial page specified by the range [pa,pa+len).

So the length parameter should not be checked for page-alignment. By contrast,
the current implementation fails to check the offset argument, which must be
page aligned.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-20 16:45:25 -05:00
Michael Adler 7254d5742a sim: mmap: correct behavior for fixed address
Change mmap fixed address request to return an error if the mapping is
impossible due to conflict instead of what I believe used to be silent
corruption.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-20 16:45:08 -05:00
Michael Adler a3fe4c0662 sim: implement getdents/getdents64 in user mode
Has been tested only for alpha.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-20 16:44:53 -05:00
Severin Wischmann ext:(%2C%20Ioannis%20Ilkos%20%3Cioannis.ilkos09%40imperial.ac.uk%3E) e72736aaf0 x86: syscall: implementation of exit_group
On exit_group syscall, we used to exit the simulator.  But now we will only
halt the execution of threads that belong to the group.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-20 16:43:48 -05:00
Andreas Hansson 6d4866383f mem: Modernise PhysicalMemory with C++11 features
Bring the PhysicalMemory up-to-date by making use of range-based for
loops and vector intialisation where possible.
2014-10-16 05:50:01 -04:00
Andreas Hansson edc77fc03c misc: Move AddrRangeList from port.hh to addr_range.hh
The new location seems like a better fit. The iterator typedefs are
removed in favour of using C++11 auto.
2014-10-16 05:49:59 -04:00
Andreas Sandberg e6ad39adac ext: Update fputils to rev 6a47fd8358
This patch updates fputils to the latest revision (6a47fd8358) from
the upstream repository (github.com/andysan/fputils). Most notably,
this includes changes that export a limited set of 64-bit float
manipulation and avoids a warning about unused 64-bit floats in clang.
2014-10-16 05:49:58 -04:00
Geoffrey Blake 2d2006ddb3 dev: refactor pci config space for sysfs scanning
Sysfs on ubuntu scrapes the entire PCI config space
when it discovers a device using 4 byte accesses.
This was not supported by our devices, in particular the NIC
that implemented the extended PCI config space.  This change
allows the extended PCI config space to be accessed by
sysfs properly.
2014-10-16 05:49:57 -04:00
Andrew Bardsley d6732895a5 mem: Add ExternalMaster and ExternalSlave ports
This patch adds two MemoryObject's: ExternalMaster and ExternalSlave.
Each object has a single port which can be bound to an externally-
provided bridge to a port of another simulation system at
initialisation.
2014-10-16 05:49:56 -04:00
Andrew Bardsley 83f7e7afaf sim: SystemC hosting
This patch hosts gem5 onto SystemC scheduler. There's already an upstream
review board patch that does something similar but this patch ...:

 1) is less obtrusive to the existing gem5 code organisation. It's divided
 into the 'generic' preparatory patches (already submitted) and this patch
 which affects no existing files

 2) does not try to exactly track the gem5 event queue with notifys into
 SystemC and so doesn't requive the event queue to be modified for
 anything other than 'out of event queue' scheduling events

 3) supports debug logging with SC_REPORT

The patch consists of the files:
    util/systemc/
        sc_gem5_control.{cc,hh} -- top level objects to use to
                                   instantiate gem5 Systems within
                                   larger SystemC test harnesses as
                                   sc_module objects
        sc_logger.{cc,hh}       -- logging support
        sc_module.{cc,hh}       -- a separated event loop specific to
                                   SystemC
        stats.{cc,hh}           -- example Stats handling for the sample
                                   top level
        main.{cc,hh}            -- a sample top level

On the downside this patch is only currently functional with C++
configuration at the top level.

The above sc_... files are indended to be compiled alongside gem5 (as a
library, see main.cc for a command line and util/systemc/README for
more details.)

The top-level system instantiation in sc_gem5_control.{cc,hh} provides
two classes: Gem5Control and Gem5System

Gem5Control is a simulation control class (from which a singleton
object should be created) derived from Gem5SystemC::Module which
carries the top level simulation control interface for gem5.  This
includes hosting a system-building configuration file and
instantiating the Root object from that file.

Gem5System is a base class for instantiating renamed gem5 Systems
from the config file hosted by the Gem5Control object.  In use, a
SystemC module class should be made which represents the desired,
instantiable gem5 System.  That class's instances should create
a Gem5System during their construction, set the parameters of that
system and then call instantiate to build that system.  If this
is all carried out in the sc_core::sc_module-derived classes
constructor, the System's external ports will become children of
that module and can then be recovered by name using sc_core::
sc_find_object.

It is intended that this interface is used with dlopen.  To that
end, the header file sc_gem5_control.hh includes no other header
files from gem5 (and so can be easily copied into another project).
The classes Gem5System and Gem5Control have all their member
functions declared `virtual' so that those functions can be called
through the vtable acquired by building the top level Gem5Control
using dlsym(..., "makeGem5Control") and `makeSystem' on the
Gem5Control.
2014-10-16 05:49:54 -04:00
Andreas Hansson e2a13386e5 sim: EventQueue wakeup on events scheduled outside the event loop
This patch adds a 'wakeup' member function to EventQueue which should be
called on an event queue whenever an event is scheduled on the event queue
from outside code within the call tree of the gem5 event loop.

This clearly isn't necessary for normal gem5 EventQueue operation but
becomes the minimum necessary interface to allow hosting gem5's event loop
onto other schedulers where there may be calls into gem5 from external
code which schedules events onto an EventQueue between the current time and
the time of the next scheduled event.

The use case I have in mind is a SystemC hosting where the event loop is:

    while (more events) {
        wait(time_to_next_event or wakeup)
        setCurTick
        service events at this time
    }

where the 'wait' needs to be woken up if time_to_next_event becomes shorter
due to a scheduled event from SystemC arriving in a gem5 object.

Requiring 'wakeup' to be called is a more efficient interface than
requiring all gem5 event scheduling actions to affect the host scheduler.

This interface could be located elsewhere, say on another global object,
or by being passed by the host scheduler to objects which will schedule
such events, but it seems cleanest to put it on EventQueue as it is
actually a signal to the queue.

EventQueue::wakeup is called for async_event events on event queue 0 as
it's only important that *some* queue be triggered for such events.
2014-10-16 05:49:53 -04:00
Andrew Bardsley 960935a5bd base: Reimplement the DPRINTF mechanism in a Logger class
This patch adds a Logger class encapsulating dprintf.  This allows
variants of DPRINTF logging to be constructed and substituted in
place of the default behaviour.

The Logger provides a logMessage(when, name, format, ...) member
function like Trace::dprintf and a getOstream member function to
use a raw ostream for logging.

A class OstreamLogger is provided which generates the customary
debugging output with Trace::OstreamLogger::logMessage being the
old Trace::dprintf.
2014-10-16 05:49:53 -04:00
Andreas Hansson a2d246b6b8 arch: Use shared_ptr for all Faults
This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".
2014-10-16 05:49:51 -04:00
Andreas Hansson a769963d16 o3: Use shared_ptr for MemDepEntry
This patch transitions the o3 MemDepEntry from the ad-hoc
RefCountingPtr to the c++11 shared_ptr. There are no changes in
behaviour, and the code modifications are mainly replacing "new" with
"make_shared".
2014-10-16 05:49:49 -04:00
Andreas Hansson db3739682d mem: Use shared_ptr for Ruby Message classes
This patch transitions the Ruby Message and its derived classes from
the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no
changes in behaviour, and the code modifications are mainly replacing
"new" with "make_shared".

The cloning of derived messages is slightly changed as they previously
relied on overriding the base-class through covariant return types.
2014-10-16 05:49:49 -04:00
Andreas Hansson acdfcad30d base: Use shared_ptr for stat Node
This patch transitions the stat Node and its derived classes from
the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no
changes in behaviour, and the code modifications are mainly replacing
"new" with "make_shared".
2014-10-16 05:49:48 -04:00
Andreas Hansson 8b789ae451 base: Transition CP annotate to use shared_ptr 2014-10-16 05:49:47 -04:00