Commit graph

12 commits

Author SHA1 Message Date
Curtis Dunham
392ef0349e ext: update SST test config
Align configuration with new SST change [1] requiring units for
memHierarchy's backend.mem_size parameter.

[1] c901abb4e7

Change-Id: I19fa09bec8aa453dc52d154598a4ebb20ea304d8
2016-09-20 15:51:24 +01:00
Curtis Dunham
0da55e5dbc ext: eliminate warnings in SST connector
Now compiles completely clean.
2016-09-02 14:58:15 +01:00
Curtis Dunham
5c0a7f98f8 commit 15c633eea52f21dae8cb3a195823b3cdec7be491
Author: Curtis Dunham <Curtis.Dunham@arm.com>
    ext: update SST connector for SST 6.0
2016-08-24 14:20:53 +01:00
Mitch Hayenga
c75ff71139 mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.

This is a re-spin of 20264eb after the revert (bd1c6789) and includes
some fixes of that commit.
2016-04-07 09:30:20 -05:00
Andreas Sandberg
be28d96510 Revert power patch sets with unexpected interactions
The following patches had unexpected interactions with the current
upstream code and have been reverted for now:

e07fd01651f3: power: Add support for power models
831c7f2f9e39: power: Low-power idle power state for idle CPUs
4f749e00b667: power: Add power states to ClockedObject

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

--HG--
extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
2016-04-06 19:43:31 +01:00
Mitch Hayenga
8615b27174 mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
2016-04-05 12:39:21 -05:00
Curtis Dunham
b4282af318 ext: fix SST connector
Should work with SST 5.1 and trunk as of right now.
2016-02-04 16:57:59 -06:00
Curtis Dunham
fe32b40269 ext: remove redundant parameter in example SST+gem5 test
The SST connector automatically adds --initialize-only to the gem5
"command line" (as it should); the config script doesn't need it.
2016-01-29 17:47:15 -06:00
Curtis Dunham
7c4a6604b9 ext: fix SST connector
Writeback no longer a MemCmd.
2015-12-08 14:30:31 -06:00
Curtis Dunham
83e07c07f9 ext: fix SST connector
The renamings in changesets 8f5993cf (2015-03-23) "mem: rename
Locked/LOCKED to LockedRMW/LOCKED_RMW" and fdd4a895 (2015-07-03)
"mem: Split WriteInvalidateReq into write and invalidate" broke the
SST connector.  This commit repeats those renamings in ext/sst.
2015-10-06 18:08:28 -05:00
Curtis Dunham
c3268f8820 config: Support full-system with SST's memory system
This patch adds an example configuration in ext/sst/tests/ that allows
an SST/gem5 instance to simulate a 4-core AArch64 system with SST's
memHierarchy components providing all the caches and memories.
2015-04-08 15:56:06 -05:00
Curtis Dunham
f05cb84ed1 ext: Add SST connector
This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
2015-04-08 15:56:06 -05:00