config: Support full-system with SST's memory system
This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories.
This commit is contained in:
Curtis Dunham
parent
f05cb84ed1
commit
c3268f8820
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@ -1,4 +1,4 @@
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# Copyright (c) 2012-2013 ARM Limited
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# Copyright (c) 2012-2013, 2015 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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@ -46,6 +46,13 @@ from m5.objects import *
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from Caches import *
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def config_cache(options, system):
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if options.external_memory_system and (options.caches or options.l2cache):
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print "External caches and internal caches are exclusive options.\n"
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sys.exit(1)
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if options.external_memory_system:
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ExternalCache = ExternalCacheFactory(options.external_memory_system)
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if options.cpu_type == "arm_detailed":
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try:
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from O3_ARM_v7a import *
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@ -114,10 +121,50 @@ def config_cache(options, system):
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system.cpu[i].dcache = dcache_real
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system.cpu[i].dcache_mon = dcache_mon
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elif options.external_memory_system:
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# These port names are presented to whatever 'external' system
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# gem5 is connecting to. Its configuration will likely depend
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# on these names. For simplicity, we would advise configuring
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# it to use this naming scheme; if this isn't possible, change
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# the names below.
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if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
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system.cpu[i].addPrivateSplitL1Caches(
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ExternalCache("cpu%d.icache" % i),
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ExternalCache("cpu%d.dcache" % i),
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ExternalCache("cpu%d.itb_walker_cache" % i),
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ExternalCache("cpu%d.dtb_walker_cache" % i))
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else:
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system.cpu[i].addPrivateSplitL1Caches(
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ExternalCache("cpu%d.icache" % i),
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ExternalCache("cpu%d.dcache" % i))
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system.cpu[i].createInterruptController()
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if options.l2cache:
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system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
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elif options.external_memory_system:
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system.cpu[i].connectUncachedPorts(system.membus)
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else:
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system.cpu[i].connectAllPorts(system.membus)
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return system
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# ExternalSlave provides a "port", but when that port connects to a cache,
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# the connecting CPU SimObject wants to refer to its "cpu_side".
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# The 'ExternalCache' class provides this adaptation by rewriting the name,
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# eliminating distracting changes elsewhere in the config code.
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class ExternalCache(ExternalSlave):
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def __getattr__(cls, attr):
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if (attr == "cpu_side"):
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attr = "port"
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return super(ExternalSlave, cls).__getattr__(attr)
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def __setattr__(cls, attr, value):
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if (attr == "cpu_side"):
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attr = "port"
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return super(ExternalSlave, cls).__setattr__(attr, value)
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def ExternalCacheFactory(port_type):
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def make(name):
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return ExternalCache(port_data=name, port_type=port_type,
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addr_ranges=[AllMemory])
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return make
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@ -1,4 +1,4 @@
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# Copyright (c) 2010-2012 ARM Limited
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# Copyright (c) 2010-2012, 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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@ -203,7 +203,8 @@ def makeSparcSystem(mem_mode, mdesc=None):
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return self
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def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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dtb_filename=None, bare_metal=False, cmdline=None):
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dtb_filename=None, bare_metal=False, cmdline=None,
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external_memory=""):
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assert machine_type
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if bare_metal:
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@ -293,7 +294,15 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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'lpj=19988480 norandmaps rw loglevel=8 ' + \
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'mem=%(mem)s root=%(rootdev)s'
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self.realview.setupBootLoader(self.membus, self, binary)
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# When using external memory, gem5 writes the boot loader to nvmem
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# and then SST will read from it, but SST can only get to nvmem from
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# iobus, as gem5's membus is only used for initialization and
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# SST doesn't use it. Attaching nvmem to iobus solves this issue.
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# During initialization, system_port -> membus -> iobus -> nvmem.
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if external_memory:
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self.realview.setupBootLoader(self.iobus, self, binary)
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else:
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self.realview.setupBootLoader(self.membus, self, binary)
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.flags_addr = self.realview.realview_io.pio_addr + 0x30
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@ -322,7 +331,24 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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self.boot_osflags = fillInCmdline(mdesc, cmdline)
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self.realview.attachOnChipIO(self.membus, self.bridge)
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if external_memory:
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# I/O traffic enters iobus
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self.external_io = ExternalMaster(port_data="external_io",
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port_type=external_memory)
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self.external_io.port = self.iobus.slave
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# Ensure iocache only receives traffic destined for (actual) memory.
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self.iocache = ExternalSlave(port_data="iocache",
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port_type=external_memory,
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addr_ranges=self.mem_ranges)
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self.iocache.port = self.iobus.master
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# Let system_port get to nvmem and nothing else.
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self.bridge.ranges = [self.realview.nvmem.range]
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self.realview.attachOnChipIO(self.iobus)
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else:
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self.realview.attachOnChipIO(self.membus, self.bridge)
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self.realview.attachIO(self.iobus)
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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@ -189,6 +189,14 @@ def config_mem(options, system):
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them.
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"""
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if options.external_memory_system:
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system.external_memory = m5.objects.ExternalSlave(
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port_type=options.external_memory_system,
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port_data="init_mem0", port=system.membus.master,
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addr_ranges=system.mem_ranges)
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system.kernel_addr_check = False
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return
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nbr_mem_ctrls = options.mem_channels
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import math
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from m5.util import fatal
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@ -104,6 +104,8 @@ def addCommonOptions(parser):
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parser.add_option("--memchecker", action="store_true")
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# Cache Options
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parser.add_option("--external-memory-system", type="string",
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help="use external ports of this port_type for caches")
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parser.add_option("--caches", action="store_true")
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parser.add_option("--l2cache", action="store_true")
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parser.add_option("--fastmem", action="store_true")
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@ -98,7 +98,8 @@ def build_test_system(np):
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test_sys = makeArmSystem(test_mem_mode, options.machine_type,
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options.num_cpus, bm[0], options.dtb_filename,
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bare_metal=options.bare_metal,
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cmdline=cmdline)
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cmdline=cmdline,
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external_memory=options.external_memory_system)
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if options.enable_context_switch_stats_dump:
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test_sys.enable_context_switch_stats_dump = True
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else:
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@ -185,7 +186,7 @@ def build_test_system(np):
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test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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else:
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elif not options.external_memory_system:
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test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
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test_sys.iobridge.slave = test_sys.iobus.master
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test_sys.iobridge.master = test_sys.membus.slave
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199
ext/sst/tests/test6_arm_4c.py
Normal file
199
ext/sst/tests/test6_arm_4c.py
Normal file
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@ -0,0 +1,199 @@
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# Copyright (c)2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Curtis Dunham
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import sst
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import sys
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import os
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lat="1 ns"
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buslat="2 ns"
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clockRate = "1GHz"
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def getenv(name):
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res = ""
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try:
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res = os.environ[name]
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except KeyError:
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pass
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return res
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baseCacheParams = ({
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"debug" :getenv("DEBUG"),
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"debug_level" : 6,
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"coherence_protocol" : "MSI",
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"replacement_policy" : "LRU",
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"cache_line_size" : 64,
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"cache_frequency" : clockRate,
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"statistics" : 1
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})
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l1CacheParams = ({
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"debug" : getenv("DEBUG"),
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"debug_level" : 6,
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"L1" : 1,
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"cache_size" : "64 KB",
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"associativity" : 4,
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"access_latency_cycles" : 2,
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"low_network_links" : 1
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})
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l2CacheParams = ({
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"debug" : getenv("DEBUG"),
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"debug_level" : 6,
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"L1" : 0,
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"cache_size" : "256 KB",
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"associativity" : 8,
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"access_latency_cycles" : 8,
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"high_network_links" : 1,
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"mshr_num_entries" : 4096,
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"low_network_links" : 1
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})
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GEM5 = sst.Component("system", "gem5.gem5")
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GEM5.addParams({
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"comp_debug" : getenv("GEM5_DEBUG"),
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"gem5DebugFlags" : getenv("M5_DEBUG"),
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"frequency" : clockRate,
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"cmd" : "configs/example/fs.py --num-cpus 4 --disk-image=vexpress64-openembedded_minimal-armv8_20130623-376.img --root-device=/dev/sda2 --kernel=vmlinux.aarch64.20140821 --dtb-filename=vexpress.aarch64.20140821.dtb --mem-size=256MB --machine-type=VExpress_EMM64 --cpu-type=timing --external-memory-system=sst --initialize-only"
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})
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bus = sst.Component("membus", "memHierarchy.Bus")
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bus.addParams({
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"bus_frequency": "2GHz",
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"debug" : getenv("DEBUG"),
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"debug_level" : 8
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})
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def buildL1(name, m5, connector):
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cache = sst.Component(name, "memHierarchy.Cache")
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cache.addParams(baseCacheParams)
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cache.addParams(l1CacheParams)
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link = sst.Link("cpu_%s_link"%name)
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link.connect((m5, connector, lat), (cache, "high_network_0", lat))
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return cache
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SysBusConn = buildL1("gem5SystemBus", GEM5, "system.external_memory.port")
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bus_port = 0
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link = sst.Link("sysbus_bus_link")
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link.connect((SysBusConn, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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bus_port = bus_port + 1
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ioCache = buildL1("ioCache", GEM5, "system.iocache.port")
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ioCache.addParams({
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"debug" : 0,
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"debug_level" : 6,
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"cache_size" : "16 KB",
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"associativity" : 4
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})
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link = sst.Link("ioCache_bus_link")
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link.connect((ioCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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def buildCPU(m5, num):
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l1iCache = buildL1("cpu%u.l1iCache" % num, m5, "system.cpu%u.icache.port" % num)
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l1dCache = buildL1("cpu%u.l1dCache" % num, m5, "system.cpu%u.dcache.port" % num)
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itlbCache = buildL1("cpu%u.itlbCache" % num, m5, "system.cpu%u.itb_walker_cache.port" % num)
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dtlbCache = buildL1("cpu%u.dtlbCache" % num, m5, "system.cpu%u.dtb_walker_cache.port" % num)
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l1dCache.addParams({
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"debug" : 0,
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"debug_level" : 10,
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"snoop_l1_invalidations" : 1
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})
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global bus_port
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link = sst.Link("cpu%u.l1iCache_bus_link" % num) ; bus_port = bus_port + 1
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link.connect((l1iCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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link = sst.Link("cpu%u.l1dCache_bus_link" % num) ; bus_port = bus_port + 1
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link.connect((l1dCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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link = sst.Link("cpu%u.itlbCache_bus_link" % num) ; bus_port = bus_port + 1
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link.connect((itlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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link = sst.Link("cpu%u.dtlbCache_bus_link" % num) ; bus_port = bus_port + 1
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link.connect((dtlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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buildCPU(GEM5, 0)
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buildCPU(GEM5, 1)
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buildCPU(GEM5, 2)
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buildCPU(GEM5, 3)
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l2cache = sst.Component("l2cache", "memHierarchy.Cache")
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l2cache.addParams(baseCacheParams)
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l2cache.addParams(l2CacheParams)
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l2cache.addParams({
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"network_address" : "2",
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"directory_at_next_level" : "1"
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})
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link = sst.Link("l2cache_bus_link")
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link.connect((l2cache, "high_network_0", buslat), (bus, "low_network_0", buslat))
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memory = sst.Component("memory", "memHierarchy.MemController")
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memory.addParams({
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"request_width" : 64,
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"coherence_protocol" : "MSI",
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"access_time" : "25 ns",
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"backend.mem_size" : 256,
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"clock" : "2GHz",
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"debug" : getenv("DEBUG"),
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"range_start" : 0, # 2 * (1024 ** 3), # it's behind a directory controller.
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})
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comp_chiprtr = sst.Component("chiprtr", "merlin.hr_router")
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comp_chiprtr.addParams({
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"xbar_bw" : "16GB/s",
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"link_bw" : "16GB/s",
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"input_buf_size" : "1KB",
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"num_ports" : "3",
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"flit_size" : "72B",
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"output_buf_size" : "1KB",
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"id" : "0",
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"topology" : "merlin.singlerouter"
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})
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comp_dirctrl = sst.Component("dirctrl", "memHierarchy.DirectoryController")
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comp_dirctrl.addParams({
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"coherence_protocol" : "MSI",
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"network_address" : "1",
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"entry_cache_size" : "16384",
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"network_bw" : "1GB/s",
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"addr_range_start" : 2 * (1024 ** 3),
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"addr_range_end" : 2 * (1024 ** 3) + 256 * (1024 ** 2)
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})
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sst.Link("link_cache_net_0").connect((l2cache, "directory", "10ns"), (comp_chiprtr, "port2", "2ns"))
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sst.Link("link_dir_net_0").connect((comp_chiprtr, "port1", "2ns"), (comp_dirctrl, "network", "2ns"))
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sst.Link("l2cache_io_link").connect((comp_chiprtr, "port0", "2ns"), (GEM5, "network", buslat))
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sst.Link("link_dir_mem_link").connect((comp_dirctrl, "memory", "10ns"), (memory, "direct_link", "10ns"))
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@ -1,4 +1,4 @@
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# Copyright (c) 2009-2014 ARM Limited
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# Copyright (c) 2009-2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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@ -509,21 +509,22 @@ class VExpress_EMM(RealView):
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# Attach I/O devices that are on chip and also set the appropriate
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# ranges for the bridge
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def attachOnChipIO(self, bus, bridge):
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self.gic.pio = bus.master
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self.local_cpu_timer.pio = bus.master
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if hasattr(self, "gicv2m"):
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self.gicv2m.pio = bus.master
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self.hdlcd.dma = bus.slave
|
||||
# Bridge ranges based on excluding what is part of on-chip I/O
|
||||
# (gic, a9scu)
|
||||
bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
|
||||
AddrRange(0x2B000000, size='4MB'),
|
||||
AddrRange(0x30000000, size='256MB'),
|
||||
AddrRange(0x40000000, size='512MB'),
|
||||
AddrRange(0x18000000, size='64MB'),
|
||||
AddrRange(0x1C000000, size='64MB')]
|
||||
self.vgic.pio = bus.master
|
||||
def attachOnChipIO(self, bus, bridge=None):
|
||||
self.gic.pio = bus.master
|
||||
self.vgic.pio = bus.master
|
||||
self.local_cpu_timer.pio = bus.master
|
||||
if hasattr(self, "gicv2m"):
|
||||
self.gicv2m.pio = bus.master
|
||||
self.hdlcd.dma = bus.slave
|
||||
if bridge:
|
||||
# Bridge ranges based on excluding what is part of on-chip I/O
|
||||
# (gic, a9scu)
|
||||
bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
|
||||
AddrRange(0x2B000000, size='4MB'),
|
||||
AddrRange(0x30000000, size='256MB'),
|
||||
AddrRange(0x40000000, size='512MB'),
|
||||
AddrRange(0x18000000, size='64MB'),
|
||||
AddrRange(0x1C000000, size='64MB')]
|
||||
|
||||
|
||||
# Set the clock domain for IO objects that are considered
|
||||
|
|
|
|||
Loading…
Reference in a new issue