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commit 15c633eea52f21dae8cb3a195823b3cdec7be491

Browse source 
Author: Curtis Dunham <Curtis.Dunham@arm.com>
    ext: update SST connector for SST 6.0
This commit is contained in:
Curtis Dunham 2016-08-24 14:20:53 +01:00
parent d1abc287f6
commit 5c0a7f98f8
8 changed files with 20 additions and 21 deletions
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2
ext/sst/ExtMaster.cc
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@ -48,7 +48,7 @@
#undef fatal
#endif
#include <sst_config.h>
#include <core/sst_config.h>
#include <mem/packet.hh>

1
ext/sst/ExtMaster.hh
View file

@ -48,7 +48,6 @@
#include <list>
#include <set>
#include <sst/core/serialization.h>
#include <sst/core/component.h>
#include <sst/elements/memHierarchy/memEvent.h>

3
ext/sst/ExtSlave.cc
View file

@ -44,8 +44,7 @@
#include "gem5.hh"
#include <sst_config.h>
#include <sst/core/serialization.h>
#include <core/sst_config.h>
#include <sst/core/params.h>
#include <sst/core/output.h>

1
ext/sst/ExtSlave.hh
View file

@ -45,7 +45,6 @@
#ifndef EXT_SST_EXTSLAVE_HH
#define EXT_SST_EXTSLAVE_HH
#include <sst/core/serialization.h>
#include <sst/core/component.h>
#include <sst/core/output.h>
#include <sst/core/interfaces/simpleMem.h>

3
ext/sst/gem5.cc
View file

@ -42,9 +42,8 @@
//
// For license information, see the LICENSE file in the current directory.
#include <sst_config.h>
#include <core/sst_config.h>
#include <Python.h> // Before serialization to prevent spurious warnings
#include <sst/core/serialization.h>
#include "gem5.hh"

1
ext/sst/gem5.hh
View file

@ -48,7 +48,6 @@
#include <string>
#include <vector>
#include <sst/core/serialization.h>
#include <sst/core/component.h>
#include <sst/core/output.h>

3
ext/sst/libgem5.cc
View file

@ -42,9 +42,8 @@
//
// For license information, see the LICENSE file in the current directory.
#include <sst_config.h>
#include <core/sst_config.h>
#include <sst/core/serialization.h>
#include <sst/core/element.h>
#include <sst/core/component.h>

27
ext/sst/tests/test6_arm_4c.py
View file

@ -52,18 +52,24 @@ def getenv(name):
pass
return res
def debug(d):
try:
r = int(getenv(d))
except ValueError:
return 0
return r
baseCacheParams = ({
"debug" :getenv("DEBUG"),
"debug" :debug("DEBUG"),
"debug_level" : 6,
"coherence_protocol" : "MSI",
"replacement_policy" : "LRU",
"cache_line_size" : 64,
"cache_frequency" : clockRate,
"statistics" : 1
"cache_frequency" : clockRate
})
l1CacheParams = ({
"debug" : getenv("DEBUG"),
"debug" : debug("DEBUG"),
"debug_level" : 6,
"L1" : 1,
"cache_size" : "64 KB",
@ -73,7 +79,7 @@ l1CacheParams = ({
})
l2CacheParams = ({
"debug" : getenv("DEBUG"),
"debug" : debug("DEBUG"),
"debug_level" : 6,
"L1" : 0,
"cache_size" : "256 KB",
@ -87,8 +93,8 @@ l2CacheParams = ({
GEM5 = sst.Component("system", "gem5.gem5")
GEM5.addParams({
"comp_debug" : getenv("GEM5_DEBUG"),
"gem5DebugFlags" : getenv("M5_DEBUG"),
"comp_debug" : debug("GEM5_DEBUG"),
"gem5DebugFlags" : debug("M5_DEBUG"),
"frequency" : clockRate,
"cmd" : "configs/example/fs.py --num-cpus 4 --disk-image=vexpress64-openembedded_minimal-armv8_20130623-376.img --root-device=/dev/sda2 --kernel=vmlinux.aarch64.20140821 --dtb-filename=vexpress.aarch64.20140821.dtb --mem-size=256MB --machine-type=VExpress_EMM64 --cpu-type=timing --external-memory-system=sst"
})
@ -96,7 +102,7 @@ GEM5.addParams({
bus = sst.Component("membus", "memHierarchy.Bus")
bus.addParams({
"bus_frequency": "2GHz",
"debug" : getenv("DEBUG"),
"debug" : debug("DEBUG"),
"debug_level" : 8
})
@ -154,8 +160,7 @@ l2cache = sst.Component("l2cache", "memHierarchy.Cache")
l2cache.addParams(baseCacheParams)
l2cache.addParams(l2CacheParams)
l2cache.addParams({
"network_address" : "2",
"directory_at_next_level" : "1"
"network_address" : "2"
})
link = sst.Link("l2cache_bus_link")
@ -168,7 +173,7 @@ memory.addParams({
"access_time" : "25 ns",
"backend.mem_size" : 256,
"clock" : "2GHz",
"debug" : getenv("DEBUG"),
"debug" : debug("DEBUG"),
"range_start" : 0, # 2 * (1024 ** 3), # it's behind a directory controller.
})