commit 15c633eea52f21dae8cb3a195823b3cdec7be491
Author: Curtis Dunham <Curtis.Dunham@arm.com> ext: update SST connector for SST 6.0
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8 changed files with 20 additions and 21 deletions
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@ -48,7 +48,7 @@
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#undef fatal
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#endif
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#include <sst_config.h>
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#include <core/sst_config.h>
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#include <mem/packet.hh>
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@ -48,7 +48,6 @@
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#include <list>
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#include <set>
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#include <sst/core/serialization.h>
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#include <sst/core/component.h>
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#include <sst/elements/memHierarchy/memEvent.h>
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@ -44,8 +44,7 @@
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#include "gem5.hh"
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#include <sst_config.h>
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#include <sst/core/serialization.h>
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#include <core/sst_config.h>
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#include <sst/core/params.h>
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#include <sst/core/output.h>
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@ -45,7 +45,6 @@
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#ifndef EXT_SST_EXTSLAVE_HH
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#define EXT_SST_EXTSLAVE_HH
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#include <sst/core/serialization.h>
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#include <sst/core/component.h>
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#include <sst/core/output.h>
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#include <sst/core/interfaces/simpleMem.h>
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@ -42,9 +42,8 @@
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//
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// For license information, see the LICENSE file in the current directory.
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#include <sst_config.h>
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#include <core/sst_config.h>
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#include <Python.h> // Before serialization to prevent spurious warnings
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#include <sst/core/serialization.h>
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#include "gem5.hh"
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@ -48,7 +48,6 @@
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#include <string>
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#include <vector>
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#include <sst/core/serialization.h>
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#include <sst/core/component.h>
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#include <sst/core/output.h>
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@ -42,9 +42,8 @@
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//
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// For license information, see the LICENSE file in the current directory.
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#include <sst_config.h>
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#include <core/sst_config.h>
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#include <sst/core/serialization.h>
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#include <sst/core/element.h>
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#include <sst/core/component.h>
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@ -52,18 +52,24 @@ def getenv(name):
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pass
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return res
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def debug(d):
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try:
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r = int(getenv(d))
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except ValueError:
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return 0
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return r
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baseCacheParams = ({
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"debug" :getenv("DEBUG"),
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"debug" :debug("DEBUG"),
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"debug_level" : 6,
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"coherence_protocol" : "MSI",
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"replacement_policy" : "LRU",
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"cache_line_size" : 64,
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"cache_frequency" : clockRate,
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"statistics" : 1
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"cache_frequency" : clockRate
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})
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l1CacheParams = ({
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"debug" : getenv("DEBUG"),
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"debug" : debug("DEBUG"),
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"debug_level" : 6,
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"L1" : 1,
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"cache_size" : "64 KB",
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@ -73,7 +79,7 @@ l1CacheParams = ({
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})
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l2CacheParams = ({
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"debug" : getenv("DEBUG"),
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"debug" : debug("DEBUG"),
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"debug_level" : 6,
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"L1" : 0,
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"cache_size" : "256 KB",
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@ -87,8 +93,8 @@ l2CacheParams = ({
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GEM5 = sst.Component("system", "gem5.gem5")
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GEM5.addParams({
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"comp_debug" : getenv("GEM5_DEBUG"),
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"gem5DebugFlags" : getenv("M5_DEBUG"),
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"comp_debug" : debug("GEM5_DEBUG"),
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"gem5DebugFlags" : debug("M5_DEBUG"),
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"frequency" : clockRate,
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"cmd" : "configs/example/fs.py --num-cpus 4 --disk-image=vexpress64-openembedded_minimal-armv8_20130623-376.img --root-device=/dev/sda2 --kernel=vmlinux.aarch64.20140821 --dtb-filename=vexpress.aarch64.20140821.dtb --mem-size=256MB --machine-type=VExpress_EMM64 --cpu-type=timing --external-memory-system=sst"
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})
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@ -96,7 +102,7 @@ GEM5.addParams({
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bus = sst.Component("membus", "memHierarchy.Bus")
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bus.addParams({
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"bus_frequency": "2GHz",
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"debug" : getenv("DEBUG"),
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"debug" : debug("DEBUG"),
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"debug_level" : 8
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})
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@ -154,8 +160,7 @@ l2cache = sst.Component("l2cache", "memHierarchy.Cache")
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l2cache.addParams(baseCacheParams)
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l2cache.addParams(l2CacheParams)
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l2cache.addParams({
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"network_address" : "2",
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"directory_at_next_level" : "1"
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"network_address" : "2"
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})
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link = sst.Link("l2cache_bus_link")
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@ -168,7 +173,7 @@ memory.addParams({
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"access_time" : "25 ns",
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"backend.mem_size" : 256,
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"clock" : "2GHz",
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"debug" : getenv("DEBUG"),
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"debug" : debug("DEBUG"),
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"range_start" : 0, # 2 * (1024 ** 3), # it's behind a directory controller.
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})
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