Get rid of addPort().
Change getPort() behavior on PhysicalMemory.
SConscript:
cpu/simple/cpu.hh:
sim/system.cc:
sim/system.hh:
Replace Memory with MemObject.
cpu/base.hh:
No need to declare Port here anymore.
cpu/cpu_exec_context.hh:
Need PageTable definition.
cpu/simple/cpu.cc:
mem/physical.cc:
mem/physical.hh:
Replace Memory with MemObject.
Get rid of addPort(); allow getting anonymous ports with getPort().
mem/translating_port.hh:
Remove unneeded header.
sim/process.cc:
Replace Memory with MemObject.
Change how initialization port gets set up to deal with change in
addPort()/getPort(). Current solution is not ideal but it works.
sim/process.hh:
Remove unneeded headers and declarations.
Make LiveProcess::getDesc() abstract instead of panicing if called.
sim/syscall_emul.hh:
Fix includes.
--HG--
extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f
- Get rid of unused ProxyMemory class (replaced by TranslatingPort).
- Get rid of remaining unused prot_* functions.
mem/physical.cc:
mem/physical.hh:
mem/port.hh:
Get rid of remaining unused prot_* functions.
--HG--
extra : convert_revision : f16c208f4e4c38bd6bb3626339674c9278da9e07
Ignoring returned latency for now.
Refactored loadSections in ObjectFile hierarchy.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
Have each section record a pointer to image data.
This allows us to move common loadSections code into ObjectFile.
base/loader/object_file.cc:
Have each section record a pointer to image data.
This allows us to move common loadSections code into ObjectFile.
Also explicitly load BSS now since we need to allocate the
translations for it in syscall emulation.
cpu/base.hh:
Don't need memPort (just pass port in to ExecContext constructor).
cpu/exec_context.cc:
cpu/exec_context.hh:
mem/port.cc:
mem/translating_port.cc:
mem/translating_port.hh:
Pass syscall emulation Port into constructor instead of
getting it from BaseCPU.
cpu/simple/cpu.cc:
Explicitly choose one of three timing models.
Statically allocate request and packet objects when possible.
Several more minor bug fixes.
Works for simple program with SIMPLE_CPU_MEM_IMMEDIATE model now.
Probably have memory leaks with SIMPLE_CPU_MEM_TIMING (if it works at all).
Pass syscall emulation Port into constructor instead of
getting it from BaseCPU.
cpu/simple/cpu.hh:
Explicitly choose one of three timing models.
Statically allocate request and packet objects when possible.
Pass syscall emulation Port into constructor instead of
getting it from BaseCPU.
mem/physical.cc:
Set packet result field.
--HG--
extra : convert_revision : 359d0ebe4b4665867f4e26e7394ec0f1d17cfc26
See configs/test.py for test config (using simple
binary in my home directory on zizzer).
base/chunk_generator.hh:
Fix assertion for chunkSize == 0 (not a power of 2)
base/intmath.hh:
Fix roundDown to take integer alignments.
cpu/base.cc:
Register exec contexts regardless of state (not sure why
this check was in here in the first place).
mem/physical.cc:
Add breaks to switch.
python/m5/objects/BaseCPU.py:
Default mem to Parent.any (e.g. get from System).
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
HierParams is gone.
python/m5/objects/PhysicalMemory.py:
mmu param is full-system only.
sim/process.cc:
Stack mapping request must be page-aligned and page-sized.
Don't delete objFile object in create since we are counting
on it being around for startup().
--HG--
extra : convert_revision : 90c43ee927e7d82a045d6e10302d965797d006f7
Ready to start testing if I could fix the linking errors I can't ever seem to fix.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Add connecting of ports until builder can handle it.
mem/physical.cc:
Add function to allocate a port in the object
Remove some full_sys stuff untill needed
mem/physical.hh:
Add function to allocate a port in the object
python/m5/objects/BaseCPU.py:
Update the params
sim/process.cc:
Make sure to use the right name (hopefully CPU constructor already called)
--HG--
extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85
Clean out old memory python files, move them into old_mem directory. Maybe we should just delete them, they are under revision control.
Add new py files for new objects.
SConscript:
Update because memory is just a header file now
base/chunk_generator.hh:
Make Chunk Generator return the entire size if the chunk_size is set to zero. Useful when trying to chunck on blocksize of memory, which can write large pieces of data.
cpu/simple/cpu.cc:
Make sure to delete the pkt.
mem/physical.cc:
mem/physical.hh:
Set up response event.
mem/port.cc:
Rename rqst to req to conform to same standard naming convention.
python/m5/objects/PhysicalMemory.py:
Update the params, inheritence
--HG--
extra : convert_revision : 857154ec256522baf423b715833930497999549b
mem/physical.cc:
Remove unneeded functions. Need to add a .toString option for commands to making printing prettier.
mem/physical.hh:
Remove unneeded functions.
--HG--
extra : convert_revision : 3707d317f542d56c0a0758a2c5ba493b92fb0c87
The Memory is now a pure virtual base class for all memory type objects (DRAM, physical).
We should consider renaming MemObject to something more meaningful to represent it is for all memory heirarchy objects, perhaps MemHeirObject?
mem/physical.cc:
mem/physical.hh:
Move the port from the base class into the actual object.
--HG--
extra : convert_revision : b7754ee7b90fd8f816f9876dce374c1d43c7e34b
mem/physical.cc:
Return 0 for block size. The chunk generator should treat this as a infinite size.
mem/physical.hh:
Add function prototype
mem/port.hh:
Fix function to take no arguments
mem/translating_port.cc:
mem/translating_port.hh:
Remove the memsetBlob because it doesn't exist yet.
--HG--
extra : convert_revision : dfe352acfc2912ecc9a1ba1863e5666f46b991cc
mem/physical.cc:
Implement the blockSize function, return VMPageSize for the physical memory
mem/port.hh:
Add a function to get a pointer to a peer, needed for initVirtMem to work in the loader.
sim/process.cc:
The way the translating port is setup we don't want the memory port, we want the peer port associated with that memory. We may need to revisit this.
--HG--
extra : convert_revision : 46a51d448d1683db7bd5afe64adbe167a5743060
mem/mem_object.hh:
Create constrtor so it compiles
mem/packet.hh:
Fix typedefs so they compile, add in a few more headers for compilation
mem/page_table.cc:
convert to new mem system so it compiles
mem/page_table.hh:
fix it to the version that had asid support. Make it compile in the new system
mem/physical.cc:
Fix some compilation bugs
mem/physical.hh:
Add a type that made compile fail
mem/port.hh:
Fix a spelling error that messed up compilation
mem/request.hh:
fix typedefs and forward declerations so it compiles
--HG--
extra : convert_revision : 580fb1ba31ada799ff0122601b8b5a8d994bb8af
mem/physical.cc:
mem/physical.hh:
Added a stripped down version of the physical memory object
--HG--
extra : convert_revision : 26826fb316f4cac900ec648fa268f1d95bc960f1
