Commit graph

184 commits

Author SHA1 Message Date
Nathan Binkert
9aed27efb3 style: fix stupid bugs
--HG--
extra : convert_revision : ef3dcc3a160eb19a6c4fcdcd411d392aa42e4efe
2007-07-28 16:55:51 -07:00
Nathan Binkert
c27e23f2e8 style: Check/Fix whitespace on SCons files
--HG--
extra : convert_revision : 46e6b2dd8e1984cbab0ea24c94760794734c0f95
2007-07-28 16:49:20 -07:00
Nathan Binkert
abc76f20cb Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python.  Parameter objects
are generated and initialized by python.  The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.

--HG--
extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-23 21:51:38 -07:00
Nathan Binkert
552097b92e Allow the fixwhite stuff to work when committing from a subdir
--HG--
extra : convert_revision : 10e6ecc60bb8ee4e4a6f06f8c56550299c262c91
2007-07-23 20:55:57 -07:00
Nathan Binkert
089fce4f59 do proper style checks for merged files
--HG--
extra : convert_revision : f9d4c61ded4b13655dbe86f0bb6a0b3beaf45151
2007-07-22 13:45:12 -07:00
Nathan Binkert
78759ad176 fix the style fixing thing
--HG--
extra : convert_revision : 65ffc14e7b78b49df9a67ef0d3521551dd44d1cd
2007-07-22 09:08:05 -07:00
Nathan Binkert
4b5ba96d38 Add code to turn the style stuff into a mercurial hook.
Nag the user during compile if they have an hg cloned copy of M5, have
mercurial installed, but don't have the style hook enabled.

--HG--
extra : convert_revision : 6bcbb67f1a3fcd36db7d3ef16a9ff19680f126f2
2007-07-21 22:33:08 -07:00
Nathan Binkert
4f0f217c1b Get rid of GNU libelf and its autoconf nastiness and replace
it with FreeBSD's implementation

--HG--
extra : convert_revision : ef9c4551b9a6b54b76a89f286ff9804c55790621
2007-05-26 18:15:22 -07:00
Nathan Binkert
b5037ad82b Actually move the time two minutes into the future to make sure
that we get the result that we want

--HG--
extra : convert_revision : d3e1aca921705fe8c8b955229c2afcd2aa9b36ea
2007-04-27 12:15:25 -07:00
Nathan Binkert
0ae6f03439 Make sure that we don't rebuild libelf stuff that we don't
have to since it doesn't work well on non-linux

--HG--
extra : convert_revision : 2f1f81f756cccf25f1b2b04e6b5ca4b7a20e96b7
2007-04-27 11:15:15 -07:00
Nathan Binkert
5825104982 update the stuff that's removed from the SConscripts
since things have moved around a bit

--HG--
extra : convert_revision : 79322a65af6140d0c41aed0b381587eb05d72fd9
2007-04-18 16:56:06 -07:00
Ali Saidi
438b951a5b add code to whack the intel gbe model from the relase.... it's not tested and it's configuration is a hack
--HG--
extra : convert_revision : b65cd6d9b45a67ba64ea398cf0c0ce28f91c7e27
2007-04-09 18:49:02 -04:00
Gabe Black
b33f4623ab Update to statetrace. This will break it, but I want to make sure it gets into mercurial.
--HG--
extra : convert_revision : 6960d2f728c85e99e32bf9b752e45b3cb5e30e3e
2007-03-15 06:10:50 -04:00
Ali Saidi
9d026ac006 fix regress... SPARC_FS may not be in the builds so check for it
--HG--
extra : convert_revision : 16710e4c44bd34496ed31ae8e954544b06e92589
2007-03-09 16:27:24 -05:00
Ali Saidi
ea7bdf9f60 Merge zizzer:/bk/newmem
into  udhcp-macvpn-108.public.engin.umich.edu:/Users/ali/work/m5.newmem

--HG--
extra : convert_revision : c6b11f535cca7fd46f1a3cea3b5a966e8fa80347
2007-03-07 12:46:03 -05:00
Ali Saidi
44b732691f If we're running the quick tests, remove the SPARC_FS build since we don't have any quick SPARC_FS tests at the moment
--HG--
extra : convert_revision : 4505f1600cae5d049560f3b397541e9a9dea0420
2007-03-07 12:45:21 -05:00
Gabe Black
f776ec84c1 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace

--HG--
extra : convert_revision : 0959fb162253ff1eed8da0a990f58897322f0e1f
2007-03-05 20:54:36 -05:00
Gabe Black
9b72ff8290 Fixing statetrace to work with 32 bit SPARC processes, as well as rewritting it's single stepping code.
--HG--
extra : convert_revision : 69b1668a850519ab98b02c525ec41ff727eb6036
2007-03-05 20:54:20 -05:00
Ali Saidi
a81143f06a add a sparc fs regression
src/dev/sparc/iob.cc:
    don't warn on cpu restart/idle/halt stuff
tests/SConscript:
    add sparc target in test Sconscript
util/regress:
    Add SPARC_FS target in regress

--HG--
extra : convert_revision : 37fa21700ec4c350d87ca9723bc3359feb81c50a
2007-03-03 22:45:26 -05:00
Ali Saidi
cf0e202cba make m5 readfile work on solaris... we can have a solaris regression soon!
src/arch/sparc/isa/decoder.isa:
    add readfile and break to sparc decoder
src/arch/sparc/isa/operands.isa:
    fix O0-O5 operands registers
util/m5/Makefile.sparc:
    Make sparc makefile compile a 64bit binary
util/m5/m5.c:
    readfile was in here twice, once will be sufficient I think
util/m5/m5op_sparc.S:
    implement readfile and debugbreak

--HG--
extra : convert_revision : 139b3f480ee6342b37b5642e072c8486d91a3944
2007-02-24 22:05:01 -05:00
Ali Saidi
7a2ecf9e26 add pseduo instruction support for sparc
util/m5/Makefile.alpha:
    Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
    Make the makefile more reasonable
util/m5/Makefile.alpha:
    Remove authors from copyright.
util/m5/Makefile.alpha:
    Updated Authors from bk prs info
util/m5/Makefile.alpha:
    bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
    Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
    Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
    split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
    ivle and ivlb aren't used anymore
util/m5/m5op.h:
    stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
    move the op ids into their own header file since we can share them between sparc and alpha

--HG--
rename : util/m5/Makefile => util/m5/Makefile.sparc
rename : util/m5/m5op.S => util/m5/m5op_alpha.S
extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
2007-02-21 21:06:17 -05:00
Steve Reinhardt
98ef836ca6 Use perl FindBin package to set path to rundiff to the
directory where tracediff is.

--HG--
extra : convert_revision : f0cc0af264aa624cbacbf3ba42b6b64f90a8e759
2007-02-06 10:06:11 -08:00
Nathan Binkert
e65544b88b Nate's utility for compiling m5
--HG--
extra : convert_revision : 84b21f667736dfe07891323dcc810437ccb3c7c0
2006-12-17 18:58:50 -08:00
Nathan Binkert
2d09f30a6d Utilities for doing a format check for some elements of proper
m5 style and fixing whitespace.  For whitespace, any tabs in
leading whitespace on a line are converted to spaces, and any
trailing whitespace is removed.

--HG--
extra : convert_revision : d0591663c028a388635fc71c6c1d31f700748cf6
2006-12-17 18:58:05 -08:00
Steve Reinhardt
a7ea4885ce If no tests are specified for regression, just build the binaries
(instead of complaining and exiting).

--HG--
extra : convert_revision : 24ac0bab7fd92d9e74c80847a667f0affcd0473d
2006-12-12 09:54:59 -08:00
Steve Reinhardt
7b25e4091c Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3

--HG--
extra : convert_revision : 7c78ae3298645aed2179ed4f2aa361619406f9de
2006-12-10 01:42:31 -05:00
Steve Reinhardt
96d1efe0a9 Add '-j' option directly to regress script (passed to scons).
--HG--
extra : convert_revision : 9776806b24da70b815280e47d2d5ec8674c82669
2006-12-10 01:42:16 -05:00
Steve Reinhardt
ac32645c27 Change detault regression build from opt to fast.
--HG--
extra : convert_revision : b6db0254b73a97ab6e3685c90cc9cd30ea274d4f
2006-12-07 14:41:56 -05:00
Steve Reinhardt
1431d1f9c2 Merge zizzer.eecs.umich.edu:/bk/newmem
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : 4a077b463b938c54b546b00e586d8609c24ae465
2006-12-02 22:12:26 -08:00
Steve Reinhardt
711dc47e8c Delete src/oldmem.
util/make_release.py:
    src/oldmem gone from repo, no need to delete here.

--HG--
extra : convert_revision : 570fa1b8d7144376cf13a010160a39d1c1cccbc2
2006-12-03 01:11:24 -05:00
Steve Reinhardt
d3e888ff90 Merge zizzer.eecs.umich.edu:/bk/newmem
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : 4c8de6e4c6f729c83e92abd81ea6c1347e647756
2006-12-02 19:52:26 -08:00
Nathan Binkert
5d637417a8 don't blow away the whole destination directory
--HG--
extra : convert_revision : 7370bad15cc30e75ebb0c8685324d8db06fc2936
2006-12-01 22:33:18 -08:00
Nathan Binkert
6e885ec9ba Get rid of the old release-edits script and create make_release.py
which takes care of almost everything needed for putting together
a release.

--HG--
extra : convert_revision : b05d418a1002633b1286591eb8a8588ba33f5df1
2006-11-30 20:50:47 -08:00
Steve Reinhardt
d2a71f6b2a cscope-find.py:
Write directly to 'cscope.files' and run 'cscope -b' .
Now this script does everything automatically.
cscope-index.py:
Rename: util/cscope-find.py -> util/cscope-index.py

util/cscope-find.py:
    Write directly to 'cscope.files' and run 'cscope -b' .
    Now this script does everything automatically.

--HG--
rename : util/cscope-find.py => util/cscope-index.py
extra : convert_revision : cd6fa5cc0c2146f7184c9213956aff67c7cb9341
2006-11-29 13:17:41 -08:00
Steve Reinhardt
28f8318252 Add no-op versions of ivlb and ivle back in for backwards compatibility.
--HG--
extra : convert_revision : 383b72c130b20f3d7cde4e08fa36a481f3c0bf7c
2006-11-24 12:32:33 -05:00
Gabe Black
58f7ed2416 Cleaned up remnants of ivlb and ivle
--HG--
extra : convert_revision : 93b37dbcd3d9dd1eced0f829223f52b53fe58643
2006-11-06 20:49:48 -05:00
Gabe Black
466c387318 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : cb15101d24ef2969e1819d6bdeeb2dd1f23f02d1
2006-10-23 09:44:58 -04:00
Steve Reinhardt
810dee6e98 Have tracediff print warning if no traceflags are set.
Elaborate on description a bit.

--HG--
extra : convert_revision : 2649961b53d6fb2774ddfb60219415ae4251db2d
2006-10-22 12:51:00 -04:00
Steve Reinhardt
0e121bc14f Updated to work with new command line argument ordering.
Note that command line syntax has totally changed as a result.
See comments for more details.

--HG--
extra : convert_revision : bdb6e27abd2da83c7468dfe2a95e8bf54757ac6c
2006-10-21 02:24:27 -07:00
Gabe Black
0b5cf4ba6e Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
2006-10-20 16:39:47 -04:00
Steve Reinhardt
3772e4fc97 m5term: assume localhost if host name not provided.
util/term/term.c:
    Reindent.
util/term/term.c:
    Assume localhost if only port number is given on command line.

--HG--
extra : convert_revision : 768e61a56339a0795ca258cca788e9a2c20cbaae
2006-10-19 21:42:30 -07:00
Gabe Black
76c07ea46b Cleaned up the function a bit to help route out bugs.
--HG--
extra : convert_revision : db9a526bddc8634cea63b42b882f580806066db5
2006-10-19 14:57:06 -04:00
Gabe Black
bb2ab310eb Fixed up exetrace.cc to deal with microcode, and to made floating point register numbers correlate to the numbers used in SPARC in m5 and statetrace.
src/cpu/exetrace.cc:
    Fixed up to deal with microcode, and to make floating point register numbers correlate to the numbers used in SPARC.
util/statetrace/arch/tracechild_sparc.cc:
util/statetrace/arch/tracechild_sparc.hh:
    Make floating point register numbers correlate to the numbers used in SPARC.

--HG--
extra : convert_revision : 878897292f696092453cf61d6eac2d1c407ca13b
2006-10-18 20:52:34 -04:00
Kevin Lim
4ed184eade Merge ktlim@zamp:./local/clean/o3-merge/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
    Hand merge.

--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
2006-09-30 23:43:23 -04:00
Gabe Black
b7d0395126 Adding what was tracedump but is now statetrace to the tree. Let me know if statetrace is also already taken.
util/statetrace/Makefile:
    Makefile to build statetrace. Targets are:

    statetrace: alias to build using the "native" compiler
    statetrace-native: use the native compiler
    statetrace-sparc: use the sparc cross compiler

    I'll make this a little more fancy and capable later.
util/statetrace/arch/tracechild_i386.cc:
    Implementation of i386 support
util/statetrace/arch/tracechild_i386.hh:
    Declaration of i386 support
util/statetrace/arch/tracechild_sparc.cc:
    implementation of SPARC support
util/statetrace/arch/tracechild_sparc.hh:
    declaration of SPARC support
util/statetrace/printer.cc:
    Implementation of the "Printer" objects which parse and output the state of the process after each instruction. There are currently two types of printers, nested ones and register ones. These are called NestingPrinter and RegPrinter respectively.
util/statetrace/printer.hh:
    Declaration of "Printer" objects
util/statetrace/refcnt.hh:
    This is copied from m5. I should use the one already in the tree, but I'll do that later.
util/statetrace/regstate.hh:
    Interface for accessing registers.
util/statetrace/statetrace.cc:
    Main file with argument parsing and the "main" function which contains the tracing loop.
util/statetrace/tracechild.cc:
    Implementation of the base tracechild class.
util/statetrace/tracechild.hh:
    Declaration of the base tracechild class.
util/statetrace/tracechild_arch.cc:
    This file hooks in support for the appropriate architecture. Just the implementation is brought in, since the main program should ideally not have to know anything at all about an architecture other than it's interface.
util/statetrace/x86.format:
    An example output template for x86. A few example SPARC templates will be added later.

--HG--
extra : convert_revision : 7c8bf8230907aba42ed1e707b9ca2d6da0d4e6d4
2006-09-17 03:46:30 -04:00
Ali Saidi
44c6f953b0 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 14ac24236ff65b7e489c1ce4b4e9a295966013b8
2006-09-11 17:57:30 -04:00
Ali Saidi
46502851ab add annotation code to m5
configs/common/Benchmarks.py:
    add annotate test app
src/SConscript:
    add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
    add annotate instructions
src/base/traceflags.py:
    Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
    add anotate ops

--HG--
extra : convert_revision : 7f965c0d84e41ce34f2ec8ec27a009276d67d8d6
2006-09-11 17:57:20 -04:00
Steve Reinhardt
9e6d12b095 Added cscope-find.py utility to generate file list for cscope.
--HG--
extra : convert_revision : 80f2db90f1c2406039d0447b84aa0442b7b974f8
2006-09-08 19:22:25 -04:00
Steve Reinhardt
f6f3ce1311 regress:
Clean up help output.

util/regress:
    Clean up help output.

--HG--
extra : convert_revision : 8375d58a9d72e1871a15690991dc8fc60d47a2b3
2006-09-02 08:20:54 -07:00
Steve Reinhardt
d8501ec17c Get rid of extra stuff in util/regress only needed by cron job,
to make it more usable by regular folks.

util/regress:
    Get rid of extra stuff only needed by cron job,
    to make it more usable by regular folks.

--HG--
extra : convert_revision : e113c05af5eec846db526d734cce8ff66aa95d72
2006-09-01 20:11:50 -04:00