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Author SHA1 Message Date
Brad Beckmann
877be2009c ruby: Changes necessary to get the hammer protocol to work in GEM5 2009-11-18 16:34:32 -08:00
Brad Beckmann
b0973035b4 ruby: added the original hammer protocols from old ruby 2009-11-18 16:34:31 -08:00
Brad Beckmann
2783a7b9ad ruby: returns the number of LLC needed for broadcast 
Added feature to CacheMemory to return the number of last level caches.
This count is need for broadcast protocols such as MOESI_hammer.
 2009-11-18 16:34:31 -08:00
Brad Beckmann
7b8fcecf11 ruby: cache configuration fix to use bytes 
Changed cache size to be in bytes instead of kb so that testers can use very
small caches and increase the chance of writeback races.
 2009-11-18 16:34:31 -08:00
Brad Beckmann
99338a7460 ruby: fix CacheMemory destructor 2009-11-18 16:33:35 -08:00
Brad Beckmann
7ab484624f ruby: split CacheMemory.hh into a .hh and a .cc 2009-11-18 16:33:35 -08:00
Brad Beckmann
8b0f970084 ruby: Added default names to message buffers 
Added default names to message buffers created by the simple network.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
ed54ecf1c8 ruby: slicc method error fix 
Added error message when a method call is not supported by an object.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
994169327a ruby: slicc action error fix 
Small fix to the State Machine error message when duplicate actions are defined.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
cc2db929cb ruby: slicc state machine error fixes 
Added error messages when:
- a state does not exist in a machine's list of known states.
- an event does not exist in a machine
- the actions of a certain machine have not been declared
 2009-11-18 13:55:58 -08:00
Brad Beckmann
e84881b7a3 ruby: Removed unused action z_stall 2009-11-18 13:55:58 -08:00
Brad Beckmann
70a261c0ae m5: Added option to take a checkpoint at the end of simulation 2009-11-18 13:55:58 -08:00
Brad Beckmann
b5d2052fa0 m5: Fixed bug in atomic cpu destructor 2009-11-18 13:55:58 -08:00
Brad Beckmann
faf1d97f24 ruby: fixed dma mi example to work with multiple dma ports 2009-11-18 13:55:58 -08:00
Brad Beckmann
f54790977b m5: removed master and slave deletions. 
The unresolved destructor call caused a seg fault when called.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
4d731a522d m5: fixed destructor to deschedule the tickEvent and event 2009-11-18 13:55:58 -08:00
Brad Beckmann
93f0069dd5 ruby: getPort function fix 
Fixed RubyMemory::getPort function to not pass in a -1 for the idx parameter
 2009-11-18 13:55:58 -08:00
Brad Beckmann
204d1776ca ruby: Fixed Directory memory destructor 2009-11-18 13:55:58 -08:00
Brad Beckmann
b8c413e993 m5: Moved profile option since Simulation depends on it. 2009-11-18 13:55:58 -08:00
Brad Beckmann
6e1dc2546c m5: Added isValidSrc and isValidDest calls to packet.hh 2009-11-18 13:55:58 -08:00
Brad Beckmann
90d6e2652f ruby: included ruby config parameter ports per core 
Slightly improved the major hack need to correctly assign the number of ports
per core.  CPUs have two ports: icache + dcache.  MemTester has one port.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
dce53610c3 ruby: Added error check for openning the ruby config file 2009-11-18 13:55:58 -08:00
Brad Beckmann
3cf24f9716 ruby: Support for merging ALPHA_FS and ruby 
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers.  Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
d7a4f665ed ruby: Added more info to bridge error message 2009-11-18 13:55:57 -08:00
Brad Beckmann
17e14efa7e ruby: Ruby 64-bit address output fixes. 2009-11-18 13:55:57 -08:00
Brad Beckmann
b7cc66af31 ruby: Ruby destruction fix. 2009-11-18 13:55:57 -08:00
Brad Beckmann
5492f71755 ruby: Ruby debug print fixes. 2009-11-18 13:55:57 -08:00
Brad Beckmann
c3204421d8 ruby: Ruby memtest python script. 2009-11-18 13:55:57 -08:00
Derek Hower
b3b8e309ed Added tag Calvin_Submission for changeset 5de565c4b7bd 2009-11-18 11:55:42 -06:00
Derek Hower
9ef5e72917 ruby: added sequencer stats to track what requests are waiting on 2009-11-18 11:55:30 -06:00
Derek Hower
d11dd6ed2c ruby: turned off randomization by default, turned on memory controller random arbitrate 2009-11-18 11:53:43 -06:00
Ali Saidi
422f0d9f10 ARM: Begin implementing CP15 2009-11-17 18:02:09 -06:00
Ali Saidi
0916c376a9 ARM: Differentiate between LDM exception return and LDM user regs. 2009-11-17 18:02:08 -06:00
Ali Saidi
1470dae8e9 ARM: Boilerplate full-system code. 
--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
 2009-11-17 18:02:08 -06:00
Ali Saidi
171e7f7b24 imported patch isa_fixes2.diff 2009-11-16 11:37:03 -06:00
Gabe Black
9127ee5ac8 ARM: Make the exception return form of ldm restore CPSR. 2009-11-15 00:23:14 -08:00
Gabe Black
903fb8c73d ARM: Create a new type of load uop that restores spsr into cpsr. 2009-11-15 00:15:42 -08:00
Gabe Black
b41725f723 ARM: Check in the actual change from the last commit. 
The last commit was somehow empty. This was what was supposed to go in it.
 2009-11-14 21:03:10 -08:00
Gabe Black
5ca47da599 ARM: Switch the immediate and register versions of msr. 
These were accidently transposed. This change straightens them out.
 2009-11-14 20:57:59 -08:00
Gabe Black
c4042985d7 ARM: Fix up the implmentation of the msr instruction. 2009-11-14 19:22:30 -08:00
Gabe Black
e2ab64543b ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits. 2009-11-14 19:22:30 -08:00
Gabe Black
425ebf6bd7 ARM: Add a bitfield to indicate if an immediate should be used. 2009-11-14 19:22:30 -08:00
Gabe Black
e543f16247 ARM: Write some functions to write to the CPSR and SPSR for instructions. 2009-11-14 19:22:30 -08:00
Gabe Black
812e390693 ARM: Fix up the implmentation of the mrs instruction. 2009-11-14 19:22:29 -08:00
Gabe Black
1df0025e28 ARM: More accurately describe the effects of using the control operands. 2009-11-14 19:22:29 -08:00
Gabe Black
50b9149c75 ARM: Hook up the moded versions of the SPSR. 
These registers can be accessed directly, or through MISCREG_SPSR which will
act as whichever SPSR is appropriate for the current mode.
 2009-11-14 19:22:29 -08:00
Ali Saidi
4e9ce1805e SE: Fix SE mode OS X compilation. 2009-11-14 11:49:01 -06:00
Ali Saidi
48bc573f5f ARM: Move around decoder to properly decode CP15 2009-11-14 11:25:00 -06:00
Derek Hower
2f5839832e ruby: added -A option to TwoLevel_SplitL1UnifiedL2 to set the L1 cache size 2009-11-13 09:45:23 -06:00
Derek Hower
f7f475a6f4 ruby: gave ALIASED_REQUEST priority over BUFFER_FULL in sequencer 2009-11-13 09:44:51 -06:00