src/SConscript:
src/arch/sparc/SConscript:
commit a couple of things that I forgot to last time.
--HG--
extra : convert_revision : f140912905b9d36eccc27e35ebcaf2c15611b56b
so the events can be migrated on cpu switches.
Create a new wrapper classe called CpuEventWrapper that works like the old wrapper class but calls the function with the xc
parameter
Use new CpuEventWrapper class from tick compare events on sparc
src/arch/sparc/regfile.hh:
Use new CpuEventWrapper class from tick compare events
src/arch/sparc/ua2005.cc:
Move definition to to a fullsystem only file, since it is.
src/cpu/base.cc:
On switch from one cpu to another CpuEvent::replaceExecContext() needs to be called on all (oldxc,newxc) pairs.
--HG--
extra : convert_revision : eecf4540427cc0ddf75e19a3371cf32b56cba0f5
setup all initialization stuff for UA2005
Setup fullsys build options
Start to make fullsystem compile
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
RCS to BitKeeper
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add support for doing virtual to physical translation using the in-memory
page table
src/arch/sparc/vtophys.cc:
a tad bit of error checking
src/arch/sparc/vtophys.hh:
Cleanup of full-system global variables, primarily in simple_cpu.cc,
to allow multi-system simulations. (Multiple systems not yet yested
though.) Also changes to build sim_smt in full-system mode (though
with only SimpleCPU and not the full timing CPU for now).
Still to do: minimize changes in SimpleCPU code between full-system
and application modes... way too many ifdefs there. Much of the
full-system stuff moved into SimpleCPU should be put in a new System
object to allow multiprocessor simulations.
Converted last remaining modules from C to C++ (mostly in /old).
Renamed all .c files to .cc and a few .h files to .hh.
Renamed architecture-specific files in arch/$TARGET from
$TARGET.{cc,hh,def} to machine.{cc,hh,def} to get rid of pointless
intermediate files in object directory. Split exo-specific
definitions out of machine.hh into machine_exo.h.
Specifics:
In machine.def, null resource descriptors must be FUClamd_NA (and not
NA) to pass C++ type checking.
Enhanced error checking/reporting in bas
src/arch/sparc/vtophys.cc:
- Get rid of my String class, the Vector class, the bitvector class, and my
doubly linked list class.
- Convert tokenize, to_number (formerly StringToNumber) and eat_white to
function on stl strings.
- Change most cases of char * and const char * to string, or const string &
- Some formatting and style nits, but not too many.
src/arch/sparc/vtophys.cc:
simplify
src/arch/sparc/vtophys.cc:
Renamed SimpleCPU::(read|write)_(byte|half|word|qword) to just read &
write, overloaded on the type of the 'data' argument. Merged the
full-system and non-full-system implementations of these eight
original functions into two common template functions.
To support this, also renamed (read|write)[1248] on memory_object and
derivatives to just read & write, again overloaded on the type of the
'data' argument. Many of these functions could now be condensed into
a few template functions (though with a level of indirection so that
the interface can remain virtual). I did not do that though.
src/arch/sparc/vtophys.cc:
First pass at compiling with gcc 3.x. Lots of "std::" in header files,
"using namespace std" in source files. (Note policy of not putting "using"
statements in headers or before includes in sources.)
Still not able to compile with gcc 3.2.
Errors:
- Can't create an ifstream from a file descriptor anymore (breaks IniFile).
- "`class MSHR::MSHRegister' is private" errors in mshr.cc and prefetch_cache.cc:
not clear why since it's in the public part of the class declaration.
- cpu.cc:879: can't match a reference and 0 (specifically "no match for `bool ?
SimObjectParam<PipeTrace*>& : int' operator")
- pipetrace.cc: "invalid conversion from `int' to `std::_Ios_Fmtflags'"
Warnings:
- strstream now deprecated... needs some rewriting in sat_counter.hh
and hybrid_pred.hh (need to get all that code out of the headers anyway)
- trace.hh macro problem: cpp now says 'pasting "::" and "Event" does not
give a valid preprocessing token'
- major "implicit typename" issues in base/sized.hh
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Implement some interval statistics for full system mode.
Create a callpal function that is called when a callpal occurs so it's easier
to manipulate the statics.
Rework the vtophys stuff to make it a bit cleaner.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Get rid of almost all old-style object names. This commit is equivalent
to running the following script on the current head:
#! /bin/sh
find \( -name '*.cc' -o -name '*.hh' \) -exec perl -pi -e '\
s/\bmemory_object\b(?!\.hh)/FunctionalMemory/g;\
s/\bvirtual_memory\b(?!\.hh)/VirtualMemory/g;\
s/\bmain_memory\b(?!\.hh)/MainMemory/g;\
s/\bphysical_memory\b(?!\.hh)/PhysicalMemory/g;\
s/\bspec_memory\b(?!\.hh)/SpeculativeMemory/g;\
s/\bMemObj\b(?!\.hh)/TimingMemObj/g;\
s/\bmemory_translation\b(?!\.hh)/AddressTranslator/g;\
s/\balpha_tlb\b(?!\.hh)/AlphaTlb/g;\
s/\balpha_itb\b(?!\.hh)/AlphaItb/g;\
s/\balpha_dtb\b(?!\.hh)/AlphaDtb/g;\
s/\bmemory_controller\b(?!\.hh)/MemoryController/g;\
s/\bstorebuffer_t\b(?!\.hh)/StoreBuffer/g;\
s/\bstorebuffer_entry_t\b(?!\.hh)/StoreBufferEntry/g;\
s/\bcreate_vector_t\b(?!\.hh)/CreateVector/g;\
s/\bcv_spec_state\b(?!\.hh)/CreateVecSpecState/g;\
s/\bspec_state_list\b(?!\.hh)/SpecStateList/g;\
s/\bdyn_inst_t\b(?!\.hh)/DynInst/g;' {} \;
src/arch/sparc/vtophys.cc:
since cprintf properly deals with 64-bit types, stop using FMT* as much as
possible
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Change byte_t etc. to C99 standard int8_t etc.
Other than old/host.h, all other changes were produced by this script:
#! /bin/sh
find \( -name '*.cc' -o -name '*.hh' -o -name '*.c' -o -name '*.h' -o -name 'machine.def' \) -exec perl -pi -e '\
s/\bbyte_t\b(?!\.hh)/uint8_t/g;\
s/\bsbyte_t\b(?!\.hh)/int8_t/g;\
s/\bhalf_t\b(?!\.hh)/uint16_t/g;\
s/\bshalf_t\b(?!\.hh)/int16_t/g;\
s/\bword_t\b(?!\.hh)/uint32_t/g;\
s/\bsword_t\b(?!\.hh)/int32_t/g;\
s/\bqword_t\b(?!\.hh)/uint64_t/g;\
s/\bsqword_t\b(?!\.hh)/int64_t/g;\
s/\bbool_t\b(?!\.hh)/bool/g;\
s/\bdfloat_t\b(?!\.hh)/double/g;\
s/\bsfloat_t\b(?!\.hh)/float/g;' {} \;
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add CVS Id tags
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Massive renaming to (almost) eliminate all md_* and MD_* names
in preparation for total exorcism of machine.def.
Most of the changes in this commit were performed with the
following perl script (perl -pi <script> <files>). A small
amount of manual fixup was needed to (mostly getting rid of
the Addr typedefs in the various memory objects now that
the former md_addr_t has that name).
# rename machine-dependent types and constants (will be moving into ISA traits object)
s/md_addr_t/Addr/g;
s/md_intreg_t/IntReg/g;
s/md_gpr_t/IntRegFile/g;
s/md_fpreg_t/FloatReg/g;
s/md_fpr_t/FloatRegFile/g;
s/md_ctrlreg_t/MiscReg/g;
s/md_ctrl_t/MiscRegFile/g;
s/md_ipr_t/InternalProcReg/g;
s/md_anyreg_t/AnyReg/g;
s/md_inst_t/MachInst/g;
s/regs_t/RegFile/g;
# manually fix declaration in old/regs.h and a few forward decls
s/struct RegFile/RegFile/g;
s/MD_NUM_IREGS/NumIntRegs/g;
s/MD_NUM_FREGS/NumFloatRegs/g;
s/MD_NUM_CREGS/NumMiscRegs/g;
s/MD_IPR_NUM/NumInternalProcRegs/g;
s/MD_TOTAL_REGS/TotalNumRegs/g;
s/MD_REG_ZERO/ZeroReg/g;
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
New ISA description system. No more machine.def!
Instructions are now decoded into StaticInst objects, and all static
instruction properties (including execution behavior) are associated
with those objects. Extended documentation in progress.
Currently supports Alpha only; PISA will not compile.
Use END_OF_MACHINE_DOT_DEF tag to extract previous version.
src/arch/sparc/vtophys.cc:
get rid of MD_IPR_foo and call it IPR_foo
add some comments to describe what the various PALtemp registers do
formatting
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
license
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
a little style
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add attribution to license.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Make include paths explicit.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
CopyData and CopyString moved from kernel.cc to vtophys.cc
kernel.cc and kernel.hh moved to kern/tru64
src/arch/sparc/vtophys.hh:
Include isa_traits.hh for Addr
src/arch/sparc/vtophys.cc:
formatting fixes
src/arch/sparc/vtophys.cc:
fix up vtophys to deal with translations if there
is no ptbr, and to deal with PAL addresses
add ptomem which is just a wrapper for dma_addr
src/arch/sparc/vtophys.hh:
add ptomem which is a wrapper for dma_addr with the
same usage as vtomem
src/arch/sparc/vtophys.cc:
Fix to remote debugger while in PAL code
src/arch/sparc/vtophys.cc:
Remote an old hack that is now unnecessary
src/arch/sparc/vtophys.cc:
Removed buggy code that tries to fix PAL addresses (may cause problems
while trying to debug in PAL code, but that should do this fix outside
of vtophys)
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Updated Copyright
src/arch/sparc/vtophys.cc:
added back some code andrew removed and couldn't remember why.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
rename CopyData to CopyOut and implement CopyIn to copy data
from the simulator into the simulatee
src/arch/sparc/vtophys.cc:
fixed a bad merge from linux<->tru64
src/arch/sparc/vtophys.cc:
Check max address pal can be at so we don't do the wrong conversion
if gdb asks for an unaligned access.
src/arch/sparc/vtophys.cc:
PGOFSET -> ALPHA_PGOFSET to avoid include file problems
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
in the arch/alpha directory we should use arch/alpha, not
targetarch. sort includes while we're here.
src/arch/sparc/vtophys.cc:
use new constants, functions and structs to clean up the
vtophys code.
src/arch/sparc/vtophys.hh:
Clean up a little bit and make the protypes match new changes.
src/arch/sparc/vtophys.cc:
deal with isa addition
src/arch/sparc/vtophys.cc:
shuffle files around for new directory structure
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Remove RCS Id string
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Update copyright dates and author list
src/arch/sparc/vtophys.cc:
Added a using directive for AlphaISA
src/arch/sparc/vtophys.hh:
Added the AlphaISA namespace specifier where needed
src/arch/sparc/vtophys.hh:
Made Addr a global type
src/arch/sparc/vtophys.cc:
Change access to the IPR to go through the XC.
src/arch/sparc/vtophys.cc:
Avoid directly accessing objects within the XC.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
fixed for new memory system
put in namespace AlphaISA
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
Remove authors from copyright.
src/arch/sparc/vtophys.cc:
bk cp alpha/vtophys.cc sparc/vtophys.cc
src/arch/sparc/vtophys.hh:
bk cp alpha/vtophys.hh sparc/vtophys.hh
src/arch/sparc/SConscript:
remove fullsystem files that don't exist
src/arch/sparc/isa_traits.hh:
split off fullsystem and se iprs into two functions to remove lots of #ifs
src/arch/sparc/regfile.hh:
split off fullsystem and se iprs into two functions to remove lots of #ifs
setup all initialization stuff for UA2005
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
Add system level tick storage to make stick be syncronized across multiple processors
src/arch/sparc/vtophys.hh:
start to create a vtophys for Sparc
src/base/loader/symtab.hh:
Addr is defined in sim/host.hh
--HG--
extra : convert_revision : ae4658e6bc2e2b51d7fb1c711d069ffe99e1377d
Rip out storage in miscreg file that will never store anything
Add storage and defines for Priv and Hyperpriv registers
Change defines to match the spec register numbers
Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.
Use bitfields for things that are rarely used in decoder
Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead
Still todo:
Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs
Deal with signaling interrupts on timer expiration
Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU
Other misc:
Instruction decoding needs major help!
src/arch/sparc/isa/decoder.isa:
Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely
changed to bitfields.
src/arch/sparc/isa/formats/integerop.isa:
These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set
at once
src/arch/sparc/isa/formats/priv.isa:
PrivTick is handled by miscreg now, don't need a seperate class for it
src/arch/sparc/isa/operands.isa:
prune the number of control regs down to a reasonable amount
src/arch/sparc/isa_traits.hh:
Replace 8 defines with 1 and flick some bits
src/arch/sparc/process.cc:
Better to clean the entire registers that specific bits which leads to indetermanistic behavior.
src/arch/sparc/regfile.hh:
Rip out storage that will never be backed by anything
Add storage for Priv and Hyperpriv registers
change defines to match the spec
change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.
--HG--
extra : convert_revision : 64276a3ea884eea70112e721f85a515946ded4c2
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
Move traceData->finalize() into postExecute().
src/cpu/simple/timing.cc:
Fixes for full system. Now boots Alpha Linux!
- Handle ifetch faults, suspend/resume.
- Delete memory request & packet objects on response.
- Don't try to do split memory accesses on prefetch references
(ISA description doesn't support this).
src/cpu/simple/timing.hh:
Minor reorganization of internal methods.
--HG--
extra : convert_revision : 59e3ee5e4cb53c424ebdbe2e504d97e88c08a978
Store original source & senderState for timing packets
that get a response, so we can properly route the
response packet back to the original sender.
--HG--
extra : convert_revision : 03dbcc8dc06d93de243bfcdc3cbaa012773c6782
src/base/traceflags.py:
Sort flags so you can find things.
Add BusAddrRanges flag for tracking RangeChange events
separately from general bus activity.
src/mem/bus.cc:
Add BusAddrRanges flag for tracking RangeChange events
separately from general bus activity.
src/mem/port.cc:
src/mem/port.hh:
Print Config trace message when peers are set up.
--HG--
extra : convert_revision : d7c11d5f90c8de5c8d97e473501a268a567e9e44
- new constructor guarantees initialization of most fields
- flags track status of non-guaranteed fields (addr, size, src)
- accessor functions (getAddr() etc.) check status on access
- Command & Result classes are nested in Packet class scope
- Command now built from vector of behavior bits
- string version of Command for tracing
- reinitFromRequest() and makeTimingResponse() encapsulate
common manipulations of existing packets
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/timing.cc:
src/dev/alpha_console.cc:
src/dev/ide_ctrl.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/isa_fake.cc:
src/dev/ns_gige.cc:
src/dev/pciconfigall.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/dev/tsunami_io.cc:
src/dev/tsunami_pchip.cc:
src/dev/uart8250.cc:
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/physical.cc:
src/mem/port.cc:
src/mem/port.hh:
src/mem/request.hh:
Update for new Packet interface.
--HG--
extra : convert_revision : 9973d09ea4fa61795f23772a7d3995fa4df5c269
cpu/o3/2bit_local_pred.cc:
Branch predictor cleanup/fixup. Rename this to LocalBP.
cpu/o3/2bit_local_pred.hh:
Rename to LocalBP, update to support changes to BPredUnit, include comments.
cpu/o3/alpha_cpu_builder.cc:
Support extra parameters to the branch predictor. Now it takes in a parameter to tell it which branch predictor it is using, the local or the tournament predictor.
cpu/o3/alpha_params.hh:
Add in extra parameter for the branch predictor type.
cpu/o3/bpred_unit.cc:
Branch predictor fixup/cleanup. Rename it to BPredUnit.
cpu/o3/bpred_unit.hh:
Branch predictor fixup/cleanup. Now supports both the local and tournament predictors, and stores the branch predictor update state.
cpu/o3/bpred_unit_impl.hh:
Branch predictor overhaul. Now supports both the local and tournament predictors.
cpu/o3/cpu_policy.hh:
cpu/ozone/ozone_impl.hh:
cpu/ozone/simple_impl.hh:
Reflect the class name change.
cpu/o3/decode_impl.hh:
Be sure to set the predicted target as well so we don't squash twice.
cpu/o3/tournament_pred.cc:
cpu/o3/tournament_pred.hh:
Fixes to the tournament predictor.
cpu/ozone/simple_params.hh:
Include parameter for the branch predictor type.
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/OzoneCPU.py:
Include the parameter for the branch predictor type.
--HG--
extra : convert_revision : 34afebb3b40b47accb12558e439ee4cb03df5e64
arch/alpha/ev5.cc:
Fix up some stuff I missed in the last kernel stats checkin.
cpu/checker/cpu.cc:
Allow the checker to disable its kernel stats.
cpu/cpu_exec_context.cc:
Allow CPUExecContext to be created without kernelStats.
cpu/cpu_exec_context.hh:
Allow CPUExecContext to be created without kernelStats. Default usage leaves kernelStats on.
--HG--
extra : convert_revision : 8ed5bffd3a5b6275baa07fb4ea385eeab1a0456a
cpu/ozone/front_end_impl.hh:
cpu/ozone/lw_back_end_impl.hh:
cpu/ozone/lw_lsq_impl.hh:
Support new flags added in.
--HG--
extra : convert_revision : 2e756fd1913cf600650afc39dd715d59b9b89c42
arch/alpha/isa/main.isa:
Use automatic path includes thanks to updates to isa parser.
arch/isa_parser.py:
Pull changes to isa parser from newmem into m5. This fixes a bug where the files include in main.isa were not being included as dependencies properly.
--HG--
extra : convert_revision : 8ef1e2e1a64e7a5762baf7a09abc8665d7c2f688
Need to rewrite bus bridge to get any further.
src/dev/io_device.cc:
Set packet dest on timing responses.
src/mem/bus.cc:
Fix dest addr bounds check assertion.
Add assertion to catch infinite loopbacks.
src/mem/physical.cc:
Add comment.
--HG--
extra : convert_revision : 419b65a3a61e2d099884dbda117b338dffd80896
The "execute" portion of IEW is really just the last cycle of execution, at which point execute() gets called. Execution begins inside the IQ, when it schedules FUs for specific instructions. As a result, the Execute stage should just pull all completing instructions out of the IQ stage and execute them.
Limiting the number of writebacks outstanding must still be done.
cpu/o3/iew_impl.hh:
Rework how instructions are scheduled and executed. There shouldn't be a specific "width" from issue to execute because issue does the scheduling of the functional units (really the beginning of the execution).
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
Rework how instructions are scheduled and executed.
--HG--
extra : convert_revision : bbf1a8a4c0a2f2a938bdd78d74493048fd3b4b55
cpu/checker/cpu.cc:
Cleanup checker, give more useful warning messages.
Also fix bug
cpu/checker/cpu.hh:
Cleanup checker, use forward declaration instead of include.
--HG--
extra : convert_revision : 8f231199a0a75788218320cdbcc7f70441e5d574
arch/alpha/ev5.cc:
Move kernel stats out of CPU and into XC. Also be sure to check if the kernel stats exist prior to using them.
--HG--
extra : convert_revision : 565cd7026410fd7d8586f953d9b328c2e67a9473
IsIprAccess flag may go away in the future (op class can be used to tell this), and the CPU still needs a specific way to identify/deal with syscalls.
arch/alpha/isa/decoder.isa:
Added a few extra flags to help the new CPU identify various classes of instructions without having to force certain behaviors for all CPUs.
cpu/base_dyn_inst.hh:
cpu/static_inst.hh:
Added extra flags.
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue_impl.hh:
Handle store conditionals specially.
cpu/o3/lsq_unit_impl.hh:
Extra flags tells if the instruction is a store conditional.
cpu/o3/rename_impl.hh:
Handle IPR accesses and store conditionals specially.
--HG--
extra : convert_revision : 39debec4fa5341ae8a8ab5650bd12730aeb6c04f
Undo changes to allow multiple build roots in a single
invocation... this would have been too messy to maintain
with the auto-configure stuff, and probably isn't useful anyway.
--HG--
extra : convert_revision : 32a2d9d7fc980911acc3e7b9430df1ba5a0ee68e
It doesn't compile, and if we really want this we should
start over from scratch and see if we can reuse parts from
BaseSimpleCPU (e.g., derive a FastSimpleCPU).
SConstruct:
src/arch/SConscript:
src/cpu/cpu_models.py:
Get rid of FastCPU model.
--HG--
extra : convert_revision : f3f0362f7292bf21e8e0d4d84c475be8a9789a0c
src/arch/sparc/isa/formats/nop.isa:
Fix nop header so we can compile with multiple CPU models.
(Former code re-defined Nop object for each model.)
--HG--
extra : convert_revision : 04e92622edf4dfefd9e149a17f604e17a93707c9
SConstruct:
Clean up libelf handling. Required better handling of
per-build-root stuff in general (though libelf is the
only thing in that category currently).
src/SConscript:
No libelf-specific stuff in here anymore.
src/base/loader/elf_object.cc:
Just need to include gelf.h... it includes libelf.h.
--HG--
extra : convert_revision : 3d6bdcf8233bda0ac8d08ff777de323df8aa45ae
This temporarily will break the O3 and Ozone CPU models. Updates to fix them will be coming soon.
arch/alpha/isa/decoder.isa:
Undo changes to instruction flags that has caused statistics to change in regressions.
--HG--
extra : convert_revision : c0fa9d55a22cae7c4f02d388870565b205d6fba3
cpu/SConscript:
Remove sat_counter.cc and push its functions into the .hh file (all functions were 3 or less lines).
cpu/o3/sat_counter.hh:
Incorporate .cc code into this file.
--HG--
extra : convert_revision : d75b1319292b00b00af1ce377cc0215fd06e6916
Dependecy graph code moved into its own class.
This requires the changes to the functional units, which is in the next check in.
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
IEW and IQ code cleanup and reorganization.
cpu/o3/inst_queue.cc:
Dependency graph code moved into its own class now.
cpu/o3/inst_queue.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
cpu/o3/inst_queue_impl.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
Issue loop cleaned up, with completion events for functional units now used more correctly (before they weren't used for multi-cycle ops with pipelined FU's).
--HG--
extra : convert_revision : 35e50192df6f71dc81d46a73fdd65f7ec07c10e4
SConscript:
Split off activity/idling code into its own class to do the processing separately.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_params.hh:
Activity stuff. This is mostly for debugging and may be removed later on (or changed to enable/disable activity idling).
cpu/o3/cpu.cc:
Move activity idling stuff mostly into its own class, so it no longer clutters this file.
cpu/o3/cpu.hh:
Move activity idling stuff into its own class.
python/m5/objects/AlphaFullCPU.py:
Add parameter for initial activity value.
--HG--
extra : convert_revision : f32f7cc03895dc07ab57ddba78c5402a1a8b0f1a
TimingSimpleCPU. Not there yet.
cpu/simple/atomic.cc:
Only read SC result if store was an SC.
Don't fake SC here; fake it in PhysicalMemory so
all CPU models can share in the joy.
cpu/simple/timing.cc:
Don't forget to checkForInterrupts().
Only fetch subsequent instruction if we're still running
(i.e. not quiesced).
dev/io_device.hh:
Initialize port pointer in SendEvent object.
mem/physical.cc:
Move fake SC "implementation" here from AtomicSimpleCPU.
mem/request.hh:
Initialize flags to all clear, not uninitialized.
Otherwise we can't reliably look at flags w/o explicitly
setting them every time we create a request.
--HG--
extra : convert_revision : ae7601ce6fb54c54e19848aa5391327f9a6e61a6
