running SPEC FP codes).
arch/alpha/isa_desc:
Don't warn about non-standard trapping modes more than
once per static instruction. (Had the flag to suppress
these but forgot to check it!)
build/SConstruct:
Add USE_SSE2 option to enable compiling w/SSE2 (important
for getting IEEE-compliant FP on x86).
--HG--
extra : convert_revision : eac69efb28cce7b48035480d8b7cb004782969f4
SConscript:
Get rid of the pc_sample stuff and move to the new profiling stuff
base/traceflags.py:
DPRINTF Stack stuff
cpu/base.cc:
cpu/base.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
Add profiling stuff
kern/kernel_stats.hh:
Use a smart pointer
sim/system.cc:
sim/system.hh:
Create a new symbol table that has all of the symbols for a
particular system
util/stats/categories.py:
change around the categories, add categories for function
profiling stuff
util/stats/profile.py:
No profile parsing and display code to deal with function
profiling stuff, graph, dot, and text outputs.
--HG--
extra : convert_revision : b3de0cdc8bd468e42647966e2640ae009bda9eb8
Seems to avoid the significant problems on platforms w/o fenv.h.
arch/alpha/isa_desc:
Explicitly handle rounding on FP-to-integer conversions.
Seems to avoid the significant problems on platforms w/o fenv.h.
Get rid of FP "Fast" vs "General" distinction... more headache than
it's worth.
arch/isa_parser.py:
Fix bug with "%s" in C++ templates (must escape properly to
pass through Python string interpolation).
--HG--
extra : convert_revision : de964d764e67e0934ac0ef535f53c974640731fb
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line. Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.
SConscript:
MySQL detection moved to SConstruct.
Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
Revamp fenv.h support... most of the ugliness is hidden
in base/fenv.hh now.
base/mysql.hh:
Fix typo in #ifndef guard.
build/SConstruct:
Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.
python/SConscript:
Generate m5_build_env directly from scons options
instead of indirectly via CPPDEFINES.
python/m5/convert.py:
Allow '0' and '1' for booleans.
Rewrite toBool to use dict.
base/fenv.hh:
Revamp <fenv.h> support to make it a compile option
(so we can test w/o it even if it's present) and to
make isa_desc cleaner.
--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
code into a function that can be called by the AlphaConsole class.
AlphaConsole will pass in its address.
arch/alpha/ev5.hh:
Move Phys2K0Seg to ev5.hh and fixup the TSUNAMI uncacheable
bits so that they will be converted correctly.
dev/alpha_access.h:
Do not hard code the location of the AlphaConsole
dev/alpha_console.cc:
fixup #includes
tell the system where the alpha console is
sim/system.hh:
Provide a function that will tell the system where the AlphaAccess
structure (device) lives
--HG--
extra : convert_revision : 92d70ca926151a32eebe9925de597459ac58013e
SConscript:
Added kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
Added Argument to support replacement of calibrate_clocks function in FreeBSD.
dev/ns_gige.hh:
Fixed NIC model number typo.
dev/tsunami_io.cc:
Added support for RTC writes and PIC 2 mask reads. Made RTC static member.
dev/tsunami_io.hh:
Made RTC static member.
kern/freebsd/freebsd_system.cc:
Added events to skip functions in FreeBSD.
kern/freebsd/freebsd_system.hh:
Added events to skip certain functions.
--HG--
extra : convert_revision : 8aaca51d3f9b1bb601722a5bae240aae77b445db
kern/linux/sched.hh:
kern/linux/thread_info.hh:
got rid of everything but exactly what we needed
util/categories.py:
newest version from one of my repositories
--HG--
extra : convert_revision : c4328e5938d421d60493c0da07022bfa9e92c404
arch/alpha/alpha_tru64_process.cc:
Sort #includes
Make code more portable. g++ doesn't seem to always like
struct ::stat (and others). So, we typedef stat outside of
the namespace as something else and use the typedef
base/hostinfo.cc:
use snprintf to quell warning
base/inifile.cc:
use strncpy to quell warning
base/stats/events.cc:
don't use strcpy
cpu/beta_cpu/btb.cc:
use FloorLog2 instead of log2
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/inst_queue.hh:
cpu/beta_cpu/sat_counter.hh:
use sim/host.hh instead of stdint.h
--HG--
extra : convert_revision : 59bd9235dda74e72a8b6a70b3f3a981840384f3f
We can now run the SimpleScalar wupwise binary
to completion on the test input.
Didn't have time to do more testing, but I fixed
a major problem w/getdirentries that should help
a lot more programs run.
arch/alpha/alpha_tru64_process.cc:
Add truncate, ftruncate, statfs, and fstatfs.
Add v4.x (pre-F64) stat, fstat, and lstat.
Add setsysinfo (though all it does is provide more
specific warning messages).
Fix subtle but major bug in getdirentries.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Add truncate, ftruncate, statfs, and fstatfs.
--HG--
extra : convert_revision : 9037393d00dc49b0074a41603ea647587f5a9ec7
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
Remove OOO CPU stuff.
arch/alpha/faults.hh:
Add fake memory fault. This will be removed eventually.
arch/alpha/isa_desc:
Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
Remove asid.
cpu/beta_cpu/comm.hh:
Remove global history field.
cpu/beta_cpu/commit.hh:
Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
Add debug function.
cpu/beta_cpu/decode_impl.hh:
Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
Extra forward declares added due to compile error.
--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
arch/alpha/alpha_tru64_process.cc:
getdirent isn't implemented by cygwin. panic if this function is
executed. (It shouldn't be too much to emulate it using opendir,
readdir, etc.)
arch/alpha/pseudo_inst.cc:
Use lseek once and read instead pread.
base/intmath.hh:
we want int, long, and long long variations of FloorLog2 instead
of int32_t, int64_t. Otherwise, we leave one out.
base/socket.cc:
Fix define that seems to be for apple
sim/serialize.cc:
don't use the intXX_t stuff, instead, use the real types
so we're sure that we cover all of them.
--HG--
extra : convert_revision : 9fccaff583100b06bbaafd95a162c4e19beed59e
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
millisecond, microsecond, etc. so that the user can explicitly
convert between system ticks and time and know what sorts of
expensive operations are being used for that conversion.
arch/alpha/alpha_tru64_process.cc:
arch/alpha/pseudo_inst.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ns_gige.cc:
dev/sinic.cc:
dev/tsunami_io.cc:
dev/uart.cc:
sim/stat_control.cc:
sim/syscall_emul.hh:
Use the new variables for getting the event clock
dev/etherdump.hh:
delete variables that are no longer needed.
--HG--
extra : convert_revision : d95fc7d44909443e1b7952a24ef822ef051c7cf2
arch/alpha/alpha_tru64_process.cc:
sim/process.cc:
sim/process.hh:
Add an address range for the nxm
sim/syscall_emul.hh:
Check to make sure that if we have an nxm config space that the mmap hasn't grown into it
--HG--
extra : convert_revision : e479e5240080ae488080d228bafea488835d6e77
arch/alpha/alpha_tru64_process.cc:
g++ 3.4 fixes. Must cast to an int prior to returning value.
--HG--
extra : convert_revision : d8ccfd7aa7ca00d9bc2d76cff014b9f142d10640
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
cpu/exec_context.hh:
sim/process.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Changed all syscalls to use syscall return object
arch/alpha/isa_traits.hh:
Added syscall return object that packages return value and return
status into an object.
sim/process.cc:
renamed variable name to nm so base class function name() can be called
--HG--
extra : convert_revision : 6609c5ffecc9e3519d7a0cd160879fd21d54abfc
cpu/static_inst.hh:
Hand-merge. These execute functions are within an external file in the new CPU case.
--HG--
extra : convert_revision : a34112f471fa31bdd5bb53552ddd704b9571c110
1) Add fault_handler_delay param to FullCPU to wait N cycles after
committing faulting instruction before fetching fault handler.
2) Make hw_rei a serializing instruction (flushes pipe, basically).
arch/alpha/isa_desc:
Make hw_rei a serializing instruction (guarantees previous insts
complete before hw_rei will issue).
--HG--
extra : convert_revision : 704cef65b3869be9eee724055cedb22114a78359
instructions use it (instead of IntALU, as before). Default config
has a single non-pipelined 3-cycle unit. A bit conservative for the
ev6 (some are 1, some are 3).
arch/alpha/isa_desc:
Make hw_mfpr and hw_mtpr use IprAccessOp op class.
cpu/full_cpu/op_class.hh:
Add IprAccess.
--HG--
extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442
particular binary machine instruction and should be immutable after
they are constructed.
cpu/simple_cpu/simple_cpu.hh:
Make StaticInst parameters const.
--HG--
extra : convert_revision : e535fa10c842ce173336323f39d9108c1847f8ba
SConscript:
Include new files.
arch/alpha/isa_desc:
Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Fixes for gcc-3.4.
Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
Use new params pointer in BaseCPU.
Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
Remove unused global variable.
cpu/static_inst.hh:
Include OoODynInst for new lightweight OoO CPU
--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
a faulting instruction is the fault handler, which appears as an independent
instruction to the timing model. New code will stall fetch and not fetch the
fault handler as long as there's a faulting instruction in the pipeline (i.e.,
the faulting inst has to commit first).
Also fix Ali's bad-address assertion that doesn't apply to full system.
Added some more debugging support in the process. Hopefully we'll move to the new
cpu model soon and we won't need it anymore.
arch/alpha/alpha_memory.cc:
Reorganize lookup() so we can trace the result of the lookup as well.
arch/alpha/isa_traits.hh:
Add NoopMachInst (so we can insert them in the pipeline on ifetch faults).
base/traceflags.py:
Replace "Dispatch" flag with "Pipeline" (since I added similar
DPRINTFs in other pipe stages).
cpu/exetrace.cc:
Change default for printing mis-speculated instructions to true (since
that's often what we want, and right now you can't change it from the
command line...).
--HG--
extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc
add dprintf on alignment faults
fix RR benchmark rcS script name
Add Dual test without rcS script
Update Monet to be closer to the real thing
Fix p4/monet configs
Add a way to read the DRIR register with at 32bit access for validation
SConscript:
build/SConstruct:
always use mysql if the libraries are installed
arch/alpha/alpha_memory.cc:
Add a DPRINTF to print alignment faults when they happen
dev/tsunami_cchip.cc:
Add a way to read the DRIR for validation.
--HG--
extra : convert_revision : 8c112c958f36b785390c46e70a889a79c6bea015
address calculation and memory access portions separately.
Not currently used by any CPU models, but Kevin says he needs this.
Also clean up handling of execution tracing for memory accesses
(move it all into isa_desc and out of CPU models).
Got rid of some ancient unused code too.
arch/alpha/isa_desc:
Add execute() methods to EAComp and MemAcc portions of memory
access instructions, to allow CPU models to execute the effective
address calculation and memory access portions separately.
Requires the execution context to remember the effective address
across the two invocations. Added setEA() and getEA() methods to
execution context to support this. A model that does not use the
split execution model can panic if these methods are called.
Also added hook to call traceData->setAddr() after EA computation
on any load or store operation.
arch/isa_parser.py:
Call traceData->setData() on memory writes (stores).
cpu/simple_cpu/simple_cpu.cc:
Get rid of unused code.
cpu/simple_cpu/simple_cpu.hh:
Add (non-functional) setEA() and getEA() methods for new
split memory access execution support.
--HG--
extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0
