Commit graph

3025 commits

Author SHA1 Message Date
Ron Dreslinski
890f0fc782 Merge zizzer:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : 27bfbce7c674f0628ef53921329c08f31db6ef44
2006-08-15 16:35:12 -04:00
Ron Dreslinski
47b1c80502 Make test1 capable of running with caches (-C, --caches) for testing.
--HG--
extra : convert_revision : 0b018f9e33b83c346ca0fb1b4e4066fb80c96b8c
2006-08-15 16:24:01 -04:00
Ron Dreslinski
d5ac1cb51f Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches.
-Basically removed the ASID from places it is no longer needed due to PageTable

src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
    Remove asid where it wasn't neccesary anymore due to Page Table

--HG--
extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28
2006-08-15 16:21:46 -04:00
Steve Reinhardt
65d00083ef README:
Fix SWIG version number.

README:
    Fix SWIG version number.

--HG--
extra : convert_revision : 618d6e63d44bc7664dace545d4e35119f52b8407
2006-08-15 15:43:00 -04:00
Ron Dreslinski
d0d0d7b636 Merge zizzer:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : 8a8d7fe59610806015c8242a2f5eacf9afce7164
2006-08-15 14:28:22 -04:00
Ron Dreslinski
dc375e42bc Some changes to support blocking in the caches
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache_impl.hh:
    Outstanding blocking updates for cache

--HG--
extra : convert_revision : 3a7b4aa4921de8239f604f1852f262a2305862c0
2006-08-15 14:24:49 -04:00
Steve Reinhardt
0748851071 Update release files.
README:
    Add brief build instructions for the impatient.
    A few minor fixes.
RELEASE_NOTES:
    Change date; add beta disclaimer.

--HG--
extra : convert_revision : d31af687c657feb36a2694ef9f0abd67390c7023
2006-08-15 08:49:15 -07:00
Gabe Black
74e80fc6c7 Some touchup to the reorganized includes and "using" directives.
--HG--
extra : convert_revision : 956c80d6d826b08e52c0892a480a0a9b74b96b9d
2006-08-15 05:49:52 -04:00
Gabe Black
cd6eb53965 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

src/cpu/static_inst.hh:
    SCCS merged

--HG--
extra : convert_revision : a4f6377dbd691ab58fe5f7958b983b092575f250
2006-08-15 05:08:30 -04:00
Gabe Black
74546aac01 Cleaned up include files and got rid of many using directives in header files.
--HG--
extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
2006-08-15 05:07:15 -04:00
Gabe Black
c9900f159e Fixed ALPHA_FS by moving the remnants of isa_fullsys_traits.hh into arch/alpha/pagetable.hh and fixing up some includes
--HG--
extra : convert_revision : 02a47fa62b17245763314890beb68339c789d18f
2006-08-15 04:46:51 -04:00
Steve Reinhardt
336beeaf43 More cleanup for release.
--HG--
extra : convert_revision : 94b45da5d1a658c4d0f87c73ce72facc9da8d981
2006-08-15 02:08:25 -04:00
Steve Reinhardt
5bd07f98ed Fix up doxygen.
--HG--
rename : docs/footer.html => src/doxygen/footer.html
rename : docs/stl.hh => src/doxygen/stl.hh
extra : convert_revision : 2b2e5637930843c1be07deaa708fd4126213cda2
2006-08-14 19:25:07 -04:00
Steve Reinhardt
a04552ce86 Changes for release.
README:
    s/m5.eecs.umich.edu/www.m5sim.org/
    whack mentions of "CD distribution"
RELEASE_NOTES:
    Set date of 2.0 beta release
    Fix typo

--HG--
extra : convert_revision : 5baa113a98f89dbf56f60adb4513ca22b63673b1
2006-08-14 18:15:53 -04:00
Gabe Black
741bc40cc3 Changed the size parameter from int to int64_t
--HG--
extra : convert_revision : a19404bdc3a6434fe28f8aa278dc6addf764be22
2006-08-14 03:18:38 -04:00
Gabe Black
fc8b4f5253 Started to add support for O3 for sparc.
--HG--
extra : convert_revision : 3f94bda14024a09b9fbd7a5d13284d4987349ddf
2006-08-11 20:29:15 -04:00
Gabe Black
95dc8e4d57 Changed the compiler guards to say SPARC
--HG--
extra : convert_revision : e79964148c7fb7075627f46add6687f6cd0ee241
2006-08-11 20:28:35 -04:00
Gabe Black
fb35d474a5 Added code to support setting up all of the auxillieary vectors configured by the sparc linux elf loader.
src/arch/sparc/process.cc:
    All of the auxilliary vectors are now set like they are in the linux elf loader. This code should probably be moved to arch/sparc/linux/process.cc somehow.

--HG--
extra : convert_revision : 4a90cacf70b1032cad3f18b0f833a6df8237e0de
2006-08-11 20:27:22 -04:00
Gabe Black
1f44717732 #include of iostream needed.
--HG--
extra : convert_revision : d31bb943ab25103cf715159054df318a5b88abc9
2006-08-11 20:23:31 -04:00
Gabe Black
e6842652ba Adjusted the decoder a little.
--HG--
extra : convert_revision : 5bdbe00342837ae4caacb3ad86c7becca36ba6ce
2006-08-11 20:22:36 -04:00
Gabe Black
ec26f0bb3d Started adding a system to output data after every instruction.
src/arch/alpha/regfile.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/cpu/exetrace.hh:
    Added functions to start to support dumping register values once per cycle.
src/cpu/exetrace.cc:
    Added some code to support printing the value of registers after each cycle.
src/python/m5/main.py:
    Options to turn on output after every instruction. They are commented out.

--HG--
extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0
2006-08-11 20:21:35 -04:00
Gabe Black
800e6ecc07 Pushed most of constants.hh back into isa_traits.hh and regfile.hh and created a seperate file for the syscallreturn class.
--HG--
extra : convert_revision : 9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9
2006-08-11 19:43:10 -04:00
Korey Sewell
f612f09669 make test3.py usable again ... I guess I should fix up test4 and test5 too???
Also, What happened to the "lets make real names for these tests" thing we
were talking about? Is test1 - test(n) OK now?

--HG--
extra : convert_revision : 60716e41ecc79a78241be383ab3cae4b9e382335
2006-08-11 18:42:43 -04:00
Korey Sewell
9058175af9 really confused about this license but OK...
--HG--
extra : convert_revision : 85e40593e344b9eff325061630db27d178937258
2006-08-10 20:51:43 -04:00
Kevin Lim
08c0919b43 Clean up some more config stuff.
configs/common/FSConfig.py:
    Clean up some code to make functions look less like classes.  Also put makeList function (formerly listWrapper) into m5 itself.
configs/test/fs.py:
    Update for changed code.
src/python/m5/__init__.py:
    Put makeList into m5.

--HG--
extra : convert_revision : 731806a7486f9abf986f52926126df666b024b1d
2006-07-27 17:49:00 -04:00
Kevin Lim
53e17d0368 Update ref stats.
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/stderr:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/stdout:
    Updated output.

--HG--
extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 17:47:43 -04:00
Kevin Lim
94dd369fcd Output the command line.
src/python/m5/main.py:
    Output the command line being used.

--HG--
extra : convert_revision : 51dadb0ef79ca1e8bbb5a3bd64110071c30ade0d
2006-07-27 17:37:28 -04:00
Kevin Lim
52c3991182 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 70221af596bddbfcc40646d03f175ef5e4b75909
2006-07-27 16:43:29 -04:00
Kevin Lim
64b7213046 Need config read/write latency.
--HG--
extra : convert_revision : 2d978635db89e727f228890738b24fcad9b6ced6
2006-07-27 16:43:02 -04:00
Korey Sewell
95561dc138 MIPS ISA runs 'hello world' in O3CPU ...
src/arch/mips/isa/base.isa:
    special case syscall disasembly... maybe give own instruction class?
src/arch/mips/isa/decoder.isa:
    add 'IsSerializeAfter' flag for syscall
src/cpu/o3/commit.hh:
    Add skidBuffer to commit
src/cpu/o3/commit_impl.hh:
    Use skidbuffer in MIPS ISA
src/cpu/o3/fetch_impl.hh:
    Print name out when there is a fault
src/cpu/o3/mips/cpu_impl.hh:
    change comment

--HG--
extra : convert_revision : d032549e07102bdd50aa09f044fce8de6f0239b5
2006-07-26 18:47:06 -04:00
Gabe Black
36e9ca5611 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 3bb2cdd9b286e7f0235fb5fd5099b89775e05a10
2006-07-26 03:48:48 -04:00
Gabe Black
e803c8a912 Added alot of fp instructions, and some impdep instructions.
--HG--
extra : convert_revision : cc703919b59e674044ae370a65dc03deece6d69e
2006-07-26 03:42:16 -04:00
Gabe Black
e081615cd9 Now ignore sigaction
src/arch/sparc/isa/operands.isa:
    Added the GSR register as a control register

--HG--
extra : convert_revision : 11ff4016d5c72468dd2daeba3a6105d4e84220ce
2006-07-26 03:40:56 -04:00
Korey Sewell
6e969c31c7 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : be1e5dcb1c5025db8526e628c2060b1790d38227
2006-07-23 13:41:53 -04:00
Korey Sewell
19ca97af79 This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world
succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh!

Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS
ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... )

src/arch/alpha/isa/mem.isa:
    spacing
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
    Gabe really authored this
src/arch/mips/isa/decoder.isa:
    add StoreConditional Flag to instruction
src/arch/mips/isa/formats/basic.isa:
    Steven really did this file
src/arch/mips/isa/formats/branch.isa:
    fix bug for uncond/cond control
src/arch/mips/isa/formats/mem.isa:
    Adjust O3CPU memory access to use new memory model interface.
src/arch/mips/isa/formats/util.isa:
    update LoadStoreBase template
src/arch/mips/isa_traits.cc:
    update SERIALIZE partially
src/arch/mips/process.cc:
src/arch/mips/process.hh:
    no need for this for NOW. ASID/Virtual addressing handles it
src/arch/mips/regfile/misc_regfile.hh:
    add in clear() function and comments for future usage of special misc. regs
src/cpu/base_dyn_inst.hh:
    add in nextNPC variable and supporting functions.

    add isCondDelaySlot function

    Update predTaken and mispredicted functions
src/cpu/base_dyn_inst_impl.hh:
    init nextNPC
src/cpu/o3/SConscript:
    add MIPS files to compile
src/cpu/o3/alpha/thread_context.hh:
    no need for my name on this file
src/cpu/o3/bpred_unit_impl.hh:
    Update RAS appropriately for MIPS
src/cpu/o3/comm.hh:
    add some extra communication variables to aid in handling the
    delay slots
src/cpu/o3/commit.hh:
    minor name fix for nextNPC functions.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
    Fix necessary variables and functions for squashes with delay slots
src/cpu/o3/cpu.cc:
    Update function interface ...

    adjust removeInstsNotInROB function to recognize delay slots insts
src/cpu/o3/cpu.hh:
    update removeInstsNotInROB
src/cpu/o3/decode.hh:
    declare necessary variables for handling delay slot
src/cpu/o3/dyn_inst.hh:
    Add in MipsDynInst
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/rename.hh:
    declare necessary variables and adjust functions for handling delay slot
src/cpu/o3/inst_queue.hh:
src/cpu/simple/base.cc:
    no need for my name here
src/cpu/o3/isa_specific.hh:
    add in MIPS files
src/cpu/o3/scoreboard.hh:
    dont include alpha specific isa traits!
src/cpu/o3/thread_context.hh:
    no need for my name here, i just rearranged where the file goes
src/cpu/static_inst.hh:
    add isCondDelaySlot function
src/cpu/o3/mips/cpu.cc:
src/cpu/o3/mips/cpu.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/mips/dyn_inst.cc:
src/cpu/o3/mips/dyn_inst.hh:
src/cpu/o3/mips/dyn_inst_impl.hh:
src/cpu/o3/mips/impl.hh:
src/cpu/o3/mips/params.hh:
src/cpu/o3/mips/thread_context.cc:
src/cpu/o3/mips/thread_context.hh:
    MIPS file for O3CPU...mirrors ALPHA definition

--HG--
extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
2006-07-23 13:39:42 -04:00
Gabe Black
887e00f18d Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : f6a68bbf8aad9be54ff24310b3e51eaed9abb8b5
2006-07-23 03:06:12 -04:00
Gabe Black
8711078885 Added myself to the authors list.
--HG--
extra : convert_revision : d90154159473ed93c5b50cf3221e132eda242852
2006-07-23 03:04:46 -04:00
Kevin Lim
f9729e999f Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 45650c90385b4e13e79ccf271a30bb55552b380f
2006-07-23 00:10:52 -04:00
Kevin Lim
6ef6e9b14d Fix up test.py
configs/test/test.py:
    Fix up this config.

--HG--
extra : convert_revision : e15071ee27b860cc3ad79277aa61f3e6bb7405d3
2006-07-23 00:10:11 -04:00
Gabe Black
c77cb31473 Reorganized SPARC binaries
--HG--
rename : configs/test/hello_sparc => configs/test/sparc_tests/hello_sparc
extra : convert_revision : d8f36fc9b346f0e89dc8406403576e88bb2dc139
2006-07-22 17:30:50 -04:00
Gabe Black
14b11a9734 Fixed subtract with carry, and started some work with floating point.
src/arch/sparc/isa/decoder.isa:
    fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point.
src/arch/sparc/isa/operands.isa:
    Added in floating point operands, and changed the numbering of operands.
src/arch/sparc/regfile.hh:
    Fixed some memory errors related to floating point.

--HG--
extra : convert_revision : fa0aef2021a5cf99f175fceeb533fe63eb5f805c
2006-07-22 15:50:40 -04:00
Kevin Lim
7ccdb7accc Last minute check in. Very few functional changes other than some minor config updates. Also include some recently generated stats.
SConstruct:
    Make test CPUs option non-sticky.
configs/common/FSConfig.py:
    Be sure to set the memory mode.
configs/test/fs.py:
    Wrong string.
tests/SConscript:
    Only test valid CPUs that have been compiled in.
tests/test1/ref/alpha/atomic/config.ini:
tests/test1/ref/alpha/atomic/config.out:
tests/test1/ref/alpha/atomic/m5stats.txt:
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/config.ini:
tests/test1/ref/alpha/detailed/config.out:
tests/test1/ref/alpha/detailed/m5stats.txt:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/config.ini:
tests/test1/ref/alpha/timing/config.out:
tests/test1/ref/alpha/timing/m5stats.txt:
tests/test1/ref/alpha/timing/stdout:
    Update output.

--HG--
extra : convert_revision : 6eee2a5eae0291b5121b41bcd7021179cdd520a3
2006-07-22 15:50:39 -04:00
Kevin Lim
db5f710a7b Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
    Hand merge.

--HG--
extra : convert_revision : 78f7c46084f66d52ddfe0386fd7c08de8017331e
2006-07-21 16:08:17 -04:00
Kevin Lim
a6c2e5cca0 Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.
configs/test/fs.py:
    Pull out a lot of common code and put it into configs/common/FSConfig.py.

--HG--
extra : convert_revision : 175b18d75f82ddecbcc9a6418fe40df314db55d5
2006-07-21 15:56:35 -04:00
Kevin Lim
acf9cf21a2 Missed some files in a previous check-in. Also check-in the SMT tests. Reference stats will be coming soon.
--HG--
extra : convert_revision : c2f7ea613f350e62395f2b50e4c8cc21c6960a22
2006-07-21 15:53:07 -04:00
Kevin Lim
bf90e1dbde Minor functionality updates.
SConstruct:
    Include an option to specify the CPUs being tested.
src/cpu/SConscript:
    Checker isn't SMT right now, so don't do SMT tests with the O3CPU if we're using the checker.
src/python/m5/objects/O3CPU.py:
    Include default options.  Unfortunately FullO3Config.py is still needed because it specifies which FUPool is being used.
tests/SConscript:
    Several minor updates (sorry for one commit).  Updated the copyright and fixed some m5 style issues.  Also added the ability to specify which CPUs to run the tests on.

--HG--
extra : convert_revision : b0b801115705544ea02e572e31314f7bb8b5f0f2
2006-07-21 15:46:12 -04:00
Kevin Lim
bd33d8d4ac Some reorganization. Options are all handled at the user level script. Move createCpus function (now called connectCpu) to Util.py, where it can be used by other configs.
--HG--
rename : configs/test/SysPaths.py => configs/common/SysPaths.py
extra : convert_revision : 2b1b95c5f29e7ade08b1abd6f24c129d600fe2e8
2006-07-21 15:42:44 -04:00
Gabe Black
8bbe925192 Fixed a glitch in the disassembly output.
--HG--
extra : convert_revision : 833aa358b12ac987e0ab467708425c17e5a8fdb7
2006-07-20 21:01:57 -04:00
Gabe Black
419acd31cb Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 0c696374b19b27c0bd50ffa7f75117b1e211e4bc
2006-07-20 19:04:09 -04:00
Ali Saidi
0850c3dedb Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c7fedc68996f2f6cbfb70baebf7c87e0736da883
2006-07-20 19:04:08 -04:00