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stats: updates due to previous mmap and exit_group patches.

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This commit is contained in:
Nilay Vaish 2014-10-20 16:48:19 -05:00
parent 922a9d8ed2
commit d2a0f60b69
66 changed files with 2106 additions and 2104 deletions
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6
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -402,7 +402,7 @@ system.cpu.fetch.Insts 135034231 # Nu
system.cpu.fetch.Branches 28272297 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11865865 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 113822766 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1679444 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 1679445 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 53 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 32316581 # Number of cache lines fetched
@ -669,7 +669,7 @@ system.cpu.commit.op_class_0::total 91053638 # Cl
system.cpu.commit.bw_lim_events 4115210 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 217038076 # The number of ROB reads
system.cpu.rob.rob_writes 219583064 # The number of ROB writes
system.cpu.rob.rob_writes 219583065 # The number of ROB writes
system.cpu.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 16958 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
@ -678,7 +678,7 @@ system.cpu.cpi 1.274156 # CP
system.cpu.cpi_total 1.274156 # CPI: Total CPI of All Threads
system.cpu.ipc 0.784833 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.784833 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 108123919 # number of integer regfile reads
system.cpu.int_regfile_reads 108123923 # number of integer regfile reads
system.cpu.int_regfile_writes 58738896 # number of integer regfile writes
system.cpu.fp_regfile_reads 58 # number of floating regfile reads
system.cpu.fp_regfile_writes 100 # number of floating regfile writes

8
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes 53956115 # nu
system.cpu.num_mem_refs 27220755 # number of memory refs
system.cpu.num_load_insts 22475911 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 108282001 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 108282000.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 18732304 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction

8
tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -158,10 +158,10 @@ system.cpu.num_cc_register_writes 53956115 # nu
system.cpu.num_mem_refs 27220755 # number of memory refs
system.cpu.num_load_insts 22475911 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 294082436 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 294082435.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 18732304 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction

8
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -80,10 +80,10 @@ system.cpu.num_fp_register_writes 90 # nu
system.cpu.num_mem_refs 105711441 # number of memory refs
system.cpu.num_load_insts 82803521 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 244431648 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 244431647.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 29302884 # Number of branches fetched
system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction

8
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -72,10 +72,10 @@ system.cpu.num_fp_register_writes 90 # nu
system.cpu.num_mem_refs 105711441 # number of memory refs
system.cpu.num_load_insts 82803521 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 722977060 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 722977059.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 29302884 # Number of branches fetched
system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction

14
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -313,7 +313,7 @@ system.cpu.fetch.Insts 201519425 # Nu
system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 94568947 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1664994 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 1664995 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions
@ -518,11 +518,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 47392313 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 797958 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 117208009 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 117208008 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 52857681 45.10% 45.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 52857680 45.10% 45.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 10970810 9.36% 68.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8748486 7.46% 75.54% # Number of insts commited each cycle
@ -534,7 +534,7 @@ system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 117208009 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 117208008 # Number of insts commited each cycle
system.cpu.commit.committedInsts 157988547 # Number of instructions committed
system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -582,8 +582,8 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% #
system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
system.cpu.commit.bw_lim_events 23468572 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 419324214 # The number of ROB reads
system.cpu.rob.rob_writes 657627212 # The number of ROB writes
system.cpu.rob.rob_reads 419324213 # The number of ROB reads
system.cpu.rob.rob_writes 657627213 # The number of ROB writes
system.cpu.timesIdled 611 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 58315 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
@ -592,7 +592,7 @@ system.cpu.cpi 0.783061 # CP
system.cpu.cpi_total 0.783061 # CPI: Total CPI of All Threads
system.cpu.ipc 1.277040 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.277040 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 493625450 # number of integer regfile reads
system.cpu.int_regfile_reads 493625454 # number of integer regfile reads
system.cpu.int_regfile_writes 240898259 # number of integer regfile writes
system.cpu.fp_regfile_reads 178 # number of floating regfile reads
system.cpu.fp_regfile_writes 135 # number of floating regfile writes

8
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes 61764861 # nu
system.cpu.num_mem_refs 122219137 # number of memory refs
system.cpu.num_load_insts 90779385 # Number of load instructions
system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 337900081 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 337900080.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 29309705 # Number of branches fetched
system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction

40
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes 61764861 # nu
system.cpu.num_mem_refs 122219137 # number of memory refs
system.cpu.num_load_insts 90779385 # Number of load instructions
system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 731978130 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 731978129.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 29309705 # Number of branches fetched
system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
@ -127,9 +127,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu.op_class::total 278192465 # Class of executed instruction
system.cpu.icache.tags.replacements 24 # number of replacements
system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks.
system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
@ -139,14 +139,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 46
system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 435393138 # Number of tag accesses
system.cpu.icache.tags.data_accesses 435393138 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits
system.cpu.icache.overall_hits::total 217695357 # number of overall hits
system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses
system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits
system.cpu.icache.overall_hits::total 217695356 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
@ -159,12 +159,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 44230000
system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses

6
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

@ -409,7 +409,7 @@ system.cpu.fetch.Insts 731737281 # Nu
system.cpu.fetch.Branches 175071152 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 95967885 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 447534266 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 14941834 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 14941835 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 5427 # Number of stall cycles due to full MSHR
@ -677,7 +677,7 @@ system.cpu.commit.op_class_0::total 548694828 # Cl
system.cpu.commit.bw_lim_events 13835955 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1090469902 # The number of ROB reads
system.cpu.rob.rob_writes 1334452491 # The number of ROB writes
system.cpu.rob.rob_writes 1334452492 # The number of ROB writes
system.cpu.timesIdled 9125 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 280326 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
@ -686,7 +686,7 @@ system.cpu.cpi 0.916475 # CP
system.cpu.cpi_total 0.916475 # CPI: Total CPI of All Threads
system.cpu.ipc 1.091137 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.091137 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 611059108 # number of integer regfile reads
system.cpu.int_regfile_reads 611059162 # number of integer regfile reads
system.cpu.int_regfile_writes 328109228 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.cc_regfile_reads 2170105339 # number of cc regfile reads

8
tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
View file

@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes 344080722 # nu
system.cpu.num_mem_refs 172745235 # number of memory refs
system.cpu.num_load_insts 115884756 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 558724596 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 558724595.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 121548301 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction

8
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -166,10 +166,10 @@ system.cpu.num_cc_register_writes 344080722 # nu
system.cpu.num_mem_refs 172745235 # number of memory refs
system.cpu.num_load_insts 115884756 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1415078046 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1415078045.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 121548301 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction

14
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

@ -332,7 +332,7 @@ system.cpu.fetch.Insts 1278658073 # Nu
system.cpu.fetch.Branches 231811700 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 157369245 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 706106364 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 20239876 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 20239877 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 1021 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 98431 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 825605 # Number of stall cycles due to pending traps
@ -539,11 +539,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 584047933 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 9837228 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 824173639 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 824173638 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.855178 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.504108 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 355774645 43.17% 43.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 355774644 43.17% 43.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 174944190 21.23% 64.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 57267566 6.95% 71.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 86311577 10.47% 81.82% # Number of insts commited each cycle
@ -555,7 +555,7 @@ system.cpu.commit.committed_per_cycle::8 76959576 9.34% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 824173639 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 824173638 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -603,8 +603,8 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% #
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
system.cpu.commit.bw_lim_events 76959576 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2860250697 # The number of ROB reads
system.cpu.rob.rob_writes 4305432555 # The number of ROB writes
system.cpu.rob.rob_reads 2860250696 # The number of ROB reads
system.cpu.rob.rob_writes 4305432556 # The number of ROB writes
system.cpu.timesIdled 2603 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 181705 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
@ -613,7 +613,7 @@ system.cpu.cpi 1.092700 # CP
system.cpu.cpi_total 1.092700 # CPI: Total CPI of All Threads
system.cpu.ipc 0.915164 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.915164 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2763452160 # number of integer regfile reads
system.cpu.int_regfile_reads 2763452214 # number of integer regfile reads
system.cpu.int_regfile_writes 1467518123 # number of integer regfile writes
system.cpu.fp_regfile_reads 6756 # number of floating regfile reads
system.cpu.fp_regfile_writes 202 # number of floating regfile writes

8
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes 376685745 # nu
system.cpu.num_mem_refs 533262343 # number of memory refs
system.cpu.num_load_insts 384102157 # Number of load instructions
system.cpu.num_store_insts 149160186 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1770458657 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1770458656.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 149758583 # Number of branches fetched
system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction
system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction

40
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes 376685745 # nu
system.cpu.num_mem_refs 533262343 # number of memory refs
system.cpu.num_load_insts 384102157 # Number of load instructions
system.cpu.num_store_insts 149160186 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3295745698 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 3295745697.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 149758583 # Number of branches fetched
system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction
system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction
@ -127,9 +127,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu.op_class::total 1528988702 # Class of executed instruction
system.cpu.icache.tags.replacements 1253 # number of replacements
system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks.
system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
@ -141,14 +141,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 7
system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2136696946 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2136696946 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits
system.cpu.icache.overall_hits::total 1068344252 # number of overall hits
system.cpu.icache.tags.tag_accesses 2136696944 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2136696944 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1068344251 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068344251 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068344251 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068344251 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068344251 # number of overall hits
system.cpu.icache.overall_hits::total 1068344251 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
@ -161,12 +161,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 115806000
system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1068347065 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1068347065 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1068347065 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses

6
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

@ -377,7 +377,7 @@ system.cpu.fetch.Insts 334152318 # Nu
system.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3511516 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 3511517 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR
@ -646,7 +646,7 @@ system.cpu.commit.op_class_0::total 327812213 # Cl
system.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 561656707 # The number of ROB reads
system.cpu.rob.rob_writes 705358338 # The number of ROB writes
system.cpu.rob.rob_writes 705358339 # The number of ROB writes
system.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273037219 # Number of Instructions Simulated
@ -655,7 +655,7 @@ system.cpu.cpi 0.824361 # CP
system.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads
system.cpu.ipc 1.213060 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 331187238 # number of integer regfile reads
system.cpu.int_regfile_reads 331187240 # number of integer regfile reads
system.cpu.int_regfile_writes 136909181 # number of integer regfile writes
system.cpu.fp_regfile_reads 187100304 # number of floating regfile reads
system.cpu.fp_regfile_writes 132166714 # number of floating regfile writes

8
tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
View file

@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes 76361749 # nu
system.cpu.num_mem_refs 168107829 # number of memory refs
system.cpu.num_load_insts 85732235 # Number of load instructions
system.cpu.num_store_insts 82375594 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 403434628 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 403434627.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 30563490 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 104312492 31.82% 31.82% # Class of executed instruction

8
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
View file

@ -158,10 +158,10 @@ system.cpu.num_cc_register_writes 76361814 # nu
system.cpu.num_mem_refs 168107847 # number of memory refs
system.cpu.num_load_insts 85732248 # Number of load instructions
system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1034470822 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1034470821.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 30563502 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction

8
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

@ -420,11 +420,11 @@ system.cpu.numCycles 815767570 # nu
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed
system.cpu.fetch.Insts 1200075862 # Number of instructions fetch has processed
system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 31064710 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 31064711 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR
@ -692,7 +692,7 @@ system.cpu.commit.op_class_0::total 788730069 # Cl
system.cpu.commit.bw_lim_events 22360845 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1888573713 # The number of ROB reads
system.cpu.rob.rob_writes 2343133825 # The number of ROB writes
system.cpu.rob.rob_writes 2343133826 # The number of ROB writes
system.cpu.timesIdled 646395 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 155573 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 640649298 # Number of Instructions Simulated
@ -701,7 +701,7 @@ system.cpu.cpi 1.273345 # CP
system.cpu.cpi_total 1.273345 # CPI: Total CPI of All Threads
system.cpu.ipc 0.785333 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.785333 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 995802638 # number of integer regfile reads
system.cpu.int_regfile_reads 995802642 # number of integer regfile reads
system.cpu.int_regfile_writes 567917186 # number of integer regfile writes
system.cpu.fp_regfile_reads 31889847 # number of floating regfile reads
system.cpu.fp_regfile_writes 22959506 # number of floating regfile writes

8
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
View file

@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes 351919006 # nu
system.cpu.num_mem_refs 381221435 # number of memory refs
system.cpu.num_load_insts 252240938 # Number of load instructions
system.cpu.num_store_insts 128980497 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 791453557 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 791453556.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 137364859 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction

8
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
View file

@ -166,10 +166,10 @@ system.cpu.num_cc_register_writes 351919006 # nu
system.cpu.num_mem_refs 381221435 # number of memory refs
system.cpu.num_load_insts 252240938 # Number of load instructions
system.cpu.num_store_insts 128980497 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 2087390168 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 2087390167.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 137364859 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction

6
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

@ -409,7 +409,7 @@ system.cpu.fetch.Insts 88199449 # Nu
system.cpu.fetch.Branches 17209876 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9548195 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 59293355 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1322460 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 1322461 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1971 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 4935 # Number of stall cycles due to full MSHR
@ -677,7 +677,7 @@ system.cpu.commit.op_class_0::total 90688136 # Cl
system.cpu.commit.bw_lim_events 3803570 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 157213253 # The number of ROB reads
system.cpu.rob.rob_writes 195483387 # The number of ROB writes
system.cpu.rob.rob_writes 195483388 # The number of ROB writes
system.cpu.timesIdled 20301 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 345307 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 70907629 # Number of Instructions Simulated
@ -686,7 +686,7 @@ system.cpu.cpi 0.919935 # CP
system.cpu.cpi_total 0.919935 # CPI: Total CPI of All Threads
system.cpu.ipc 1.087033 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.087033 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 102236516 # number of integer regfile reads
system.cpu.int_regfile_reads 102236524 # number of integer regfile reads
system.cpu.int_regfile_writes 56794814 # number of integer regfile writes
system.cpu.fp_regfile_reads 36 # number of floating regfile reads
system.cpu.fp_regfile_writes 21 # number of floating regfile writes

8
tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
View file

@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes 36877020 # nu
system.cpu.num_mem_refs 43422001 # number of memory refs
system.cpu.num_load_insts 22866262 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 97920023 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 97920022.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 13741485 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction

8
tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
View file

@ -166,10 +166,10 @@ system.cpu.num_cc_register_writes 36877020 # nu
system.cpu.num_mem_refs 43422001 # number of memory refs
system.cpu.num_load_insts 22866262 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 254587966 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 254587965.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 13741485 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction

8
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -80,10 +80,10 @@ system.cpu.num_fp_register_writes 1150968 # nu
system.cpu.num_mem_refs 58160248 # number of memory refs
system.cpu.num_load_insts 37275867 # Number of load instructions
system.cpu.num_store_insts 20884381 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 136297345 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 136297344.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12719095 # Number of branches fetched
system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction

8
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
View file

@ -80,10 +80,10 @@ system.cpu.num_fp_register_writes 1150968 # nu
system.cpu.num_mem_refs 58160248 # number of memory refs
system.cpu.num_load_insts 37275867 # Number of load instructions
system.cpu.num_store_insts 20884381 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 404484520 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 404484519.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12719095 # Number of branches fetched
system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction

6
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

@ -424,7 +424,7 @@ system.cpu.fetch.Insts 2067206547 # Nu
system.cpu.fetch.Branches 286237274 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 166967181 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1477423210 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 29286858 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 29286859 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 656844028 # Number of cache lines fetched
@ -691,7 +691,7 @@ system.cpu.commit.op_class_0::total 1664032433 # Cl
system.cpu.commit.bw_lim_events 58313739 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3330084063 # The number of ROB reads
system.cpu.rob.rob_writes 3883248691 # The number of ROB writes
system.cpu.rob.rob_writes 3883248692 # The number of ROB writes
system.cpu.timesIdled 433 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 24299 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
@ -700,7 +700,7 @@ system.cpu.cpi 0.975038 # CP
system.cpu.cpi_total 0.975038 # CPI: Total CPI of All Threads
system.cpu.ipc 1.025601 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.025601 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2176017050 # number of integer regfile reads
system.cpu.int_regfile_reads 2176017062 # number of integer regfile reads
system.cpu.int_regfile_writes 1261587528 # number of integer regfile writes
system.cpu.fp_regfile_reads 38 # number of floating regfile reads
system.cpu.fp_regfile_writes 49 # number of floating regfile writes

8
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
View file

@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes 518236214 # nu
system.cpu.num_mem_refs 633153380 # number of memory refs
system.cpu.num_load_insts 458306334 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1664034981 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1664034980.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 213462426 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction

8
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
View file

@ -166,10 +166,10 @@ system.cpu.num_cc_register_writes 518236214 # nu
system.cpu.num_mem_refs 633153380 # number of memory refs
system.cpu.num_load_insts 458306334 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4727341996 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 4727341995.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 213462426 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction

8
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
View file

@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes 1355930461 # nu
system.cpu.num_mem_refs 1677713084 # number of memory refs
system.cpu.num_load_insts 1239184746 # Number of load instructions
system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5692014456 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 5692014455.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 248500691 # Number of branches fetched
system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction

40
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View file

@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes 1355930461 # nu
system.cpu.num_mem_refs 1677713084 # number of memory refs
system.cpu.num_load_insts 1239184746 # Number of load instructions
system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 11765161052 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 11765161051.998001 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 248500691 # Number of branches fetched
system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
@ -127,9 +127,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu.op_class::total 4686862596 # Class of executed instruction
system.cpu.icache.tags.replacements 10 # number of replacements
system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks.
system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
@ -138,14 +138,14 @@ system.cpu.icache.tags.occ_task_id_blocks::1024 665
system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 8026466441 # Number of tag accesses
system.cpu.icache.tags.data_accesses 8026466441 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits
system.cpu.icache.overall_hits::total 4013232208 # number of overall hits
system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses
system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits
system.cpu.icache.overall_hits::total 4013232207 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
@ -158,12 +158,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 37156000
system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses

6
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
View file

@ -375,7 +375,7 @@ system.cpu.fetch.Insts 349266175 # Nu
system.cpu.fetch.Branches 85925623 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 42726403 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 158254745 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 12044332 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 12044333 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingQuiesceStallCycles 37 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 592 # Number of stall cycles due to full MSHR
@ -644,7 +644,7 @@ system.cpu.commit.op_class_0::total 181650341 # Cl
system.cpu.commit.bw_lim_events 3353878 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 406255589 # The number of ROB reads
system.cpu.rob.rob_writes 513821131 # The number of ROB writes
system.cpu.rob.rob_writes 513821132 # The number of ROB writes
system.cpu.timesIdled 2630 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 38922 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 172303021 # Number of Instructions Simulated
@ -653,7 +653,7 @@ system.cpu.cpi 0.986122 # CP
system.cpu.cpi_total 0.986122 # CPI: Total CPI of All Threads
system.cpu.ipc 1.014073 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.014073 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 218958563 # number of integer regfile reads
system.cpu.int_regfile_reads 218958580 # number of integer regfile reads
system.cpu.int_regfile_writes 114511116 # number of integer regfile writes
system.cpu.fp_regfile_reads 2904510 # number of floating regfile reads
system.cpu.fp_regfile_writes 2441819 # number of floating regfile writes

8
tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -171,10 +171,10 @@ system.cpu.num_cc_register_writes 190815535 # nu
system.cpu.num_mem_refs 40540779 # number of memory refs
system.cpu.num_load_insts 27896144 # Number of load instructions
system.cpu.num_store_insts 12644635 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 199192983 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 199192982.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 40300311 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction

8
tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
View file

@ -158,10 +158,10 @@ system.cpu.num_cc_register_writes 190815535 # nu
system.cpu.num_mem_refs 40540779 # number of memory refs
system.cpu.num_load_insts 27896144 # Number of load instructions
system.cpu.num_store_insts 12644635 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 460346714 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 460346713.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 40300311 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction

8
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -80,10 +80,10 @@ system.cpu.num_fp_register_writes 2974850 # nu
system.cpu.num_mem_refs 76733958 # number of memory refs
system.cpu.num_load_insts 57735091 # Number of load instructions
system.cpu.num_store_insts 18998867 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 193445891 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 193445890.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 15132745 # Number of branches fetched
system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction
system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction

8
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -72,10 +72,10 @@ system.cpu.num_fp_register_writes 2974850 # nu
system.cpu.num_mem_refs 76733958 # number of memory refs
system.cpu.num_load_insts 57735091 # Number of load instructions
system.cpu.num_store_insts 18998867 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 541126164 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 541126163.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 15132745 # Number of branches fetched
system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction
system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction

14
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

@ -292,7 +292,7 @@ system.cpu.fetch.Insts 249058784 # Nu
system.cpu.fetch.Branches 22382097 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 14763235 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 267434691 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3695048 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 3695049 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 15 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 4561 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 42381 # Number of stall cycles due to pending traps
@ -499,11 +499,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 119784082 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1557714 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 280934179 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 280934178 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.787955 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.593006 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 181002456 64.43% 64.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 181002455 64.43% 64.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 57799506 20.57% 85.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 14236358 5.07% 90.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 11930779 4.25% 94.32% # Number of insts commited each cycle
@ -515,7 +515,7 @@ system.cpu.commit.committed_per_cycle::8 6891030 2.45% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 280934179 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 280934178 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -563,8 +563,8 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% #
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
system.cpu.commit.bw_lim_events 6891030 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 615190615 # The number of ROB reads
system.cpu.rob.rob_writes 698614568 # The number of ROB writes
system.cpu.rob.rob_reads 615190614 # The number of ROB reads
system.cpu.rob.rob_writes 698614569 # The number of ROB writes
system.cpu.timesIdled 3122 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 178726 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
@ -573,7 +573,7 @@ system.cpu.cpi 2.251725 # CP
system.cpu.cpi_total 2.251725 # CPI: Total CPI of All Threads
system.cpu.ipc 0.444104 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.444104 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 456361988 # number of integer regfile reads
system.cpu.int_regfile_reads 456362005 # number of integer regfile reads
system.cpu.int_regfile_writes 239113538 # number of integer regfile writes
system.cpu.fp_regfile_reads 3275482 # number of floating regfile reads
system.cpu.fp_regfile_writes 2058196 # number of floating regfile writes

8
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes 56242058 # nu
system.cpu.num_mem_refs 77165304 # number of memory refs
system.cpu.num_load_insts 56649587 # Number of load instructions
system.cpu.num_store_insts 20515717 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 262786559 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 262786558.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12326938 # Number of branches fetched
system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction

40
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
View file

@ -77,10 +77,10 @@ system.cpu.num_cc_register_writes 56242058 # nu
system.cpu.num_mem_refs 77165304 # number of memory refs
system.cpu.num_load_insts 56649587 # Number of load instructions
system.cpu.num_store_insts 20515717 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 501907914 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 501907913.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12326938 # Number of branches fetched
system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
@ -119,9 +119,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu.op_class::total 221363385 # Class of executed instruction
system.cpu.icache.tags.replacements 2836 # number of replacements
system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks.
system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
@ -133,14 +133,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 498
system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 346993430 # Number of tag accesses
system.cpu.icache.tags.data_accesses 346993430 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 173489674 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 173489674 # number of overall hits
system.cpu.icache.overall_hits::total 173489674 # number of overall hits
system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses
system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits
system.cpu.icache.overall_hits::total 173489673 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
@ -153,12 +153,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 180319000
system.cpu.icache.demand_miss_latency::total 180319000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 180319000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 180319000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 173494368 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 173494368 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 173494368 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 173494368 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 173494368 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 173494368 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses

2
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
View file

@ -599,7 +599,7 @@ system.cpu.cpi 6.446328 # CP
system.cpu.cpi_total 6.446328 # CPI: Total CPI of All Threads
system.cpu.ipc 0.155127 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.155127 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12991 # number of integer regfile reads
system.cpu.int_regfile_reads 12992 # number of integer regfile reads
system.cpu.int_regfile_writes 7455 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes

56
tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
View file

@ -371,9 +371,9 @@ system.cpu.tickCycles 10521 # Nu
system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 3 # number of replacements
system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
system.cpu.icache.tags.total_refs 1918 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 5.978193 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 5.975078 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy
@ -382,14 +382,14 @@ system.cpu.icache.tags.occ_task_id_blocks::1024 318
system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4801 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4801 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
system.cpu.icache.overall_hits::total 1919 # number of overall hits
system.cpu.icache.tags.tag_accesses 4799 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4799 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1918 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1918 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1918 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1918 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1918 # number of overall hits
system.cpu.icache.overall_hits::total 1918 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses
@ -402,18 +402,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 21503250
system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2240 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2240 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2240 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2240 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2240 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2240 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143304 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.143304 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.143304 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.143304 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.143304 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.143304 # miss rate for overall accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 2239 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2239 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2239 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2239 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2239 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2239 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143368 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.143368 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.143368 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.143368 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.143368 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.143368 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
@ -440,12 +440,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750
system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143304 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.143304 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.143304 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143368 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.143368 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.143368 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency

6
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
View file

@ -457,7 +457,7 @@ system.cpu.fetch.Insts 12484 # Nu
system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 1011 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
@ -728,7 +728,7 @@ system.cpu.commit.op_class_0::total 5377 # Cl
system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 22692 # The number of ROB reads
system.cpu.rob.rob_writes 21719 # The number of ROB writes
system.cpu.rob.rob_writes 21720 # The number of ROB writes
system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4591 # Number of Instructions Simulated
@ -737,7 +737,7 @@ system.cpu.cpi 7.067523 # CP
system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads
system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 7944 # number of integer regfile reads
system.cpu.int_regfile_reads 7945 # number of integer regfile reads
system.cpu.int_regfile_writes 4420 # number of integer regfile writes
system.cpu.fp_regfile_reads 31 # number of floating regfile reads
system.cpu.cc_regfile_reads 28734 # number of cc regfile reads

6
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
View file

@ -375,7 +375,7 @@ system.cpu.fetch.Insts 12370 # Nu
system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1062 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 1063 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR
@ -643,7 +643,7 @@ system.cpu.commit.op_class_0::total 5377 # Cl
system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 24066 # The number of ROB reads
system.cpu.rob.rob_writes 16749 # The number of ROB writes
system.cpu.rob.rob_writes 16750 # The number of ROB writes
system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4591 # Number of Instructions Simulated
@ -652,7 +652,7 @@ system.cpu.cpi 5.166630 # CP
system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads
system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 6786 # number of integer regfile reads
system.cpu.int_regfile_reads 6787 # number of integer regfile reads
system.cpu.int_regfile_writes 3839 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.cc_regfile_reads 24301 # number of cc regfile reads

8
tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
View file

@ -256,10 +256,10 @@ system.cpu.num_cc_register_writes 2432 # nu
system.cpu.num_mem_refs 1965 # number of memory refs
system.cpu.num_load_insts 1027 # Number of load instructions
system.cpu.num_store_insts 938 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5390 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1007 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction

8
tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
View file

@ -169,10 +169,10 @@ system.cpu.num_cc_register_writes 2432 # nu
system.cpu.num_mem_refs 1965 # number of memory refs
system.cpu.num_load_insts 1027 # Number of load instructions
system.cpu.num_store_insts 938 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5390 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1007 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction

8
tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
View file

@ -158,10 +158,10 @@ system.cpu.num_cc_register_writes 2432 # nu
system.cpu.num_mem_refs 1965 # number of memory refs
system.cpu.num_load_insts 1027 # Number of load instructions
system.cpu.num_store_insts 938 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 51630 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 51629.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1007 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction

869
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

1251
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

190
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
View file

@ -1,61 +1,61 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2907000 # Number of ticks simulated
final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 2812000 # Number of ticks simulated
final_tick 2812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 972729 # Simulator instruction rate (inst/s)
host_op_rate 970456 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 484177215 # Simulator tick rate (ticks/s)
host_mem_usage 275596 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
host_inst_rate 65844 # Simulator instruction rate (inst/s)
host_op_rate 65830 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 32908431 # Simulator tick rate (ticks/s)
host_mem_usage 267356 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4374 # Number of bytes read from this memory
system.physmem.bytes_read::total 27634 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 23260 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 23260 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 3658 # Number of bytes written to this memory
system.physmem.bytes_written::total 3658 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 5815 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1163 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6978 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 925 # Number of write requests responded to by this memory
system.physmem.num_writes::total 925 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 8001375989 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1504643963 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9506019952 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8001375989 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8001375989 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1258341933 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1258341933 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8001375989 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2762985896 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10764361885 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 6978 # Transaction distribution
system.membus.trans_dist::ReadResp 6978 # Transaction distribution
system.membus.trans_dist::WriteReq 925 # Transaction distribution
system.membus.trans_dist::WriteResp 925 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11630 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4176 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15806 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23260 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8032 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 31292 # Cumulative packet size per connected master and slave (bytes)
system.physmem.bytes_read::cpu.inst 22500 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4289 # Number of bytes read from this memory
system.physmem.bytes_read::total 26789 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 22500 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22500 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 3601 # Number of bytes written to this memory
system.physmem.bytes_written::total 3601 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 5625 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1132 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6757 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 901 # Number of write requests responded to by this memory
system.physmem.num_writes::total 901 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 8001422475 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1525248933 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9526671408 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8001422475 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8001422475 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1280583215 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1280583215 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8001422475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2805832148 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10807254623 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 6757 # Transaction distribution
system.membus.trans_dist::ReadResp 6757 # Transaction distribution
system.membus.trans_dist::WriteReq 901 # Transaction distribution
system.membus.trans_dist::WriteResp 901 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11250 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4066 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15316 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22500 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7890 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 7903 # Request fanout histogram
system.membus.snoop_fanout::mean 0.735797 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.440936 # Request fanout histogram
system.membus.snoop_fanout::samples 7658 # Request fanout histogram
system.membus.snoop_fanout::mean 0.734526 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.441614 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2088 26.42% 26.42% # Request fanout histogram
system.membus.snoop_fanout::1 5815 73.58% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 2033 26.55% 26.55% # Request fanout histogram
system.membus.snoop_fanout::1 5625 73.45% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 7903 # Request fanout histogram
system.membus.snoop_fanout::total 7658 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -75,64 +75,64 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 5815 # number of cpu cycles simulated
system.cpu.workload.num_syscalls 7 # Number of system calls
system.cpu.numCycles 5625 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5814 # Number of instructions committed
system.cpu.committedOps 5814 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses
system.cpu.committedInsts 5624 # Number of instructions committed
system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 194 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls
system.cpu.num_int_insts 5113 # number of integer instructions
system.cpu.num_func_calls 190 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
system.cpu.num_int_insts 4944 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_int_register_reads 7284 # number of times the integer registers were read
system.cpu.num_int_register_writes 3397 # number of times the integer registers were written
system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2089 # number of memory refs
system.cpu.num_load_insts 1163 # Number of load instructions
system.cpu.num_store_insts 926 # Number of store instructions
system.cpu.num_mem_refs 2034 # number of memory refs
system.cpu.num_load_insts 1132 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5815 # Number of busy cycles
system.cpu.num_busy_cycles 5625 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 915 # Number of branches fetched
system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction
system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction
system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction
system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction
system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction
system.cpu.Branches 883 # Number of branches fetched
system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5815 # Class of executed instruction
system.cpu.op_class::total 5625 # Class of executed instruction
---------- End Simulation Statistics ----------

522
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
View file

@ -1,109 +1,109 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000125 # Number of seconds simulated
sim_ticks 125334 # Number of ticks simulated
final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000123 # Number of seconds simulated
sim_ticks 122907 # Number of ticks simulated
final_tick 122907 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 56489 # Simulator instruction rate (inst/s)
host_op_rate 56481 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1217426 # Simulator tick rate (ticks/s)
host_mem_usage 162604 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
host_inst_rate 19204 # Simulator instruction rate (inst/s)
host_op_rate 19202 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 419624 # Simulator tick rate (ticks/s)
host_mem_usage 174296 # Number of bytes of host memory used
host_seconds 0.29 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 2982 # delay histogram for all message
system.ruby.delayHist | 2982 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 2982 # delay histogram for all message
system.ruby.delayHist::samples 2936 # delay histogram for all message
system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 2936 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
system.ruby.outstanding_req_hist::samples 7904
system.ruby.outstanding_req_hist::samples 7659
system.ruby.outstanding_req_hist::mean 1
system.ruby.outstanding_req_hist::gmean 1
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7904 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist::total 7904
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist::total 7659
system.ruby.latency_hist::bucket_size 16
system.ruby.latency_hist::max_bucket 159
system.ruby.latency_hist::samples 7903
system.ruby.latency_hist::mean 14.859041
system.ruby.latency_hist::gmean 5.372254
system.ruby.latency_hist::stdev 24.716041
system.ruby.latency_hist | 6410 81.11% 81.11% | 0 0.00% 81.11% | 0 0.00% 81.11% | 328 4.15% 85.26% | 1088 13.77% 99.03% | 74 0.94% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist::total 7903
system.ruby.latency_hist::samples 7658
system.ruby.latency_hist::mean 15.049491
system.ruby.latency_hist::gmean 5.422767
system.ruby.latency_hist::stdev 24.869733
system.ruby.latency_hist | 6188 80.80% 80.80% | 0 0.00% 80.80% | 0 0.00% 80.80% | 330 4.31% 85.11% | 1061 13.85% 98.97% | 77 1.01% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist::total 7658
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
system.ruby.hit_latency_hist::samples 6410
system.ruby.hit_latency_hist::samples 6188
system.ruby.hit_latency_hist::mean 3
system.ruby.hit_latency_hist::gmean 3.000000
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6410 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist::total 6410
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist::total 6188
system.ruby.miss_latency_hist::bucket_size 16
system.ruby.miss_latency_hist::max_bucket 159
system.ruby.miss_latency_hist::samples 1493
system.ruby.miss_latency_hist::mean 65.774280
system.ruby.miss_latency_hist::gmean 65.543617
system.ruby.miss_latency_hist::stdev 6.088981
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 328 21.97% 21.97% | 1088 72.87% 94.84% | 74 4.96% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist::total 1493
system.ruby.Directory.incomplete_times 1492
system.ruby.miss_latency_hist::samples 1470
system.ruby.miss_latency_hist::mean 65.772109
system.ruby.miss_latency_hist::gmean 65.537231
system.ruby.miss_latency_hist::stdev 6.143987
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 330 22.45% 22.45% | 1061 72.18% 94.63% | 77 5.24% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist::total 1470
system.ruby.Directory.incomplete_times 1469
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6410 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1493 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7903 # Number of cache demand accesses
system.ruby.network.routers0.percent_links_utilized 5.948107
system.ruby.network.routers0.msg_count.Control::2 1493
system.ruby.network.routers0.msg_count.Data::2 1489
system.ruby.network.routers0.msg_count.Response_Data::4 1493
system.ruby.network.routers0.msg_count.Writeback_Control::3 1489
system.ruby.network.routers0.msg_bytes.Control::2 11944
system.ruby.network.routers0.msg_bytes.Data::2 107208
system.ruby.network.routers0.msg_bytes.Response_Data::4 107496
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11912
system.ruby.dir_cntrl0.memBuffer.memReq 2982 # Total number of memory requests
system.ruby.dir_cntrl0.memBuffer.memRead 1493 # Number of memory reads
system.ruby.dir_cntrl0.memBuffer.memWrite 1489 # Number of memory writes
system.ruby.dir_cntrl0.memBuffer.memRefresh 871 # Number of memory refreshes
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 2125 # Delay stalled at the head of the bank queue
system.ruby.dir_cntrl0.memBuffer.memBankQ 5 # Delay behind the head of the bank queue
system.ruby.dir_cntrl0.memBuffer.totalStalls 2130 # Total number of stall cycles
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.714286 # Expected number of stall cycles per request
system.ruby.dir_cntrl0.memBuffer.memBankBusy 839 # memory stalls due to busy bank
system.ruby.dir_cntrl0.memBuffer.memBusBusy 1172 # memory stalls due to busy bus
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 34 # memory stalls due to read write turnaround
system.ruby.dir_cntrl0.memBuffer.memArbWait 80 # memory stalls due to arbitration
system.ruby.dir_cntrl0.memBuffer.memBankCount | 236 7.91% 7.91% | 108 3.62% 11.54% | 74 2.48% 14.02% | 51 1.71% 15.73% | 26 0.87% 16.60% | 104 3.49% 20.09% | 18 0.60% 20.69% | 38 1.27% 21.97% | 16 0.54% 22.50% | 52 1.74% 24.25% | 154 5.16% 29.41% | 50 1.68% 31.09% | 22 0.74% 31.82% | 70 2.35% 34.17% | 30 1.01% 35.18% | 220 7.38% 42.56% | 80 2.68% 45.24% | 58 1.95% 47.18% | 80 2.68% 49.87% | 118 3.96% 53.82% | 42 1.41% 55.23% | 52 1.74% 56.98% | 82 2.75% 59.73% | 168 5.63% 65.36% | 116 3.89% 69.25% | 80 2.68% 71.93% | 138 4.63% 76.56% | 110 3.69% 80.25% | 208 6.98% 87.22% | 273 9.15% 96.38% | 40 1.34% 97.72% | 68 2.28% 100.00% # Number of accesses per bank
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2982 # Number of accesses per bank
system.ruby.network.routers1.percent_links_utilized 5.948107
system.ruby.network.routers1.msg_count.Control::2 1493
system.ruby.network.routers1.msg_count.Data::2 1489
system.ruby.network.routers1.msg_count.Response_Data::4 1493
system.ruby.network.routers1.msg_count.Writeback_Control::3 1489
system.ruby.network.routers1.msg_bytes.Control::2 11944
system.ruby.network.routers1.msg_bytes.Data::2 107208
system.ruby.network.routers1.msg_bytes.Response_Data::4 107496
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11912
system.ruby.network.routers2.percent_links_utilized 5.948107
system.ruby.network.routers2.msg_count.Control::2 1493
system.ruby.network.routers2.msg_count.Data::2 1489
system.ruby.network.routers2.msg_count.Response_Data::4 1493
system.ruby.network.routers2.msg_count.Writeback_Control::3 1489
system.ruby.network.routers2.msg_bytes.Control::2 11944
system.ruby.network.routers2.msg_bytes.Data::2 107208
system.ruby.network.routers2.msg_bytes.Response_Data::4 107496
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11912
system.ruby.network.msg_count.Control 4479
system.ruby.network.msg_count.Data 4467
system.ruby.network.msg_count.Response_Data 4479
system.ruby.network.msg_count.Writeback_Control 4467
system.ruby.network.msg_byte.Control 35832
system.ruby.network.msg_byte.Data 321624
system.ruby.network.msg_byte.Response_Data 322488
system.ruby.network.msg_byte.Writeback_Control 35736
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.ruby.network.routers0.percent_links_utilized 5.971995
system.ruby.network.routers0.msg_count.Control::2 1470
system.ruby.network.routers0.msg_count.Data::2 1466
system.ruby.network.routers0.msg_count.Response_Data::4 1470
system.ruby.network.routers0.msg_count.Writeback_Control::3 1466
system.ruby.network.routers0.msg_bytes.Control::2 11760
system.ruby.network.routers0.msg_bytes.Data::2 105552
system.ruby.network.routers0.msg_bytes.Response_Data::4 105840
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728
system.ruby.dir_cntrl0.memBuffer.memReq 2936 # Total number of memory requests
system.ruby.dir_cntrl0.memBuffer.memRead 1470 # Number of memory reads
system.ruby.dir_cntrl0.memBuffer.memWrite 1466 # Number of memory writes
system.ruby.dir_cntrl0.memBuffer.memRefresh 854 # Number of memory refreshes
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 2108 # Delay stalled at the head of the bank queue
system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue
system.ruby.dir_cntrl0.memBuffer.totalStalls 2110 # Total number of stall cycles
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.718665 # Expected number of stall cycles per request
system.ruby.dir_cntrl0.memBuffer.memBankBusy 845 # memory stalls due to busy bank
system.ruby.dir_cntrl0.memBuffer.memBusBusy 1147 # memory stalls due to busy bus
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 40 # memory stalls due to read write turnaround
system.ruby.dir_cntrl0.memBuffer.memArbWait 76 # memory stalls due to arbitration
system.ruby.dir_cntrl0.memBuffer.memBankCount | 232 7.90% 7.90% | 108 3.68% 11.58% | 64 2.18% 13.76% | 51 1.74% 15.50% | 26 0.89% 16.38% | 106 3.61% 19.99% | 20 0.68% 20.67% | 38 1.29% 21.97% | 16 0.54% 22.51% | 52 1.77% 24.28% | 138 4.70% 28.99% | 48 1.63% 30.62% | 16 0.54% 31.16% | 70 2.38% 33.55% | 30 1.02% 34.57% | 220 7.49% 42.06% | 80 2.72% 44.79% | 60 2.04% 46.83% | 80 2.72% 49.56% | 118 4.02% 53.58% | 46 1.57% 55.14% | 52 1.77% 56.91% | 84 2.86% 59.78% | 180 6.13% 65.91% | 108 3.68% 69.58% | 74 2.52% 72.10% | 140 4.77% 76.87% | 112 3.81% 80.69% | 198 6.74% 87.43% | 261 8.89% 96.32% | 40 1.36% 97.68% | 68 2.32% 100.00% # Number of accesses per bank
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2936 # Number of accesses per bank
system.ruby.network.routers1.percent_links_utilized 5.971995
system.ruby.network.routers1.msg_count.Control::2 1470
system.ruby.network.routers1.msg_count.Data::2 1466
system.ruby.network.routers1.msg_count.Response_Data::4 1470
system.ruby.network.routers1.msg_count.Writeback_Control::3 1466
system.ruby.network.routers1.msg_bytes.Control::2 11760
system.ruby.network.routers1.msg_bytes.Data::2 105552
system.ruby.network.routers1.msg_bytes.Response_Data::4 105840
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728
system.ruby.network.routers2.percent_links_utilized 5.971995
system.ruby.network.routers2.msg_count.Control::2 1470
system.ruby.network.routers2.msg_count.Data::2 1466
system.ruby.network.routers2.msg_count.Response_Data::4 1470
system.ruby.network.routers2.msg_count.Writeback_Control::3 1466
system.ruby.network.routers2.msg_bytes.Control::2 11760
system.ruby.network.routers2.msg_bytes.Data::2 105552
system.ruby.network.routers2.msg_bytes.Response_Data::4 105840
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728
system.ruby.network.msg_count.Control 4410
system.ruby.network.msg_count.Data 4398
system.ruby.network.msg_count.Response_Data 4410
system.ruby.network.msg_count.Writeback_Control 4398
system.ruby.network.msg_byte.Control 35280
system.ruby.network.msg_byte.Data 316656
system.ruby.network.msg_byte.Response_Data 317520
system.ruby.network.msg_byte.Writeback_Control 35184
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@ -122,182 +122,182 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 125334 # number of cpu cycles simulated
system.cpu.workload.num_syscalls 7 # Number of system calls
system.cpu.numCycles 122907 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5814 # Number of instructions committed
system.cpu.committedOps 5814 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses
system.cpu.committedInsts 5624 # Number of instructions committed
system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 194 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls
system.cpu.num_int_insts 5113 # number of integer instructions
system.cpu.num_func_calls 190 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
system.cpu.num_int_insts 4944 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_int_register_reads 7284 # number of times the integer registers were read
system.cpu.num_int_register_writes 3397 # number of times the integer registers were written
system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2089 # number of memory refs
system.cpu.num_load_insts 1163 # Number of load instructions
system.cpu.num_store_insts 926 # Number of store instructions
system.cpu.num_mem_refs 2034 # number of memory refs
system.cpu.num_load_insts 1132 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 125334 # Number of busy cycles
system.cpu.num_busy_cycles 122907 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 915 # Number of branches fetched
system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction
system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction
system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction
system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction
system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction
system.cpu.Branches 883 # Number of branches fetched
system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5815 # Class of executed instruction
system.ruby.network.routers0.throttle0.link_utilization 5.954490
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1493
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1489
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 107496
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11912
system.ruby.network.routers0.throttle1.link_utilization 5.941724
system.ruby.network.routers0.throttle1.msg_count.Control::2 1493
system.ruby.network.routers0.throttle1.msg_count.Data::2 1489
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11944
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 107208
system.ruby.network.routers1.throttle0.link_utilization 5.941724
system.ruby.network.routers1.throttle0.msg_count.Control::2 1493
system.ruby.network.routers1.throttle0.msg_count.Data::2 1489
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11944
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 107208
system.ruby.network.routers1.throttle1.link_utilization 5.954490
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1493
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1489
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 107496
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11912
system.ruby.network.routers2.throttle0.link_utilization 5.954490
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1493
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1489
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 107496
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11912
system.ruby.network.routers2.throttle1.link_utilization 5.941724
system.ruby.network.routers2.throttle1.msg_count.Control::2 1493
system.ruby.network.routers2.throttle1.msg_count.Data::2 1489
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11944
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 107208
system.cpu.op_class::total 5625 # Class of executed instruction
system.ruby.network.routers0.throttle0.link_utilization 5.978504
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728
system.ruby.network.routers0.throttle1.link_utilization 5.965486
system.ruby.network.routers0.throttle1.msg_count.Control::2 1470
system.ruby.network.routers0.throttle1.msg_count.Data::2 1466
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552
system.ruby.network.routers1.throttle0.link_utilization 5.965486
system.ruby.network.routers1.throttle0.msg_count.Control::2 1470
system.ruby.network.routers1.throttle0.msg_count.Data::2 1466
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552
system.ruby.network.routers1.throttle1.link_utilization 5.978504
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728
system.ruby.network.routers2.throttle0.link_utilization 5.978504
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728
system.ruby.network.routers2.throttle1.link_utilization 5.965486
system.ruby.network.routers2.throttle1.msg_count.Control::2 1470
system.ruby.network.routers2.throttle1.msg_count.Data::2 1466
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105552
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 1493 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 1493 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 1493 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 1470 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 1470 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 1470 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 1489 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 1489 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 1489 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2
system.ruby.LD.latency_hist::bucket_size 16
system.ruby.LD.latency_hist::max_bucket 159
system.ruby.LD.latency_hist::samples 1163
system.ruby.LD.latency_hist::mean 39.248495
system.ruby.LD.latency_hist::gmean 17.996261
system.ruby.LD.latency_hist::stdev 30.948505
system.ruby.LD.latency_hist | 486 41.79% 41.79% | 0 0.00% 41.79% | 0 0.00% 41.79% | 147 12.64% 54.43% | 509 43.77% 98.19% | 19 1.63% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist::total 1163
system.ruby.LD.latency_hist::samples 1132
system.ruby.LD.latency_hist::mean 39.690813
system.ruby.LD.latency_hist::gmean 18.392553
system.ruby.LD.latency_hist::stdev 30.890580
system.ruby.LD.latency_hist | 465 41.08% 41.08% | 0 0.00% 41.08% | 0 0.00% 41.08% | 147 12.99% 54.06% | 497 43.90% 97.97% | 22 1.94% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist::total 1132
system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
system.ruby.LD.hit_latency_hist::samples 486
system.ruby.LD.hit_latency_hist::samples 465
system.ruby.LD.hit_latency_hist::mean 3
system.ruby.LD.hit_latency_hist::gmean 3.000000
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 486 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist::total 486
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist::total 465
system.ruby.LD.miss_latency_hist::bucket_size 16
system.ruby.LD.miss_latency_hist::max_bucket 159
system.ruby.LD.miss_latency_hist::samples 677
system.ruby.LD.miss_latency_hist::mean 65.270310
system.ruby.LD.miss_latency_hist::gmean 65.122528
system.ruby.LD.miss_latency_hist::stdev 4.861017
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 21.71% 21.71% | 509 75.18% 96.90% | 19 2.81% 99.70% | 2 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist::total 677
system.ruby.LD.miss_latency_hist::samples 667
system.ruby.LD.miss_latency_hist::mean 65.269865
system.ruby.LD.miss_latency_hist::gmean 65.112332
system.ruby.LD.miss_latency_hist::stdev 5.027167
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 22.04% 22.04% | 497 74.51% 96.55% | 22 3.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist::total 667
system.ruby.ST.latency_hist::bucket_size 16
system.ruby.ST.latency_hist::max_bucket 159
system.ruby.ST.latency_hist::samples 925
system.ruby.ST.latency_hist::mean 17.897297
system.ruby.ST.latency_hist::gmean 6.243616
system.ruby.ST.latency_hist::stdev 26.860092
system.ruby.ST.latency_hist | 705 76.22% 76.22% | 0 0.00% 76.22% | 0 0.00% 76.22% | 49 5.30% 81.51% | 158 17.08% 98.59% | 13 1.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist::total 925
system.ruby.ST.latency_hist::samples 901
system.ruby.ST.latency_hist::mean 18.103219
system.ruby.ST.latency_hist::gmean 6.303338
system.ruby.ST.latency_hist::stdev 27.010521
system.ruby.ST.latency_hist | 684 75.92% 75.92% | 0 0.00% 75.92% | 0 0.00% 75.92% | 46 5.11% 81.02% | 158 17.54% 98.56% | 13 1.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist::total 901
system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
system.ruby.ST.hit_latency_hist::samples 705
system.ruby.ST.hit_latency_hist::samples 684
system.ruby.ST.hit_latency_hist::mean 3
system.ruby.ST.hit_latency_hist::gmean 3.000000
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 705 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist::total 705
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist::total 684
system.ruby.ST.miss_latency_hist::bucket_size 16
system.ruby.ST.miss_latency_hist::max_bucket 159
system.ruby.ST.miss_latency_hist::samples 220
system.ruby.ST.miss_latency_hist::mean 65.636364
system.ruby.ST.miss_latency_hist::gmean 65.386932
system.ruby.ST.miss_latency_hist::stdev 6.334983
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 49 22.27% 22.27% | 158 71.82% 94.09% | 13 5.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist::total 220
system.ruby.ST.miss_latency_hist::samples 217
system.ruby.ST.miss_latency_hist::mean 65.709677
system.ruby.ST.miss_latency_hist::gmean 65.456791
system.ruby.ST.miss_latency_hist::stdev 6.376574
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 46 21.20% 21.20% | 158 72.81% 94.01% | 13 5.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist::total 217
system.ruby.IFETCH.latency_hist::bucket_size 16
system.ruby.IFETCH.latency_hist::max_bucket 159
system.ruby.IFETCH.latency_hist::samples 5815
system.ruby.IFETCH.latency_hist::mean 9.497850
system.ruby.IFETCH.latency_hist::gmean 4.118767
system.ruby.IFETCH.latency_hist::stdev 19.364276
system.ruby.IFETCH.latency_hist | 5219 89.75% 89.75% | 0 0.00% 89.75% | 0 0.00% 89.75% | 132 2.27% 92.02% | 421 7.24% 99.26% | 42 0.72% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist::total 5815
system.ruby.IFETCH.latency_hist::samples 5625
system.ruby.IFETCH.latency_hist::mean 9.601422
system.ruby.IFETCH.latency_hist::gmean 4.140083
system.ruby.IFETCH.latency_hist::stdev 19.494566
system.ruby.IFETCH.latency_hist | 5039 89.58% 89.58% | 0 0.00% 89.58% | 0 0.00% 89.58% | 137 2.44% 92.02% | 406 7.22% 99.24% | 42 0.75% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist::total 5625
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
system.ruby.IFETCH.hit_latency_hist::samples 5219
system.ruby.IFETCH.hit_latency_hist::samples 5039
system.ruby.IFETCH.hit_latency_hist::mean 3
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5219 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist::total 5219
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist::total 5039
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
system.ruby.IFETCH.miss_latency_hist::samples 596
system.ruby.IFETCH.miss_latency_hist::mean 66.397651
system.ruby.IFETCH.miss_latency_hist::gmean 66.083596
system.ruby.IFETCH.miss_latency_hist::stdev 7.118063
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 132 22.15% 22.15% | 421 70.64% 92.79% | 42 7.05% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist::total 596
system.ruby.IFETCH.miss_latency_hist::samples 586
system.ruby.IFETCH.miss_latency_hist::mean 66.366894
system.ruby.IFETCH.miss_latency_hist::gmean 66.054272
system.ruby.IFETCH.miss_latency_hist::stdev 7.096661
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 137 23.38% 23.38% | 406 69.28% 92.66% | 42 7.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist::total 586
system.ruby.Directory.miss_mach_latency_hist::bucket_size 16
system.ruby.Directory.miss_mach_latency_hist::max_bucket 159
system.ruby.Directory.miss_mach_latency_hist::samples 1493
system.ruby.Directory.miss_mach_latency_hist::mean 65.774280
system.ruby.Directory.miss_mach_latency_hist::gmean 65.543617
system.ruby.Directory.miss_mach_latency_hist::stdev 6.088981
system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 328 21.97% 21.97% | 1088 72.87% 94.84% | 74 4.96% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist::total 1493
system.ruby.Directory.miss_mach_latency_hist::samples 1470
system.ruby.Directory.miss_mach_latency_hist::mean 65.772109
system.ruby.Directory.miss_mach_latency_hist::gmean 65.537231
system.ruby.Directory.miss_mach_latency_hist::stdev 6.143987
system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 330 22.45% 22.45% | 1061 72.18% 94.63% | 77 5.24% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist::total 1470
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1
@ -326,51 +326,51 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion |
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 677
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 65.270310
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.122528
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 4.861017
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 21.71% 21.71% | 509 75.18% 96.90% | 19 2.81% 99.70% | 2 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 677
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 65.269865
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.112332
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 5.027167
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 22.04% 22.04% | 497 74.51% 96.55% | 22 3.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 220
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.636364
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 65.386932
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 6.334983
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 49 22.27% 22.27% | 158 71.82% 94.09% | 13 5.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 220
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.709677
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 65.456791
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 6.376574
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 46 21.20% 21.20% | 158 72.81% 94.01% | 13 5.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 596
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.397651
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 66.083596
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 7.118063
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 132 22.15% 22.15% | 421 70.64% 92.79% | 42 7.05% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 596
system.ruby.L1Cache_Controller.Load 1163 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 5815 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 925 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 1493 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 1489 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 1489 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 677 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 596 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 220 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 486 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 5219 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 705 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 1489 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1489 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1273 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 220 0.00% 0.00%
system.ruby.Directory_Controller.GETX 1493 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 1489 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1493 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 1489 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 1493 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 1489 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 1493 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 1489 0.00% 0.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.366894
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 66.054272
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 7.096661
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 137 23.38% 23.38% | 406 69.28% 92.66% | 42 7.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586
system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 901 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 1470 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 667 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 586 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 217 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 465 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 5039 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 684 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1253 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00%
system.ruby.Directory_Controller.GETX 1470 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00%
---------- End Simulation Statistics ----------

642
tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
View file

@ -1,56 +1,56 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000032 # Number of seconds simulated
sim_ticks 31633000 # Number of ticks simulated
final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000031 # Number of seconds simulated
sim_ticks 30902000 # Number of ticks simulated
final_tick 30902000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 442331 # Simulator instruction rate (inst/s)
host_op_rate 441894 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2401898254 # Simulator tick rate (ticks/s)
host_mem_usage 285092 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
host_inst_rate 104539 # Simulator instruction rate (inst/s)
host_op_rate 104503 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 574021463 # Simulator tick rate (ticks/s)
host_mem_usage 276192 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
system.physmem.bytes_read::total 28096 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 439 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 608984289 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 279202099 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 888186388 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 608984289 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 608984289 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 388 # Transaction distribution
system.membus.trans_dist::ReadResp 388 # Transaction distribution
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes)
system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory
system.physmem.bytes_read::total 27520 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory
system.physmem.num_reads::total 430 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 606821565 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 283735681 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 890557245 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 606821565 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 606821565 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 606821565 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 283735681 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 890557245 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 380 # Transaction distribution
system.membus.trans_dist::ReadResp 380 # Transaction distribution
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 439 # Request fanout histogram
system.membus.snoop_fanout::samples 430 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 439 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 439 # Request fanout histogram
system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 430 # Request fanout histogram
system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 3870000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 12.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
@ -71,116 +71,116 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 63266 # number of cpu cycles simulated
system.cpu.workload.num_syscalls 7 # Number of system calls
system.cpu.numCycles 61804 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5814 # Number of instructions committed
system.cpu.committedOps 5814 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses
system.cpu.committedInsts 5624 # Number of instructions committed
system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 194 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls
system.cpu.num_int_insts 5113 # number of integer instructions
system.cpu.num_func_calls 190 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
system.cpu.num_int_insts 4944 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_int_register_reads 7284 # number of times the integer registers were read
system.cpu.num_int_register_writes 3397 # number of times the integer registers were written
system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2089 # number of memory refs
system.cpu.num_load_insts 1163 # Number of load instructions
system.cpu.num_store_insts 926 # Number of store instructions
system.cpu.num_mem_refs 2034 # number of memory refs
system.cpu.num_load_insts 1132 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 63266 # Number of busy cycles
system.cpu.num_busy_cycles 61804 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 915 # Number of branches fetched
system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction
system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction
system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction
system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction
system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction
system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction
system.cpu.Branches 883 # Number of branches fetched
system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5815 # Class of executed instruction
system.cpu.op_class::total 5625 # Class of executed instruction
system.cpu.icache.tags.replacements 13 # number of replacements
system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 129.108186 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.141602 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11935 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11935 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5513 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5513 # number of overall hits
system.cpu.icache.overall_hits::total 5513 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses
system.cpu.icache.overall_misses::total 303 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16581000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16581000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16581000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16581000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16581000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16581000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5816 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5816 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5816 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052098 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.052098 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.052098 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54722.772277 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54722.772277 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54722.772277 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54722.772277 # average overall miss latency
system.cpu.icache.tags.occ_blocks::cpu.inst 129.108186 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.063041 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.063041 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11547 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 5331 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5331 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5331 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5331 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5331 # number of overall hits
system.cpu.icache.overall_hits::total 5331 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses
system.cpu.icache.overall_misses::total 295 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16141000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16141000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16141000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16141000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16141000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052435 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.052435 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54715.254237 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54715.254237 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54715.254237 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54715.254237 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -189,98 +189,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052098 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.052098 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.052098 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15551000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 15551000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15551000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 15551000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15551000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15551000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52715.254237 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52715.254237 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 183.724070 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.005263 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011841 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3967 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3967 # Number of data accesses
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
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system.cpu.l2cache.tags.tag_accesses 3886 # Number of tag accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
@ -300,39 +300,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses
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@ -346,60 +346,60 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000
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system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
@ -418,28 +418,28 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2650000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2650000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7261000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7261000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7261000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7261000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
@ -449,33 +449,33 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.trans_dist::ReadReq 382 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 864 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 432 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 216000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
---------- End Simulation Statistics ----------

22
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
View file

@ -305,7 +305,7 @@ system.cpu.fetch.Insts 13500 # Nu
system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 865 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR
@ -511,13 +511,13 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 11593 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.499612 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.370164 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 11592 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.499655 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.370216 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 9440 81.43% 81.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 839 7.24% 88.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 524 4.52% 93.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 9439 81.43% 81.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 839 7.24% 88.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 524 4.52% 93.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle
@ -527,7 +527,7 @@ system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11593 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11592 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -575,8 +575,8 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% #
system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 21861 # The number of ROB reads
system.cpu.rob.rob_writes 21469 # The number of ROB writes
system.cpu.rob.rob_reads 21860 # The number of ROB reads
system.cpu.rob.rob_writes 21470 # The number of ROB writes
system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
@ -585,7 +585,7 @@ system.cpu.cpi 6.511740 # CP
system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads
system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 13743 # number of integer regfile reads
system.cpu.int_regfile_reads 13744 # number of integer regfile reads
system.cpu.int_regfile_writes 7176 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes

8
tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
View file

@ -94,10 +94,10 @@ system.cpu.num_fp_register_writes 2 # nu
system.cpu.num_mem_refs 2007 # number of memory refs
system.cpu.num_load_insts 961 # Number of load instructions
system.cpu.num_store_insts 1046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5793 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 5792.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1037 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 3784 65.32% 65.32% # Class of executed instruction

8
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -76,10 +76,10 @@ system.cpu.num_fp_register_writes 0 # nu
system.cpu.num_mem_refs 1401 # number of memory refs
system.cpu.num_load_insts 723 # Number of load instructions
system.cpu.num_store_insts 678 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5390 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1121 # Number of branches fetched
system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction

8
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
View file

@ -123,10 +123,10 @@ system.cpu.num_fp_register_writes 0 # nu
system.cpu.num_mem_refs 1401 # number of memory refs
system.cpu.num_load_insts 723 # Number of load instructions
system.cpu.num_store_insts 678 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 107952 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.999991 # Number of idle cycles
system.cpu.num_busy_cycles 107951.000009 # Number of busy cycles
system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000009 # Percentage of idle cycles
system.cpu.Branches 1121 # Number of branches fetched
system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction

8
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
View file

@ -72,10 +72,10 @@ system.cpu.num_fp_register_writes 0 # nu
system.cpu.num_mem_refs 1401 # number of memory refs
system.cpu.num_load_insts 723 # Number of load instructions
system.cpu.num_store_insts 678 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 55600 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 55599.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1121 # Number of branches fetched
system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction

18
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
View file

@ -288,7 +288,7 @@ system.cpu.fetch.Insts 15528 # Nu
system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1202 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 1203 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
@ -491,11 +491,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 19925 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.489184 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.394250 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 19924 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.489209 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.394281 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 16685 83.74% 83.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 16684 83.74% 83.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1003 5.03% 88.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 547 2.75% 91.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 737 3.70% 95.22% # Number of insts commited each cycle
@ -507,7 +507,7 @@ system.cpu.commit.committed_per_cycle::8 260 1.30% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 19925 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 19924 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5380 # Number of instructions committed
system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -555,8 +555,8 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% #
system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 41132 # The number of ROB reads
system.cpu.rob.rob_writes 44928 # The number of ROB writes
system.cpu.rob.rob_reads 41131 # The number of ROB reads
system.cpu.rob.rob_writes 44929 # The number of ROB writes
system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5380 # Number of Instructions Simulated
@ -565,7 +565,7 @@ system.cpu.cpi 7.315428 # CP
system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads
system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 21340 # number of integer regfile reads
system.cpu.int_regfile_reads 21341 # number of integer regfile reads
system.cpu.int_regfile_writes 13120 # number of integer regfile writes
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
system.cpu.cc_regfile_reads 8069 # number of cc regfile reads

8
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
View file

@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes 3536 # nu
system.cpu.num_mem_refs 1988 # number of memory refs
system.cpu.num_load_insts 1053 # Number of load instructions
system.cpu.num_store_insts 935 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 11231 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 11230.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1208 # Number of branches fetched
system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction
system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction

14
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
View file

@ -21,11 +21,11 @@ system.ruby.delayHist | 2750 100.00% 100.00% |
system.ruby.delayHist::total 2750 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
system.ruby.outstanding_req_hist::samples 8853
system.ruby.outstanding_req_hist::samples 8852
system.ruby.outstanding_req_hist::mean 1
system.ruby.outstanding_req_hist::gmean 1
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8853 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist::total 8853
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist::total 8852
system.ruby.latency_hist::bucket_size 16
system.ruby.latency_hist::max_bucket 159
system.ruby.latency_hist::samples 8852
@ -126,10 +126,10 @@ system.cpu.num_cc_register_writes 3536 # nu
system.cpu.num_mem_refs 1988 # number of memory refs
system.cpu.num_load_insts 1053 # Number of load instructions
system.cpu.num_store_insts 935 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 121759 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.999992 # Number of idle cycles
system.cpu.num_busy_cycles 121758.000008 # Number of busy cycles
system.cpu.not_idle_fraction 0.999992 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000008 # Percentage of idle cycles
system.cpu.Branches 1208 # Number of branches fetched
system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction
system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction

64
tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
View file

@ -77,10 +77,10 @@ system.cpu.num_cc_register_writes 3536 # nu
system.cpu.num_mem_refs 1988 # number of memory refs
system.cpu.num_load_insts 1053 # Number of load instructions
system.cpu.num_store_insts 935 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 56716 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 56715.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1208 # Number of branches fetched
system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction
system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction
@ -119,9 +119,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu.op_class::total 9748 # Class of executed instruction
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks.
system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy
@ -130,14 +130,14 @@ system.cpu.icache.tags.occ_task_id_blocks::1024 228
system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 13958 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13958 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits
system.cpu.icache.overall_hits::total 6637 # number of overall hits
system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13956 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits
system.cpu.icache.overall_hits::total 6636 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
@ -150,18 +150,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 12498000
system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
@ -188,12 +188,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000
system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency

2
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
View file

@ -745,7 +745,7 @@ system.cpu.cpi_total 3.619272 # CP
system.cpu.ipc::0 0.138149 # IPC: Instructions Per Cycle
system.cpu.ipc::1 0.138149 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.276299 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 26323 # number of integer regfile reads
system.cpu.int_regfile_reads 26325 # number of integer regfile reads
system.cpu.int_regfile_writes 14897 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes

6
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
View file

@ -287,7 +287,7 @@ system.cpu.fetch.Insts 40300 # Nu
system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 16187 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2310 # Number of cycles fetch has spent squashing
system.cpu.fetch.SquashCycles 2311 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1000 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
@ -553,7 +553,7 @@ system.cpu.commit.op_class_0::total 15162 # Cl
system.cpu.commit.bw_lim_events 273 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 54809 # The number of ROB reads
system.cpu.rob.rob_writes 52996 # The number of ROB writes
system.cpu.rob.rob_writes 52997 # The number of ROB writes
system.cpu.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 19379 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
@ -562,7 +562,7 @@ system.cpu.cpi 3.594417 # CP
system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads
system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 33400 # number of integer regfile reads
system.cpu.int_regfile_reads 33401 # number of integer regfile reads
system.cpu.int_regfile_writes 18599 # number of integer regfile writes
system.cpu.misc_regfile_reads 7136 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes

8
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -80,10 +80,10 @@ system.cpu.num_fp_register_writes 0 # nu
system.cpu.num_mem_refs 3683 # number of memory refs
system.cpu.num_load_insts 2231 # Number of load instructions
system.cpu.num_store_insts 1452 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 15225 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 15224.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 3363 # Number of branches fetched
system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction
system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction

8
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
View file

@ -72,10 +72,10 @@ system.cpu.num_fp_register_writes 0 # nu
system.cpu.num_mem_refs 3683 # number of memory refs
system.cpu.num_load_insts 2231 # Number of load instructions
system.cpu.num_store_insts 1452 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 82736 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 82735.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 3363 # Number of branches fetched
system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction
system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction

6
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
View file

@ -792,7 +792,7 @@ system.cpu0.fetch.Insts 481063 # Nu
system.cpu0.fetch.Branches 81418 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 76128 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 164143 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2674 # Number of cycles fetch has spent squashing
system.cpu0.fetch.SquashCycles 2675 # Number of cycles fetch has spent squashing
system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 1880 # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines 7123 # Number of cache lines fetched
@ -1058,7 +1058,7 @@ system.cpu0.commit.op_class_0::total 449934 # Cl
system.cpu0.commit.bw_lim_events 488 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 646710 # The number of ROB reads
system.cpu0.rob.rob_writes 929756 # The number of ROB writes
system.cpu0.rob.rob_writes 929757 # The number of ROB writes
system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 23966 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts 377666 # Number of Instructions Simulated
@ -1067,7 +1067,7 @@ system.cpu0.cpi 0.559735 # CP
system.cpu0.cpi_total 0.559735 # CPI: Total CPI of All Threads
system.cpu0.ipc 1.786559 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 1.786559 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 689341 # number of integer regfile reads
system.cpu0.int_regfile_reads 689346 # number of integer regfile reads
system.cpu0.int_regfile_writes 310987 # number of integer regfile writes
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
system.cpu0.misc_regfile_reads 224004 # number of misc regfile reads

8
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
View file

@ -327,10 +327,10 @@ system.cpu0.num_fp_register_writes 0 # nu
system.cpu0.num_mem_refs 82397 # number of memory refs
system.cpu0.num_load_insts 54591 # Number of load instructions
system.cpu0.num_store_insts 27806 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
system.cpu0.num_busy_cycles 175415 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles
system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu0.Branches 29689 # Number of branches fetched
system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction
system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction

8
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
View file

@ -579,10 +579,10 @@ system.cpu0.num_fp_register_writes 0 # nu
system.cpu0.num_mem_refs 74021 # number of memory refs
system.cpu0.num_load_insts 49007 # Number of load instructions
system.cpu0.num_store_insts 25014 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
system.cpu0.num_busy_cycles 525587 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu0.num_busy_cycles 525586.998000 # Number of busy cycles
system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu0.Branches 26897 # Number of branches fetched
system.cpu0.op_class::No_OpClass 23624 14.89% 14.89% # Class of executed instruction
system.cpu0.op_class::IntAlu 60907 38.39% 53.29% # Class of executed instruction