610 lines
68 KiB
Plaintext
610 lines
68 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.707539 # Number of seconds simulated
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sim_ticks 707539023000 # Number of ticks simulated
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final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1199909 # Simulator instruction rate (inst/s)
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host_op_rate 1299448 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1681197618 # Simulator tick rate (ticks/s)
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host_mem_usage 309428 # Number of bytes of host memory used
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host_seconds 420.85 # Real time elapsed on the host
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sim_insts 504986853 # Number of instructions simulated
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sim_ops 546878104 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory
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system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 139879 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s)
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system.membus.trans_dist::ReadReq 41855 # Transaction distribution
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system.membus.trans_dist::ReadResp 41855 # Transaction distribution
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system.membus.trans_dist::Writeback 95953 # Transaction distribution
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system.membus.trans_dist::ReadExReq 100794 # Transaction distribution
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system.membus.trans_dist::ReadExResp 100794 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::samples 238603 # Request fanout histogram
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system.membus.snoop_fanout::mean 0 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 0 # Request fanout histogram
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system.membus.snoop_fanout::max_value 0 # Request fanout histogram
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system.membus.snoop_fanout::total 238603 # Request fanout histogram
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system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 548 # Number of system calls
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system.cpu.numCycles 1415078046 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 504986853 # Number of instructions committed
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system.cpu.committedOps 546878104 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
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system.cpu.num_func_calls 19311615 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls
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system.cpu.num_int_insts 448454356 # number of integer instructions
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system.cpu.num_fp_insts 16 # number of float instructions
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system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read
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system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_cc_register_reads 1984297856 # number of times the CC registers were read
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system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written
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system.cpu.num_mem_refs 172745235 # number of memory refs
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system.cpu.num_load_insts 115884756 # Number of load instructions
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system.cpu.num_store_insts 56860479 # Number of store instructions
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system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
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system.cpu.num_busy_cycles 1415078045.998000 # Number of busy cycles
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system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
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system.cpu.Branches 121548301 # Number of branches fetched
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system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
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system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction
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system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
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system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction
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system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 548695378 # Class of executed instruction
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system.cpu.icache.tags.replacements 9788 # number of replacements
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system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
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system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
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system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses
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system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses
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system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits
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system.cpu.icache.overall_hits::total 516599855 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
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system.cpu.icache.overall_misses::total 11521 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 109895 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008786 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109085 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3656 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27181 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 18220084 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 18220084 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1064905 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1064905 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 255466 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 255466 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 8751 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 999039 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1007790 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 8751 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 999039 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1007790 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2770 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 39085 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 41855 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 100794 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 100794 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2770 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 139879 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 142649 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 142649 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1064905 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1064905 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.240431 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.049939 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.052702 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282923 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.282923 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.240431 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.122817 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.123995 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 95953 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 95953 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2770 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39085 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 41855 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100794 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 100794 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2770 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 139879 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 142649 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1134822 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 167203374 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1064905 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|