stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
This commit is contained in:
Steve Reinhardt
parent
1249728494
commit
9e45ada171
183 changed files with 11250 additions and 11202 deletions
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@ -353,7 +353,7 @@ type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=gzip input.log 1
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cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
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cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
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egid=100
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env=
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errout=cerr
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@ -1,2 +1,5 @@
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warn: Sockets disabled, not accepting gdb connections
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For more information see: http://www.m5sim.org/warn/d946bea6
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warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
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For more information see: http://www.m5sim.org/warn/5c5b547f
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hack: be nice to actually delete the event here
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@ -1,5 +1,5 @@
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Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simout
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Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simerr
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Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout
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Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr
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M5 Simulator System
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Copyright (c) 2001-2008
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@ -7,11 +7,11 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Jun 6 2010 03:04:38
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M5 revision ba1a0193c050 7448 default tip
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M5 started Jun 6 2010 03:24:00
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M5 compiled Aug 26 2010 11:51:59
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M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
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M5 started Aug 26 2010 11:52:05
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M5 executing on zizzer
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
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command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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@ -46,3 +46,4 @@ Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Exiting @ tick 169506496500 because target called exit()
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@ -1,340 +1,340 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 217525 # Simulator instruction rate (inst/s)
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host_mem_usage 207124 # Number of bytes of host memory used
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host_seconds 2599.94 # Real time elapsed on the host
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host_tick_rate 64460403 # Simulator tick rate (ticks/s)
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host_inst_rate 178555 # Simulator instruction rate (inst/s)
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host_mem_usage 207544 # Number of bytes of host memory used
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host_seconds 3167.39 # Real time elapsed on the host
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host_tick_rate 53516139 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 565552443 # Number of instructions simulated
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sim_seconds 0.167593 # Number of seconds simulated
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sim_ticks 167593085500 # Number of ticks simulated
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sim_seconds 0.169506 # Number of seconds simulated
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sim_ticks 169506496500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 63922842 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 71487962 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 180 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 4121924 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 70504427 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 76440051 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1674270 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.BTBHits 64068954 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 71556079 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 4120910 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 70589657 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 76519042 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1672225 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 62547159 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 18448626 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_lim_events 19702213 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 323575021 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.860023 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 2.297815 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::samples 327417755 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.838193 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 2.277454 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 107931872 33.36% 33.36% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 101513205 31.37% 64.73% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 37265964 11.52% 76.25% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 10166735 3.14% 79.39% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 11290718 3.49% 82.88% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 21721468 6.71% 89.59% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 12702626 3.93% 93.52% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 2533807 0.78% 94.30% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 18448626 5.70% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 105871733 32.34% 32.34% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 108541066 33.15% 65.49% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 36996526 11.30% 76.79% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 11988281 3.66% 80.45% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 10398233 3.18% 83.62% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 21777635 6.65% 90.27% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 9735285 2.97% 93.25% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 2406783 0.74% 93.98% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 19702213 6.02% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 323575021 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 327417755 # Number of insts commited each cycle
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system.cpu.commit.COM:count 601856963 # Number of instructions committed
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system.cpu.commit.COM:loads 115049510 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 154862033 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 4121096 # The number of times a branch was mispredicted
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system.cpu.commit.branchMispredicts 4120073 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 61591802 # The number of squashed insts skipped by commit
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system.cpu.commit.commitSquashedInsts 63088611 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 565552443 # Number of Instructions Simulated
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system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
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system.cpu.cpi 0.592670 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.592670 # CPI: Total CPI of All Threads
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system.cpu.cpi 0.599437 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.599437 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 113443216 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 19248.740390 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7746.370369 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 112634831 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 15560393000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.007126 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 808385 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 590181 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1690289000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001923 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 218204 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_accesses 116877204 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 19511.922037 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7693.277195 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 116024078 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 16646128000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.007299 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 853126 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 634854 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1679227000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001868 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 218272 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 32797.392555 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35638.802347 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 37116231 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 76584863381 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.059189 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 2335090 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1996724 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 12058958995 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.008577 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 338366 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 6528.414634 # average number of cycles each access was blocked
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system.cpu.dcache.WriteReq_avg_miss_latency 31935.176109 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34419.628617 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 37146976 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 73589663391 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.058410 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 2304345 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1968193 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 11570226999 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.008521 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 336152 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 7088.486726 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 21363.636364 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 316.462124 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 123 # number of cycles access was blocked
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system.cpu.dcache.avg_refs 323.627554 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 113 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 802995 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 800999 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 235000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 152894537 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 29313.182507 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 149751062 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 92145256381 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.020560 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 3143475 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2586905 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 13749247995 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003640 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 556570 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_accesses 156328525 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 28578.502032 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 153171054 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 90235791391 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.020198 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 3157471 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2603047 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 13249453999 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003547 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 554424 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999563 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4094.208277 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 152894537 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 29313.182507 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency
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system.cpu.dcache.occ_%::0 0.999568 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4094.232018 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 156328525 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 28578.502032 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 149751062 # number of overall hits
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system.cpu.dcache.overall_miss_latency 92145256381 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.020560 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 3143475 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2586905 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 13749247995 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003640 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 556570 # number of overall MSHR misses
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system.cpu.dcache.overall_hits 153171054 # number of overall hits
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system.cpu.dcache.overall_miss_latency 90235791391 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.020198 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 3157471 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2603047 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 13249453999 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003547 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 554424 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 470982 # number of replacements
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system.cpu.dcache.sampled_refs 475078 # Sample count of references to valid blocks.
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system.cpu.dcache.replacements 471007 # number of replacements
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system.cpu.dcache.sampled_refs 475103 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.208277 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 150344193 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126612000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 335213 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 51119249 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 861 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 4177292 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 689843810 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 144051375 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 122990983 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 9853353 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 3386 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 5413414 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 163070578 # DTB accesses
|
||||
system.cpu.dcache.tagsinuse 4094.232018 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 153756422 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126427000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 336082 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 53096224 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 870 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 4174977 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 691367918 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 145684312 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 123209609 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 10007520 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 3007 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 5427610 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 163170180 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 163012019 # DTB hits
|
||||
system.cpu.dtb.data_misses 58559 # DTB misses
|
||||
system.cpu.dtb.data_hits 163108618 # DTB hits
|
||||
system.cpu.dtb.data_misses 61562 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 122259759 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 122378622 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 122237048 # DTB read hits
|
||||
system.cpu.dtb.read_misses 22711 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 40810819 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 122354151 # DTB read hits
|
||||
system.cpu.dtb.read_misses 24471 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 40791558 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 40774971 # DTB write hits
|
||||
system.cpu.dtb.write_misses 35848 # DTB write misses
|
||||
system.cpu.fetch.Branches 76440051 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 65631744 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 195845469 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1315609 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 699070033 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 4181068 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.228053 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 65631744 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 65597112 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.085617 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 333428374 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.096612 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.077342 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dtb.write_hits 40754467 # DTB write hits
|
||||
system.cpu.dtb.write_misses 37091 # DTB write misses
|
||||
system.cpu.fetch.Branches 76519042 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 65743933 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 196171036 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1323544 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 700543147 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 4180854 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.225711 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 65743933 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 65741179 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.066420 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 337425275 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.076143 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.069329 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 203214688 60.95% 60.95% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 10311898 3.09% 64.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 15894466 4.77% 68.81% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 13958250 4.19% 72.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 12033268 3.61% 76.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 13973782 4.19% 80.79% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 5916300 1.77% 82.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3411105 1.02% 83.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 54714617 16.41% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 206998212 61.35% 61.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 10205574 3.02% 64.37% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 16013127 4.75% 69.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 13976667 4.14% 73.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 12062274 3.57% 76.83% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 13987466 4.15% 80.98% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 5886424 1.74% 82.72% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3487900 1.03% 83.76% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 54807631 16.24% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 333428374 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 65631744 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36217.817562 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35518.743109 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 65630571 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 42483500 # number of ReadReq miss cycles
|
||||
system.cpu.fetch.rateDist::total 337425275 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 65743933 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36198.392555 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35509.868421 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 65742751 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 42786500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1173 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 266 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32215500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 1182 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32385000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 912 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 72360.056229 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 72086.349781 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 65631744 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36217.817562 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35518.743109 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 65630571 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 42483500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 65743933 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36198.392555 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35509.868421 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 65742751 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 42786500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1173 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 266 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 32215500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 1182 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 32385000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 907 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 912 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.378038 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 774.221896 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 65631744 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36217.817562 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35518.743109 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.379446 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 777.105869 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 65743933 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36198.392555 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35509.868421 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 65630571 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 42483500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 65742751 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 42786500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1173 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 266 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 32215500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 1182 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 32385000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 907 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 912 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 35 # number of replacements
|
||||
system.cpu.icache.sampled_refs 907 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 36 # number of replacements
|
||||
system.cpu.icache.sampled_refs 912 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 774.221896 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 65630571 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 777.105869 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 65742751 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 1757798 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 67441684 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 43298534 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.787674 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 164010690 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 41206389 # Number of stores executed
|
||||
system.cpu.idleCycles 1587719 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 67446690 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 43287555 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.768234 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 164109637 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 41186586 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 488922033 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 596002683 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.810520 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 494218268 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 596241723 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.805354 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 396281024 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.778124 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 597106328 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4603784 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2069078 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 126900612 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 3145838 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 43054897 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 663551547 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 122804301 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6319339 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 599203767 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 4454 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 398020536 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.758758 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 597367655 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4601660 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2251946 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 127252956 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 3156398 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 43259984 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 665052109 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 122923051 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6371334 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 599454333 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 2449 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 32589 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 9853353 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 86305 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 33854 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 10007520 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 83713 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 194 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 8787843 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 12289 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 175 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 5470953 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 10609 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 89737 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5921 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 11851102 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 3242374 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 89737 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 943709 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 3660075 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.687279 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.687279 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 93535 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5935 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 12203446 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 3447461 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 93535 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 944573 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 3657087 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.668232 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.668232 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 438810493 72.47% 72.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 6669 0.00% 72.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 124770612 20.61% 93.07% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 41935289 6.93% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 438988101 72.46% 72.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 6710 0.00% 72.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 30 0.00% 72.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 124874272 20.61% 93.07% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 41956540 6.93% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 605523106 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 7132172 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011779 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 605825667 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 6927509 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011435 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 5335622 74.81% 74.81% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 49 0.00% 74.81% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 74.81% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 74.81% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 74.81% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 74.81% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 74.81% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 74.81% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 74.81% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 1469402 20.60% 95.41% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 327099 4.59% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 5320205 76.80% 76.80% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 51 0.00% 76.80% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 76.80% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 76.80% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 76.80% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 76.80% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 76.80% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 76.80% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 76.80% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 1245764 17.98% 94.78% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 361489 5.22% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 333428374 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.816052 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.661323 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 337425275 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.795437 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.663310 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 91844434 27.55% 27.55% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 66796624 20.03% 47.58% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 82026036 24.60% 72.18% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 37142853 11.14% 83.32% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 29318508 8.79% 92.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 13804488 4.14% 96.25% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 11015283 3.30% 99.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 983503 0.29% 99.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 496645 0.15% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 95395357 28.27% 28.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 68329461 20.25% 48.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 80056631 23.73% 72.25% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 36910615 10.94% 83.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 31840128 9.44% 92.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 12299933 3.65% 96.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 10951663 3.25% 99.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 1050952 0.31% 99.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 590535 0.18% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 333428374 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.806528 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 620252984 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 605523106 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 53278148 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 39411 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 29138505 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 337425275 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.787028 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 621764526 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 605825667 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 54809333 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 18475 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 31050369 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 65631783 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 65743973 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 65631744 # ITB hits
|
||||
system.cpu.itb.fetch_misses 39 # ITB misses
|
||||
system.cpu.itb.fetch_hits 65743933 # ITB hits
|
||||
system.cpu.itb.fetch_misses 40 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
|
|
@ -343,106 +343,107 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 256875 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.188321 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31137.765450 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 8801356500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 256875 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7998513500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 256875 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 219110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34284.038279 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31037.107304 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 183268 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1228808500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.163580 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 35842 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1112432000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.163580 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 35842 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 81505 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34131.924422 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31025.814367 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2781922500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 256831 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34267.808951 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31149.097625 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 12642 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 8367822000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.950777 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 244189 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7606267000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950777 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 244189 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 219184 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34300.593807 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31016.018663 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 183819 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1213040500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.161348 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 35365 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1096881500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.161348 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 35365 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 79334 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34139.271939 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31029.539668 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2708405000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 81505 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528759000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 79334 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2461697500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 81505 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 335213 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 335213 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5455.882353 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 79334 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 336082 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 336082 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5312.500000 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 3.750936 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 68 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 3.798768 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 371000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 382500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 475985 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34265.741313 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31125.440272 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 183268 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 10030165000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.614971 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 292717 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 476015 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34271.956402 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31132.262461 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 196461 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9580862500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.587280 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 279554 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9110945500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.614971 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 292717 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 8703148500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.587280 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 279554 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.051123 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.447698 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1675.210024 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14670.153699 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 475985 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34265.741313 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31125.440272 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.052597 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.448200 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1723.488326 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14686.601231 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 476015 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34271.956402 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31132.262461 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 183268 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 10030165000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.614971 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 292717 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 196461 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9580862500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.587280 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 279554 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9110945500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.614971 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 292717 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 8703148500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.587280 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 279554 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 85307 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 100934 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 84626 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 100342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16345.363723 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 378597 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 16410.089557 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 381176 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 63240 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 18950859 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 15231969 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 126900612 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 43054897 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 335186172 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 14808263 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.writebacks 62683 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 23861424 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 18454491 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 127252956 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 43259984 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 339012994 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 14846495 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 34154270 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 151775927 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 2034435 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 82 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 895748431 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 680023810 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 518612424 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 115460168 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 9853353 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 41529646 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 54757535 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 1017 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:IQFullEvents 36228613 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 153406470 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1884931 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 97 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 897942713 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 681539497 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 519842559 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 115704820 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 10007520 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 43459223 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 55987670 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 747 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 80752072 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 87364721 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 33 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 42487 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.timesIdled 36935 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -152,12 +152,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,2 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 24 2010 23:12:40
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 02:27:06
|
||||
M5 executing on SC2B0619
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 11:59:22
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -44,3 +46,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 777351681000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1555765 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 191800 # Number of bytes of host memory used
|
||||
host_seconds 386.86 # Real time elapsed on the host
|
||||
host_tick_rate 2011092592 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1386497 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 206712 # Number of bytes of host memory used
|
||||
host_seconds 434.08 # Real time elapsed on the host
|
||||
host_tick_rate 1790782589 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_seconds 0.778004 # Number of seconds simulated
|
||||
sim_ticks 778003833000 # Number of ticks simulated
|
||||
sim_seconds 0.777352 # Number of seconds simulated
|
||||
sim_ticks 777351681000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21007.583287 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18007.583287 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 4227398000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3623702000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 54405.858739 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51405.858739 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 39124493 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 17781358000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.008284 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 326828 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 16800874000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.008284 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 326828 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 41678.513805 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 38678.513805 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 153437303 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 22008756000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003430 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 528060 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 20424576000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.003430 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 528060 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999559 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4094.195523 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.999560 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4094.197079 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 41678.513805 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 38678.513805 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 153435240 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 530123 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 153437303 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 22008756000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003430 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 528060 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 20424576000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.003430 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 528060 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.197079 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 325723 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 578599000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 325740 # number of writebacks
|
||||
system.cpu.dtb.data_accesses 153970296 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 153965363 # DTB hits
|
||||
|
|
@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 795 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.328723 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 673.225223 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.328737 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 673.252668 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
|
|
@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 673.252668 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -164,36 +164,37 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 12405 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 12571416000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.951193 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 241758 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9670320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.951193 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 241758 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 167657 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1787240000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.170126 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 34370 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1374800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170126 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34370 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 72665 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3778580000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 72665 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2906600000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 72665 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 325740 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 325740 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 3.553777 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -202,44 +203,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 180062 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 14358656000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.605292 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 276128 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 11045120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.605292 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 276128 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.050771 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.447994 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1663.663316 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14679.879055 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.052155 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.448358 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1709.012624 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14691.802112 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 167236 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 288954 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 180062 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 14358656000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.605292 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 276128 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 11045120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.605292 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 276128 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 84513 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 83906 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 99616 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 16400.814735 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 354013 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 63194 # number of writebacks
|
||||
system.cpu.l2cache.writebacks 62672 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1556007666 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1554703362 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 601856964 # Number of instructions executed
|
||||
system.cpu.num_refs 154866966 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
|
||||
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:44:30
|
||||
M5 compiled Aug 26 2010 13:52:30
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:54:54
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
|
||||
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -43,4 +45,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 808121048000 because target called exit()
|
||||
Exiting @ tick 807517408000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1674821 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210020 # Number of bytes of host memory used
|
||||
host_seconds 357.42 # Real time elapsed on the host
|
||||
host_tick_rate 2260963263 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1492183 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211112 # Number of bytes of host memory used
|
||||
host_seconds 401.17 # Real time elapsed on the host
|
||||
host_tick_rate 2012902303 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 598619824 # Number of instructions simulated
|
||||
sim_seconds 0.808121 # Number of seconds simulated
|
||||
sim_ticks 808121048000 # Number of ticks simulated
|
||||
sim_seconds 0.807517 # Number of seconds simulated
|
||||
sim_ticks 807517408000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21168.913260 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18168.913260 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21105.418688 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18105.418688 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4018770000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 4006716000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3449241000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3437187000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 69110224 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 17283504000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.004446 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 308634 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 16357602000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004446 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 308634 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 54322.323841 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51322.323841 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 69111608 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 16690534000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.004426 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 307250 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 15768784000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004426 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 307250 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 42734.717951 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 216713991 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 21302274000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002295 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 498477 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 41636.575047 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 216715375 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 20697250000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002289 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 497093 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 19806843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002295 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 498477 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 19205971000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002289 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 497093 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999571 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4094.243213 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.999572 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4094.246847 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 42734.717951 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 41636.575047 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 216713991 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 21302274000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002295 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 498477 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 216715375 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 20697250000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002289 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 497093 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 19806843000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002295 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 498477 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 19205971000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002289 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 497093 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 433495 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.243213 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.246847 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 537993000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 305427 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 305501 # number of writebacks
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 643 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.282040 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 577.617873 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.282055 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 577.648910 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
|
||||
|
|
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 12 # number of replacements
|
||||
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 577.617873 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 577.648910 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -150,36 +150,37 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 12882896000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 247748 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9909920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 247748 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 12273 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 12244700000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.950462 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 235475 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9419000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950462 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 235475 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 157466 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1717040000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.173346 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33020 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1320800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173346 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33020 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 60886 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_hits 157753 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1702116000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.171839 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 32733 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1309320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171839 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32733 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 59502 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3166072000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3094104000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 60886 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2435440000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 59502 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2380080000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 60886 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 305427 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 305427 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 59502 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 305501 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 305501 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 3.359132 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 3.379196 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 157466 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 14599936000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.640681 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 280768 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 170026 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 13946816000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.612020 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 268208 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 11230720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.640681 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 280768 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 10728320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.612020 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 268208 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.049205 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.452726 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1612.352730 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14834.915268 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.050080 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.453180 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1641.035711 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14849.786647 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 157466 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 14599936000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.640681 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 280768 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 170026 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 13946816000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.612020 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 268208 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 11230720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.640681 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 280768 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 10728320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.612020 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 268208 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 81265 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 96683 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 80841 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 96272 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16447.267999 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 324771 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 16490.822357 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 325322 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 61092 # number of writebacks
|
||||
system.cpu.l2cache.writebacks 60805 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1616242096 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1615034816 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 598619824 # Number of instructions executed
|
||||
system.cpu.num_refs 219174038 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -353,7 +353,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
|
||||
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Redirecting stdout to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simout
|
||||
Redirecting stderr to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simerr
|
||||
Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout
|
||||
Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jun 6 2010 04:01:36
|
||||
M5 revision ba1a0193c050 7448 default tip
|
||||
M5 started Jun 6 2010 04:02:01
|
||||
M5 compiled Aug 26 2010 13:03:41
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:05:09
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -45,4 +45,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 1088715493000 because target called exit()
|
||||
Exiting @ tick 1088441503500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,209 +1,209 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 109148 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 208820 # Number of bytes of host memory used
|
||||
host_seconds 12878.07 # Real time elapsed on the host
|
||||
host_tick_rate 84540245 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 76473 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212472 # Number of bytes of host memory used
|
||||
host_seconds 18380.70 # Real time elapsed on the host
|
||||
host_tick_rate 59216546 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1405618369 # Number of instructions simulated
|
||||
sim_seconds 1.088715 # Number of seconds simulated
|
||||
sim_ticks 1088715493000 # Number of ticks simulated
|
||||
sim_seconds 1.088442 # Number of seconds simulated
|
||||
sim_ticks 1088441503500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 173332559 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 194142411 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 173420048 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 194153919 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 81910123 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 251618660 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 251618660 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condIncorrect 81907161 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 251603669 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 251603669 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 86248929 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 8014877 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 8072747 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1942378796 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.766863 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.200662 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1941955406 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.767030 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.200667 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 1072972593 55.24% 55.24% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 568760584 29.28% 84.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 118179777 6.08% 90.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 122167717 6.29% 96.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 27965504 1.44% 98.34% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 8603273 0.44% 98.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 11084471 0.57% 99.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 4630000 0.24% 99.59% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 8014877 0.41% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 1072656731 55.24% 55.24% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 568585470 29.28% 84.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 118066725 6.08% 90.59% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 122346784 6.30% 96.89% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 28028862 1.44% 98.34% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 8610798 0.44% 98.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 11084197 0.57% 99.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 4503092 0.23% 99.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 8072747 0.42% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1942378796 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1941955406 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 1489537512 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 402517247 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 569375203 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 81910123 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 81907161 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1489537512 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 1349352602 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 1348785802 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1405618369 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1405618369 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.549091 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.549091 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 421562233 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14361.598866 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6977.217093 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 420657692 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 12990655000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 904541 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 666380 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1661701000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.cpi 1.548701 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.548701 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 421715823 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14253.643501 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6923.398779 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 420813257 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 12864854000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002140 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 902566 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 664404 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1648890500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000565 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 238161 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 238162 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 38025 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35025 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 1521000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 1401000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 38027.777778 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35027.777778 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 684500 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 630500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 37779.329951 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36098.948570 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 164660283 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 82976518000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.013163 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2196347 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1851198 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 12459516000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002069 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 345149 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 36526.139631 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35067.237452 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 164663038 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 80123447685 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.013147 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2193592 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1850133 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 12044158308 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002058 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 343459 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 1140.488307 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1140.778331 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 588418863 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 30948.287394 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 585317975 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 95967173000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005270 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 3100888 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 2517578 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 14121217000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000991 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 583310 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 588572453 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 30033.448450 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23542.906477 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 585476295 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 92988301685 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005260 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 3096158 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 2514537 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 13693048808 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000988 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 581621 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999896 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.574437 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 588418863 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 30948.287394 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_blocks::0 4095.574913 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 588572453 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 30033.448450 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23542.906477 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 585317975 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 95967173000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005270 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 3100888 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 2517578 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 14121217000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000991 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 583310 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 585476295 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 92988301685 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005260 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 3096158 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 2514537 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 13693048808 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000988 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 581621 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 509323 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 513419 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 509328 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 513424 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.574437 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 585548366 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 166128000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 341989 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 421912263 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 3394284142 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 753420072 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 764076323 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 233540433 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 2970138 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 251618660 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 350290492 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1175688320 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 10057151 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3685758924 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 87714492 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.115558 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 350290492 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 173332559 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.692710 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 2175919229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.693886 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.844671 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dcache.tagsinuse 4095.574913 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 585702974 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 165969000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 343309 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 421597556 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 3393767574 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 753336946 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 764050676 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 233579864 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 2970228 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 251603669 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 350205998 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1175621134 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 10022642 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3685217760 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 87763558 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.115580 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 350205998 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 173420048 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.692887 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 2175535270 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.693936 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.844478 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 1350521444 62.07% 62.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 247724506 11.38% 73.45% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 78785496 3.62% 77.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 36714251 1.69% 78.76% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 82505145 3.79% 82.55% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 39097939 1.80% 84.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 30045371 1.38% 85.73% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 19662444 0.90% 86.63% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 290862633 13.37% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 1350120177 62.06% 62.06% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 247723459 11.39% 73.45% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 78876862 3.63% 77.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 36715633 1.69% 78.76% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 82505940 3.79% 82.55% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 39095379 1.80% 84.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 30113044 1.38% 85.73% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 19663449 0.90% 86.64% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 290721327 13.36% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 2175919229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 350290492 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 33351.843100 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.230992 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 350288376 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 70572500 # number of ReadReq miss cycles
|
||||
system.cpu.fetch.rateDist::total 2175535270 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 350205998 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 33274.163131 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34791.817524 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 350203877 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 70574500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 2116 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 735 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 48060500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 2121 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 740 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 48047500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1381 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 253832.156522 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 253770.925362 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 350290492 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 33351.843100 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 350288376 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 70572500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 350205998 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 33274.163131 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34791.817524 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 350203877 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 70574500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 2116 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 735 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 48060500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 2121 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 740 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 48047500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1381 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.517203 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1059.231284 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 350290492 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 33351.843100 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.517204 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1059.233334 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 350205998 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 33274.163131 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34791.817524 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 350288376 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 70572500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 350203877 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 70574500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 2116 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 735 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 48060500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 2121 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 740 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 48047500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1381 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -211,212 +211,213 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 223 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1380 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1059.231284 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 350288376 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1059.233334 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 350203877 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 1511758 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 126596313 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 341046394 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.865157 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 745176720 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 207345254 # Number of stores executed
|
||||
system.cpu.idleCycles 1347738 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 126526916 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 340982559 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.865733 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 746184493 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 208199925 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1478969218 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1850021692 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.963149 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1479878942 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1850747692 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.963175 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1424467072 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.849635 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1860023576 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 88314915 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 3103548 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 732453281 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 21345324 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 16485503 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 296886262 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2838946953 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 537831466 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 95847914 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1883819308 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 43195 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1425382580 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.850182 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1860799390 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 88298258 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 3065589 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 732363888 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 21345183 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 16501703 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 296834010 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2838380214 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 537984568 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 98702938 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1884599663 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 42681 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 9926 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 233540433 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 76384 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 10075 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 233579864 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 76418 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 116246750 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 24118 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 3315 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 116246268 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 24120 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 6075012 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 6177679 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 20 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 329936034 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 130028306 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 6075012 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2827686 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 85487229 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.645540 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.645540 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 329846641 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 129976054 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 6177679 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2822462 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 85475796 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.645702 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.645702 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1178571095 59.53% 59.53% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.53% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.53% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2996630 0.15% 59.69% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.69% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.69% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.69% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.69% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.69% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 570412087 28.81% 88.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 227687410 11.50% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1178510091 59.42% 59.42% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.42% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.42% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2995561 0.15% 59.57% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.57% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.57% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.57% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.57% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.57% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 574193114 28.95% 88.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 227603835 11.48% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1979667222 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 5110932 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.002582 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1983302601 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 6030045 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.003040 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 148685 2.91% 2.91% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.91% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.91% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 233686 4.57% 7.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 4411963 86.32% 93.81% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 316598 6.19% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 148667 2.47% 2.47% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.47% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 233339 3.87% 6.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 5333431 88.45% 94.78% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 314608 5.22% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 2175919229 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.909807 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.157368 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 2175535270 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.911639 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.163576 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 1068255963 49.09% 49.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 579314637 26.62% 75.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 292421261 13.44% 89.16% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 161809686 7.44% 96.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 50369072 2.31% 98.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 14937591 0.69% 99.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 7897011 0.36% 99.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 777368 0.04% 99.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 136640 0.01% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 1067990413 49.09% 49.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 580044793 26.66% 75.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 292279315 13.43% 89.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 158370905 7.28% 96.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 51349615 2.36% 98.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 15864540 0.73% 99.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 8721161 0.40% 99.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 777887 0.04% 99.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 136641 0.01% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 2175919229 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.909176 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2476265906 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1979667222 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 21634653 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1050976502 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1545941 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 19390982 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1261656908 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 275258 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34298.440009 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31164.934352 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 9440920000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 275258 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 8578397500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 275258 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 239542 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34105.753589 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.482948 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 204503 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1195031500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.146275 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 35039 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1086296000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146275 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 35039 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 69939 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34214.100859 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.876206 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2392900000 # number of UpgradeReq miss cycles
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 2175535270 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.911075 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2475761446 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1983302601 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 21636209 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1050320205 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 3387342 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 19392538 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1256970263 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 275262 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34309.417551 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31170.249101 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 11754 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 9040806000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.957299 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 263508 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 8213610000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.957299 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 263508 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 239543 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34105.503131 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.510605 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 204890 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1181858000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.144663 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 34653 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1074330000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.144663 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34653 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 68215 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34213.068973 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.842703 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2333844500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 69939 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2169639000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 68215 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2116155000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 69939 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 341989 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 341989 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 68215 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 343309 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 343309 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 4.064673 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.105608 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 514800 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34276.681695 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 204503 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 10635951500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.602753 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 310297 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 514805 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34285.718119 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 216644 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 10222664000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.579173 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 298161 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9664693500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.602753 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 310297 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9287940000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.579173 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 298161 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.056082 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.444448 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1837.702550 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14563.687199 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 514800 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34276.681695 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.057090 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.444973 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1870.709103 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14580.888860 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 514805 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34285.718119 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 204503 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 10635951500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.602753 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 310297 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 216644 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 10222664000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.579173 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 298161 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9664693500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.602753 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 310297 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9287940000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.579173 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 298161 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 84514 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 99965 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 83969 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 99434 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16401.389748 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 406325 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 16451.597962 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 408237 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 61949 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 446168372 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 144446189 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 732453281 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 296886262 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 2177430987 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 18705831 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.writebacks 61561 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 445088392 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 142143895 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 732363888 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 296834010 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 2176883008 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 18665128 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1244779258 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:FullRegisterEvents 818 # Number of times there has been no free registers
|
||||
system.cpu.rename.RENAME:IQFullEvents 29460 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 816810065 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 24399902 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 4857699412 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 3052479029 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2393152182 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 700108886 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 233540433 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 34052536 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1148372924 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 372701478 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 21719371 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 176909620 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 21553732 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 44523 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:FullRegisterEvents 724 # Number of times there has been no free registers
|
||||
system.cpu.rename.RENAME:IQFullEvents 28925 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 816745640 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 24395596 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 4856285750 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 3051371057 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2392375919 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 700064958 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 233579864 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 34053219 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1147596661 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 372426461 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 21718962 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 176891245 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 21553313 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 41709 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -152,12 +152,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
|
||||
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simout
|
||||
Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 25 2010 03:11:27
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 03:27:10
|
||||
M5 executing on SC2B0619
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
|
||||
M5 compiled Aug 26 2010 13:03:41
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:04:04
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -43,4 +45,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 2076000877000 because target called exit()
|
||||
Exiting @ tick 2075400743000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,43 +1,43 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 933241 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 193388 # Number of bytes of host memory used
|
||||
host_seconds 1596.08 # Real time elapsed on the host
|
||||
host_tick_rate 1300690172 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1385286 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211532 # Number of bytes of host memory used
|
||||
host_seconds 1075.25 # Real time elapsed on the host
|
||||
host_tick_rate 1930162951 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1489523295 # Number of instructions simulated
|
||||
sim_seconds 2.076001 # Number of seconds simulated
|
||||
sim_ticks 2076000877000 # Number of ticks simulated
|
||||
sim_seconds 2.075401 # Number of seconds simulated
|
||||
sim_ticks 2075400743000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21085.380854 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.380854 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21012.879485 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18012.879485 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4079726000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 4065698000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3499268000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3485240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 1008000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 954000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 54403.143945 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51403.143945 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 166528617 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 17311026000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001907 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 318199 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 16356429000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001907 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 318199 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
|
||||
|
|
@ -47,42 +47,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 42833.478535 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 21977044000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 41777.116781 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 568847975 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 21376724000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000899 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 511685 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 20437801000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 19841669000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000899 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 511685 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999812 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.229973 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_blocks::0 4095.231029 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 41777.116781 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 568846579 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 21977044000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 513081 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 568847975 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 21376724000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000899 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 511685 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 20437801000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 19841669000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000899 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 511685 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 449125 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.229973 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4095.231029 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 567696000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 316424 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 567036000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 316439 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency
|
||||
|
|
@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 1107 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.442585 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 906.413760 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.442593 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 906.429761 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
|
||||
|
|
@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 118 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 906.413760 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 906.429761 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -142,36 +142,37 @@ system.cpu.idle_fraction 0 # Pe
|
|||
system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 12098 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 12877124000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.953422 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 247637 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9905480000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.953422 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 247637 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 160849 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1754688000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.173408 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33744 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1349760000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173408 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33744 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 161183 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1737320000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.171692 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33410 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1336400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171692 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33410 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 58482 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.221675 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3040960000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 58482 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2339280000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 316424 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 316424 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 58482 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 316439 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 316439 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 3.428657 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 3.448937 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -180,44 +181,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 160849 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 15260908000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.645963 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 293479 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 173281 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 14614444000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.618599 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 281047 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 11739160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.645963 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 293479 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 11241880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.618599 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 281047 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.052187 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.447022 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1710.054315 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14648.032371 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.052996 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.447533 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1736.572582 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14664.762880 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 160849 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 15260908000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.645963 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 293479 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 173281 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 14614444000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.618599 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 281047 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 11739160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.645963 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 293479 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 11241880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.618599 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 281047 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 82908 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 98342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 82461 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 97909 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16358.086686 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 16401.335462 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 337682 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 61864 # number of writebacks
|
||||
system.cpu.l2cache.writebacks 61551 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 4152001754 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4150801486 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1489523295 # Number of instructions executed
|
||||
system.cpu.num_refs 569365767 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
|
||||
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled May 2 2010 23:23:01
|
||||
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||
M5 started May 2 2010 23:23:02
|
||||
M5 executing on burrito
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
|
||||
M5 compiled Aug 26 2010 13:20:12
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:33:02
|
||||
M5 executing on zizzer
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -44,4 +46,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 1814725999000 because target called exit()
|
||||
Exiting @ tick 1814105620000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1830893 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 225176 # Number of bytes of host memory used
|
||||
host_seconds 884.47 # Real time elapsed on the host
|
||||
host_tick_rate 2051770366 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1308474 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210192 # Number of bytes of host memory used
|
||||
host_seconds 1237.60 # Real time elapsed on the host
|
||||
host_tick_rate 1465826235 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1619366787 # Number of instructions simulated
|
||||
sim_seconds 1.814726 # Number of seconds simulated
|
||||
sim_ticks 1814725999000 # Number of ticks simulated
|
||||
sim_seconds 1.814106 # Number of seconds simulated
|
||||
sim_ticks 1814105620000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20886.624165 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17886.624165 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20817.236451 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17817.236451 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4121474000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 4107782000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3529496000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3515804000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 187876653 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 17326624000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001644 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 309404 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 16398412000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001644 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 309404 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 54292.890290 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51292.890290 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 187878126 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 16718464000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001636 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 307931 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 15794671000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001636 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 307931 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 42326.481558 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 39326.481558 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 606721452 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 21448098000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 506730 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 41219.114233 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 606722925 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 20826246000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000832 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 505257 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 19927908000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 506730 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 19310475000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000832 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 505257 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4094.901606 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_blocks::0 4094.903534 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 42326.481558 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 39326.481558 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 41219.114233 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 606721452 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 21448098000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 506730 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 606722925 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 20826246000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000832 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 505257 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 19927908000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 506730 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 19310475000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000832 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 505257 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 437952 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.901606 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.903534 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 779585000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 306191 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 306200 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
|
|
@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.322346 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 660.164839 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.322353 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 660.178535 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
|
|
@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 4 # number of replacements
|
||||
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 660.164839 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 660.178535 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -132,36 +132,37 @@ system.cpu.idle_fraction 0 # Pe
|
|||
system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 12725544000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 244722 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9788880000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 244722 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 12516 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 12074712000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.948856 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 232206 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9288240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.948856 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 232206 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 164971 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1720004000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.167015 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33077 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1323080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.167015 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33077 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 64682 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_hits 165297 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1703052000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.165369 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 32751 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1310040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165369 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32751 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 63209 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3363464000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3286868000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 64682 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2587280000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 63209 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528360000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 64682 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 306191 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 306191 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 63209 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 306200 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 306200 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 3.428492 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 3.450731 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -170,44 +171,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 164971 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 14445548000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.627412 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 277799 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 177813 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 13777764000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.598408 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 264957 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 11111960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.627412 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 277799 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 10598280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.598408 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 264957 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.052754 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.452175 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1728.633036 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14816.859075 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.053631 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.452717 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1757.366037 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14834.623829 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 164971 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 14445548000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.627412 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 277799 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 177813 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 13777764000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.598408 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 264957 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 11111960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.627412 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 277799 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 10598280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.598408 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 264957 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 81557 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 97073 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 81078 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 96612 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16545.492111 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 332814 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 16591.989866 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 333382 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 61569 # number of writebacks
|
||||
system.cpu.l2cache.writebacks 61253 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 3629451998 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3628211240 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1619366787 # Number of instructions executed
|
||||
system.cpu.num_refs 607228182 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -8,11 +8,12 @@ type=LinuxAlphaSystem
|
|||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/home/stever/m5/m5_system_2.0b3/binaries/console
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
|
|
@ -660,7 +661,7 @@ table_size=65536
|
|||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -680,7 +681,7 @@ table_size=65536
|
|||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -806,7 +807,7 @@ system=system
|
|||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
|
||||
Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,13 +7,14 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 3 2010 18:29:42
|
||||
M5 revision 75205c286109 7549 default qtip tip ext/memorderviolation_uncached.patch
|
||||
M5 started Aug 3 2010 18:34:19
|
||||
M5 executing on harpertown2
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
M5 compiled Aug 26 2010 12:51:14
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 12:51:16
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /root/ali/dist/system/m5_system_2.0b3/binaries/vmlinux
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 125751000
|
||||
Exiting @ tick 1908681362500 because m5_exit instruction encountered
|
||||
info: Launching CPU 1 @ 125480500
|
||||
Exiting @ tick 1906675009500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -8,11 +8,12 @@ type=LinuxAlphaSystem
|
|||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/home/stever/m5/m5_system_2.0b3/binaries/console
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
|
|
@ -355,7 +356,7 @@ table_size=65536
|
|||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -375,7 +376,7 @@ table_size=65536
|
|||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -501,7 +502,7 @@ system=system
|
|||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simout
|
||||
Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,12 +7,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 3 2010 18:29:42
|
||||
M5 revision 75205c286109 7549 default qtip tip ext/memorderviolation_uncached.patch
|
||||
M5 started Aug 3 2010 18:34:19
|
||||
M5 executing on harpertown2
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
|
||||
M5 compiled Aug 26 2010 12:51:14
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 12:51:33
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /root/ali/dist/system/m5_system_2.0b3/binaries/vmlinux
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1866391592500 because m5_exit instruction encountered
|
||||
Exiting @ tick 1865288389500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -152,7 +152,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
|
||||
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:38:31
|
||||
M5 compiled Aug 26 2010 13:52:30
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 14:11:34
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
|
||||
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -28,4 +30,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 152158072000 because target called exit()
|
||||
Exiting @ tick 152155526000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1413696 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 343480 # Number of bytes of host memory used
|
||||
host_seconds 64.50 # Real time elapsed on the host
|
||||
host_tick_rate 2359219725 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1008175 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 344580 # Number of bytes of host memory used
|
||||
host_seconds 90.44 # Real time elapsed on the host
|
||||
host_tick_rate 1682447495 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 91176087 # Number of instructions simulated
|
||||
sim_seconds 0.152158 # Number of seconds simulated
|
||||
sim_ticks 152158072000 # Number of ticks simulated
|
||||
sim_seconds 0.152156 # Number of seconds simulated
|
||||
sim_ticks 152155526000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 22564820 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14013.903608 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.903608 # average ReadReq mshr miss latency
|
||||
|
|
@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 9914694000 #
|
|||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.039894 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 900198 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 4738868 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 4642722 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 5384176000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.020289 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 96146 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5095738000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.020289 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 96146 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55998.688893 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52998.688893 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 4642766 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 5381586000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.020280 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 96102 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5093280000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.020280 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 96102 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 27.837649 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 27303688 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18065.511510 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 15065.511510 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 26307344 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 17999464000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.036491 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 996344 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18063.709726 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 15063.709726 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 26307388 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 17996874000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.036490 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 996300 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 15010432000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.036491 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 996344 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 15007974000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.036490 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 996300 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.874740 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3582.934837 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.874745 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3582.956819 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 27303688 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 18065.511510 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 15065.511510 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 18063.709726 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 15063.709726 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 26307344 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 17999464000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.036491 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 996344 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 26307388 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 17996874000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.036490 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 996300 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 15010432000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.036491 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 996344 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 15007974000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.036490 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 996300 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 942711 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 946807 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3582.934837 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3582.956819 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26356881 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 54489025000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 96053 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 54487870000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 96132 # number of writebacks
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 599 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.249734 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 511.454894 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.249735 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 511.457636 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 107819118 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 54667.779633 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 51667.779633 # average overall mshr miss latency
|
||||
|
|
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 2 # number of replacements
|
||||
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 511.454894 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 511.457636 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 107818519 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -150,12 +150,13 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2423668000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 46609 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1864360000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 46609 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2423512000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.999936 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 46606 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1864240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999936 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 46606 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 900797 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
|
|
@ -166,20 +167,20 @@ system.cpu.l2cache.ReadReq_misses 878 # nu
|
|||
system.cpu.l2cache.ReadReq_mshr_miss_latency 35120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000975 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 878 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 49537 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses 49493 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2575924000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2573636000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 49537 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1981480000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 49493 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1979720000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 49537 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 96053 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 96053 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 49493 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 96132 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 96132 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 52.567404 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 52.533433 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 947406 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 899919 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2469324000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.050123 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 47487 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 899922 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2469168000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.050120 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 47484 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1899480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.050123 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 47487 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1899360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.050120 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 47484 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.009182 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.265752 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 300.880505 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 8708.164911 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.009784 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.265384 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 320.609441 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 8696.109935 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 947406 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 899919 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2469324000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.050123 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 47487 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 899922 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2469168000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.050120 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 47484 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1899480000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.050123 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 47487 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1899360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.050120 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 47484 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 678 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 15333 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 15344 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 9009.045417 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 806016 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 9016.719375 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 806073 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 35 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 304316144 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 304311052 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 91176087 # Number of instructions executed
|
||||
system.cpu.num_refs 27330336 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,14 +152,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
|
||||
cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
|
||||
gid=100
|
||||
input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simout
|
||||
Redirecting stderr to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 25 2010 03:11:27
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 03:30:29
|
||||
M5 executing on SC2B0619
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
|
||||
M5 compiled Aug 26 2010 13:03:41
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:06:13
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -28,4 +30,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 366435406000 because target called exit()
|
||||
Exiting @ tick 366433850000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 794629 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 325576 # Number of bytes of host memory used
|
||||
host_seconds 306.85 # Real time elapsed on the host
|
||||
host_tick_rate 1194166006 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 994564 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 343716 # Number of bytes of host memory used
|
||||
host_seconds 245.17 # Real time elapsed on the host
|
||||
host_tick_rate 1494621764 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 243835278 # Number of instructions simulated
|
||||
sim_seconds 0.366435 # Number of seconds simulated
|
||||
sim_ticks 366435406000 # Number of ticks simulated
|
||||
sim_seconds 0.366434 # Number of seconds simulated
|
||||
sim_ticks 366433850000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency
|
||||
|
|
@ -29,15 +29,15 @@ system.cpu.dcache.SwapReq_mshr_miss_latency 424000 #
|
|||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55998.672804 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52998.672804 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 22807014 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 5316346000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.004145 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 94937 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5031535000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004145 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 94937 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
|
||||
|
|
@ -47,42 +47,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 17826578000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_avg_miss_latency 18045.256400 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 15045.256400 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 104134591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 17824996000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses 987794 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 14863118000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 14861614000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 987794 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.871490 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3569.622607 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.871491 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3569.628477 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 18045.256400 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 15045.256400 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 104134565 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_hits 104134591 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 17824996000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 987820 # number of overall misses
|
||||
system.cpu.dcache.overall_misses 987794 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 14863118000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 14861614000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 987794 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3569.622607 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3569.628477 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 134379688000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 94877 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 134378918000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 94947 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency
|
||||
|
|
@ -116,7 +116,7 @@ system.cpu.icache.fast_writes 0 # nu
|
|||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.354611 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 726.242454 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_blocks::0 726.243472 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
|
||||
|
|
@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 25 # number of replacements
|
||||
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 726.242454 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 726.243472 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -142,12 +142,13 @@ system.cpu.idle_fraction 0 # Pe
|
|||
system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2428972000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.999936 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 46711 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868440000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999936 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 46711 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
|
|
@ -158,20 +159,20 @@ system.cpu.l2cache.ReadReq_misses 1086 # nu
|
|||
system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses 48231 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2508012000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 48231 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1929240000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 94877 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 94877 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 48231 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 94947 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 94947 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 51.538160 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -180,44 +181,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 892656 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2485444000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.050823 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 47797 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1911880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.050823 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 47797 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.010976 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.262444 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 359.659901 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 8599.756547 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.011380 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.262199 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 372.883816 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 8591.744977 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 892653 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 47800 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 892656 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2485444000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.050823 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 47797 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1911880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.050823 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 47797 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 891 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 15566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 8959.416448 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 8964.628794 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 802243 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 41 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 732870812 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 732867700 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 243835278 # Number of instructions executed
|
||||
system.cpu.num_refs 105711442 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
|
||||
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled May 2 2010 23:23:01
|
||||
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||
M5 started May 2 2010 23:23:02
|
||||
M5 executing on burrito
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
|
||||
M5 compiled Aug 26 2010 13:20:12
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:47:25
|
||||
M5 executing on zizzer
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -28,4 +30,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 382077495000 because target called exit()
|
||||
Exiting @ tick 378879619000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1204056 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 359708 # Number of bytes of host memory used
|
||||
host_seconds 223.99 # Real time elapsed on the host
|
||||
host_tick_rate 1705780609 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1022159 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 344728 # Number of bytes of host memory used
|
||||
host_seconds 263.85 # Real time elapsed on the host
|
||||
host_tick_rate 1435967954 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 269696010 # Number of instructions simulated
|
||||
sim_seconds 0.382077 # Number of seconds simulated
|
||||
sim_ticks 382077495000 # Number of ticks simulated
|
||||
sim_seconds 0.378880 # Number of seconds simulated
|
||||
sim_ticks 378879619000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 15892.283447 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12892.283447 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 15327.890775 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12327.890775 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 31160318000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 30053702000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 25278158000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 24171542000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000.038318 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.038318 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 31204877 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 13152953000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.007471 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 234874 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 12448331000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.007471 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 234874 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55478.946733 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52478.946733 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 31241017 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 11025553000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.006321 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 198734 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 10429351000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006321 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 198734 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 20182.816586 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 17182.816586 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 120023607 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 44313271000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.017964 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2195594 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 19022.982198 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 16022.982198 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 120059747 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 41079255000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.017669 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2159454 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 37726489000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.017964 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2195594 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 34600893000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.017669 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2159454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.995398 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4077.149063 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.995362 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4077.003489 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 20182.816586 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 17182.816586 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 19022.982198 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 16022.982198 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 120023607 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 44313271000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.017964 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2195594 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 120059747 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 41079255000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.017669 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2159454 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 37726489000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.017964 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2195594 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 34600893000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.017669 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2159454 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4077.149063 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4077.003489 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 127446193000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 234826 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 127444032000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 283281 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
|
|
@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 808 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.325920 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 667.483560 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.325684 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 667.001102 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
|
|
@ -124,90 +124,91 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 667.483560 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 667.001102 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.292152 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.299104 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5517699000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 106109 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4244360000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 106109 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 2466 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5389467000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.976760 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 103643 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4145720000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.976760 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 103643 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1872381 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 4635644000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.045448 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 89147 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 3565880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045448 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 89147 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 128765 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51991.115598 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1898729 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 3265548000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.032015 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 62799 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 2511960000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.032015 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 62799 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 92625 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51994.385965 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 6694636000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 4815980000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 128765 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5150600000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 92625 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3705000000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 128765 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 234826 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 234826 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 92625 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 283281 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 283281 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 13.775827 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 19.797170 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000.158766 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000.186251 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1872381 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 10153343000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.094434 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 195256 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 1901195 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 8655015000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.080499 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 166442 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 7810240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.094434 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 195256 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 6657680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.080499 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 166442 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.198864 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.350544 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 6516.387210 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 11486.611177 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.204822 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.350671 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 6711.601001 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 11490.800356 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000.158766 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000.186251 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1872381 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 10153343000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.094434 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 195256 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 1901195 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 8655015000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.080499 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 166442 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 7810240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.094434 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 195256 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 6657680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.080499 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 166442 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 109048 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 132982 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 81066 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 106133 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18002.998387 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1831937 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 18202.401357 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2101133 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 70890 # number of writebacks
|
||||
system.cpu.l2cache.writebacks 48460 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 764154990 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 757759238 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 269696010 # Number of instructions executed
|
||||
system.cpu.num_refs 122219139 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
|
||||
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:39:26
|
||||
M5 compiled Aug 26 2010 13:52:30
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:57:01
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
|
||||
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -72,4 +74,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 755274721000 because target called exit()
|
||||
Exiting @ tick 745672616000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1894447 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213780 # Number of bytes of host memory used
|
||||
host_seconds 295.32 # Real time elapsed on the host
|
||||
host_tick_rate 2557466745 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1125820 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214880 # Number of bytes of host memory used
|
||||
host_seconds 496.95 # Real time elapsed on the host
|
||||
host_tick_rate 1500512692 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 559470527 # Number of instructions simulated
|
||||
sim_seconds 0.755275 # Number of seconds simulated
|
||||
sim_ticks 755274721000 # Number of ticks simulated
|
||||
sim_seconds 0.745673 # Number of seconds simulated
|
||||
sim_ticks 745672616000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 127326326 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 22055.619697 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19055.619697 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20914.908888 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17914.908888 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 126543330 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 17269462000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 16376290000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.006150 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 782996 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 14920474000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 14027302000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.006150 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 782996 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.902227 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.902227 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 54940305 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 44102275000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.014132 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 787542 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 41739649000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.014132 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 787542 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 53833.507889 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50833.507889 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 55072849 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 35260840000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.011754 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 654998 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 33295846000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 654998 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 159.673059 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 183054173 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 39076.887665 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 36076.887665 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 181483635 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 61371737000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.008580 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1570538 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 35909.141485 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 32909.141485 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 181616179 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 51637130000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.007856 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1437994 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 56660123000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.008580 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1570538 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 47323148000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.007856 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1437994 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.993060 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4067.574815 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.992972 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4067.215006 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 183054173 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 39076.887665 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 36076.887665 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 35909.141485 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 32909.141485 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 181483635 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 61371737000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.008580 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1570538 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 181616179 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 51637130000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.007856 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1437994 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 56660123000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.008580 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1570538 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 47323148000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.007856 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1437994 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 1135200 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1139296 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4067.574815 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4067.215006 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 181914877 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 11579638000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 784411 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 11578483000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 808512 # number of writebacks
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -83,13 +83,13 @@ system.cpu.dtb.write_accesses 0 # DT
|
|||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 512145761 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24746.983769 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21746.983769 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 512134240 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 285110000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 250547000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
|
|
@ -101,31 +101,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 512145761 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 24746.983769 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 21746.983769 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 512134240 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 285110000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 250547000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.485758 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 994.831789 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.485313 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 993.921198 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 512145761 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 24746.983769 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 21746.983769 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 512134240 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 285110000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 11521 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 250547000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 9788 # number of replacements
|
||||
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 994.831789 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 993.921198 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 512134240 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -150,36 +150,37 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.l2cache.ReadExReq_accesses 356300 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 18527600000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 356300 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 14252000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 356300 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 33786 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 16770728000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.905175 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 322514 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 12900560000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.905175 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 322514 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 794517 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 641390 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 7962604000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.192730 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 153127 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 6125080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.192730 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 153127 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 431242 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.715190 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 662657 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 6856720000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.165962 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 131860 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 5274400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165962 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 131860 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 298698 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51993.732800 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 22420580000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 15530424000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 431242 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 17249680000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 298698 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11947920000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 431242 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 784411 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 784411 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 298698 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 808512 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 808512 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 4.037361 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.737661 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 1150817 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 641390 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 26490204000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.442666 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 509427 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 696443 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 23627448000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.394827 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 454374 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 20377080000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.442666 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 509427 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 18174960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.394827 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 454374 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.106439 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.402713 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3487.785932 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13196.100733 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.184240 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.380639 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 6037.178832 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 12472.788257 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 1150817 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 641390 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 26490204000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.442666 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 509427 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 696443 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 23627448000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.394827 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 454374 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 20377080000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.442666 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 509427 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 18174960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.394827 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 454374 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 258533 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 276277 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 232496 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 251560 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16683.886665 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1115430 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 531606891000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 206160 # number of writebacks
|
||||
system.cpu.l2cache.tagsinuse 18509.967089 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1191806 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 525324932000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 186433 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1510549442 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1491345232 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 559470527 # Number of instructions executed
|
||||
system.cpu.num_refs 184987503 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
|
||||
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled May 2 2010 23:23:01
|
||||
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||
M5 started May 2 2010 23:23:02
|
||||
M5 executing on burrito
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
|
||||
M5 compiled Aug 26 2010 13:20:12
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:22:00
|
||||
M5 executing on zizzer
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -74,4 +76,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 1722332515000 because target called exit()
|
||||
Exiting @ tick 1701783891000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1698687 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 228888 # Number of bytes of host memory used
|
||||
host_seconds 880.50 # Real time elapsed on the host
|
||||
host_tick_rate 1956075066 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1040513 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213908 # Number of bytes of host memory used
|
||||
host_seconds 1437.46 # Real time elapsed on the host
|
||||
host_tick_rate 1183878785 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1495700521 # Number of instructions simulated
|
||||
sim_seconds 1.722333 # Number of seconds simulated
|
||||
sim_ticks 1722332515000 # Number of ticks simulated
|
||||
sim_seconds 1.701784 # Number of seconds simulated
|
||||
sim_ticks 1701783891000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 24152.982435 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21152.981277 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 22845.361911 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19845.360753 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 41722200000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 39463398000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 36539956000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 34281154000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.911625 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.911625 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 147694849 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 82059582500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.009824 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1465352 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 77663526500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009824 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1465352 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 53546.298194 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50546.298194 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 147974496 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 63490113500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.007949 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1185705 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 59932998500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.007949 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1185705 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 38769.450220 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35769.449593 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 530069624 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 123781782500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005987 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 3192766 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 35341.333979 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 32341.333293 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 530349271 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 102953511500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005463 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2913119 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 114203482500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005987 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 3192766 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 94214152500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005463 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2913119 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.997759 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4086.820737 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.997733 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4086.713108 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 38769.450220 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35769.449593 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 35341.333979 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 32341.333293 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 530069624 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 123781782500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005987 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 3192766 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 530349271 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 102953511500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005463 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2913119 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 114203482500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005987 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 3192766 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 94214152500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005463 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2913119 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4086.820737 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4086.713108 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 8218050000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 1463134 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 1528950 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 48626.865672 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45626.865672 # average ReadReq mshr miss latency
|
||||
|
|
@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 2814 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.433368 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 887.538061 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.433486 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 887.780127 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 48626.865672 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency
|
||||
|
|
@ -124,90 +124,91 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 1253 # number of replacements
|
||||
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 887.538061 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 887.780127 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014538 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.015933 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 41134299500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 791044 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 31641760000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 791044 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 69270 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 37532259500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.912432 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 721774 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28870960000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.912432 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 721774 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1310327 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 21834852000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.242685 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 419901 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 16796040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242685 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 419901 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 674308 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.126631 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1364108 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 19038240000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.211602 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 366120 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 14644800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.211602 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 366120 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 394661 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51994.993171 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 35056684000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 20520396000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 674308 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26972320000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 394661 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 15786440000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 674308 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 1463134 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 1463134 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 394661 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 1528950 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 1528950 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 3.424249 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 3.977137 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000.009497 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000.010571 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1310327 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 62969151500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.480291 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1210945 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 1433378 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 56570499500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.431486 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1087894 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 48437800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.480291 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1210945 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 43515760000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.431486 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1087894 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.111884 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.413412 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3666.207378 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13546.690457 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.230883 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.374106 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 7565.560471 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 12258.710159 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000.009497 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000.010571 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1310327 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 62969151500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.480291 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1210945 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 1433378 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 56570499500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.431486 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1087894 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 48437800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.480291 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1210945 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 43515760000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.431486 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1087894 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 664035 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 680440 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 603454 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 621473 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 17212.897835 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2329996 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 921653687000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 481618 # number of writebacks
|
||||
system.cpu.l2cache.tagsinuse 19824.270630 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2471683 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 910963647000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 436481 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 3444665030 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3403567782 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1495700521 # Number of instructions executed
|
||||
system.cpu.num_refs 533262345 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -353,7 +353,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -46,3 +46,6 @@ Writing to chair.cook.ppm
|
|||
12 8 14
|
||||
13 8 14
|
||||
14 8 14
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simerr
|
||||
Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,14 +7,15 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jun 6 2010 03:04:38
|
||||
M5 revision ba1a0193c050 7448 default tip
|
||||
M5 started Jun 6 2010 03:04:42
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 11:52:05
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.133333
|
||||
Exiting @ tick 136571603500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,340 +1,340 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 242260 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213404 # Number of bytes of host memory used
|
||||
host_seconds 1550.30 # Real time elapsed on the host
|
||||
host_tick_rate 86851686 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 136199 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214028 # Number of bytes of host memory used
|
||||
host_seconds 2757.55 # Real time elapsed on the host
|
||||
host_tick_rate 49526494 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 375574819 # Number of instructions simulated
|
||||
sim_seconds 0.134646 # Number of seconds simulated
|
||||
sim_ticks 134646047500 # Number of ticks simulated
|
||||
sim_seconds 0.136572 # Number of seconds simulated
|
||||
sim_ticks 136571603500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 35411688 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 43873215 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 1393 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 5500503 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 35240813 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 62127254 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 12478438 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.BTBHits 34712245 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 43971564 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 1375 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 5750083 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 35466067 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 62830534 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 12729193 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 44587532 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 13023462 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 12727499 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 253935739 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.569943 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.243237 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 257005436 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.551191 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.213326 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 122688628 48.31% 48.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 50190176 19.76% 68.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 18710011 7.37% 75.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 19547996 7.70% 83.15% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 12735073 5.02% 88.16% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 8256826 3.25% 91.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 5486679 2.16% 93.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 3296888 1.30% 94.87% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 13023462 5.13% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 123174402 47.93% 47.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 51601116 20.08% 68.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 20452287 7.96% 75.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 20740884 8.07% 84.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 11122877 4.33% 88.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 8764041 3.41% 91.77% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 5151763 2.00% 93.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 3270567 1.27% 95.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 12727499 4.95% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 253935739 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 257005436 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 398664594 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 100651995 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 174183397 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 5496166 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 5745758 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 95019473 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 99827575 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 375574819 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.717013 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.717013 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 95369422 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33035.714286 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31908.121827 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 95367714 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 56425000 # number of ReadReq miss cycles
|
||||
system.cpu.cpi 0.727267 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.727267 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 95959241 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33093.582888 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31984.199796 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 95957558 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 55696500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1708 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 723 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 31429500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_misses 1683 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 702 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 31376500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 981 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 30397.287074 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36179.950785 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73502664 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 549126991 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000246 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 18065 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 14753 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 119827997 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3312 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3499.727273 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 30331.836439 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36071.185392 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73502803 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 543728500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000244 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 17926 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 14695 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 116546000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3231 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 40390.006697 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_refs 40579.607280 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 38497 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 168890151 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 30625.195519 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35200.720735 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 168870378 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 605551991 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 19773 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 15476 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 151257497 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_accesses 169479970 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 30568.871437 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35119.301994 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 169460361 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 599425000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000116 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 19609 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 15397 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 147922500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4297 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 4212 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.804196 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3293.985737 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 168890151 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 30625.195519 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35200.720735 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.804256 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3294.233360 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 169479970 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 30568.871437 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35119.301994 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 168870378 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 605551991 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 19773 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 15476 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 151257497 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_hits 169460361 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 599425000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000116 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 19609 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 15397 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 147922500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4297 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 4212 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 786 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4181 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 781 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3293.985737 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168870618 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3294.233360 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 169460440 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 639 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 20455851 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 4411 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 11313984 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 531721678 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 132373008 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 100014717 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 15215664 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 13188 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1092163 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 184984239 # DTB accesses
|
||||
system.cpu.dtb.data_acv 1 # DTB access violations
|
||||
system.cpu.dtb.data_hits 184965275 # DTB hits
|
||||
system.cpu.dtb.data_misses 18964 # DTB misses
|
||||
system.cpu.dcache.writebacks 638 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 21059081 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 4405 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 11508131 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 539100093 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 134649980 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 100169012 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 15996729 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 13181 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1127363 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 185557278 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 185509117 # DTB hits
|
||||
system.cpu.dtb.data_misses 48161 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 104315848 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 105313060 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 104298344 # DTB read hits
|
||||
system.cpu.dtb.read_misses 17504 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 80668391 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 1 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 80666931 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1460 # DTB write misses
|
||||
system.cpu.fetch.Branches 62127254 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 63793845 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 167246591 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1555705 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 544184292 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 5877257 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.230706 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 63793845 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 47890126 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.020796 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 269151403 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.021852 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.019136 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dtb.read_hits 105266355 # DTB read hits
|
||||
system.cpu.dtb.read_misses 46705 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 80244218 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 80242762 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1456 # DTB write misses
|
||||
system.cpu.fetch.Branches 62830534 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 64860863 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 168703371 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1410406 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 552550587 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 6169479 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.230028 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 64860863 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 47441438 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.022934 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 273002165 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.023979 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.024544 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 165698966 61.56% 61.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 11106934 4.13% 65.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 11530416 4.28% 69.97% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 6307474 2.34% 72.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 14437862 5.36% 77.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 9686725 3.60% 81.28% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 7134176 2.65% 83.93% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3886825 1.44% 85.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 39362025 14.62% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 169159964 61.96% 61.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 10172385 3.73% 65.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 10846224 3.97% 69.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 7014396 2.57% 72.23% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 14631841 5.36% 77.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 9961062 3.65% 81.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 7189550 2.63% 83.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 4041352 1.48% 85.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 39985391 14.65% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 269151403 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 63793845 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 32214.491857 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30831.032720 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 63788994 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 156272500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 4851 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 939 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 120611000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3912 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 273002165 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 64860863 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 32283.674736 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30878.201844 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 64856030 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 156027000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000075 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 4833 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 929 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 120548500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000060 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3904 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 16305.980061 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 16612.712602 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 63793845 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 32214.491857 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 30831.032720 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 63788994 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 156272500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 4851 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 939 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 120611000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3912 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 64860863 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 32283.674736 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 30878.201844 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 64856030 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 156027000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000075 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 4833 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 929 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 120548500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000060 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3904 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.890533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1823.811736 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 63793845 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 32214.491857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 30831.032720 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.891431 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1825.650576 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 64860863 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 32283.674736 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 30878.201844 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 63788994 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 156272500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 4851 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 939 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 120611000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3912 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 64856030 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 156027000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000075 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 4833 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 929 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 120548500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000060 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3904 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 1991 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3912 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 1982 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3904 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1823.811736 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 63788994 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1825.650576 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 64856030 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 140695 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 51026412 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 27112711 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.557485 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 191688570 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 80679099 # Number of stores executed
|
||||
system.cpu.idleCycles 141045 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 51385726 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 27755438 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.545021 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 192526473 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 80254900 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 288216530 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 415792778 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.699054 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 290066917 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 417830932 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.699779 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 201478800 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.544021 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 416379790 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 6053312 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2368258 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 124922222 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 202982772 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.529714 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 418648136 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 6175903 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 3284723 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 125889658 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 241 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 6336167 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 92376215 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 493684492 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 111009471 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 9414741 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 419418502 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 122120 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 6874932 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 92903281 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 498492595 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 112271573 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 9215998 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 422011987 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 145222 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 26143 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 15215664 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 517890 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 28045 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 15996729 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 550279 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 8752772 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 41071 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 9131244 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2248 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 605872 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 176126 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 24270227 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 18844813 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 605872 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1054390 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4998922 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.394674 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.394674 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 648565 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 175867 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 25237663 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 19371879 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 648565 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1211280 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4964623 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.375011 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.375011 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 166405736 38.80% 38.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 2152798 0.50% 39.31% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34694447 8.09% 47.40% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7781263 1.81% 49.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2950957 0.69% 49.91% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16800389 3.92% 53.82% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1571056 0.37% 54.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 113131674 26.38% 80.57% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 83311342 19.43% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 168382264 39.05% 39.05% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 2152290 0.50% 39.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34830384 8.08% 47.63% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7781044 1.80% 49.44% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2959993 0.69% 50.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16854742 3.91% 54.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1589897 0.37% 54.40% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.40% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 114726286 26.60% 81.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 81917504 19.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 428833243 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 10058147 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.023455 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 431227985 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 9397735 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.021793 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 25860 0.26% 0.26% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.26% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.26% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 93260 0.93% 1.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 5650 0.06% 1.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 7446 0.07% 1.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 1317455 13.10% 14.41% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 1454078 14.46% 28.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 28.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 5920939 58.87% 87.74% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 1233459 12.26% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 51470 0.55% 0.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 51324 0.55% 1.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 3037 0.03% 1.13% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 5843 0.06% 1.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 1281381 13.63% 14.82% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 969484 10.32% 25.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 25.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 5699185 60.64% 85.78% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 1336011 14.22% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 269151403 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.593279 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.717169 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 273002165 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.579577 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.704793 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 98731931 36.68% 36.68% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 57661044 21.42% 58.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 40586976 15.08% 73.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 29421704 10.93% 84.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 23908046 8.88% 93.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 10239078 3.80% 96.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 5871323 2.18% 98.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 2172785 0.81% 99.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 558516 0.21% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 100185843 36.70% 36.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 58377873 21.38% 58.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 43478311 15.93% 74.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 28530639 10.45% 84.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 23283249 8.53% 92.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 11208488 4.11% 97.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 5200545 1.90% 99.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 1974869 0.72% 99.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 762348 0.28% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 269151403 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.592446 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 466571540 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 428833243 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 273002165 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.578762 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 470736916 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 431227985 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 89966373 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 863763 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 94399417 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 779543 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 69307198 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 72495736 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 63794154 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 64861170 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 63793845 # ITB hits
|
||||
system.cpu.itb.fetch_misses 309 # ITB misses
|
||||
system.cpu.itb.fetch_hits 64860863 # ITB hits
|
||||
system.cpu.itb.fetch_misses 307 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
|
|
@ -343,106 +343,107 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 3200 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34587.968437 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31457.812500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 110681499 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 3200 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 100665000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 3200 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4893 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34357.615894 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31171.594134 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 665 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 145264000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.864092 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4228 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 131793500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864092 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4228 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34466.386555 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31289.915966 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 4101500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 3199 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34578.066333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31448.372966 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 110511500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.999062 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 3196 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 100509000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999062 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 3196 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4881 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34355.892097 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31170.255561 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 145188000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.865806 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4226 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 131725500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865806 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4226 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 36 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34236.111111 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1232500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 36 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1116000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 639 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 639 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2666.666667 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 36 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 638 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 638 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.131910 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.134782 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 8000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 8093 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34456.852316 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31294.897684 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 665 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 255945499 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.917830 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7428 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 8080 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34451.562921 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31290.016168 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 658 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 255699500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.918564 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7422 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 232458500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.917830 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7428 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 232234500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.918564 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7422 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.106843 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.011587 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3501.040941 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 379.684950 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 8093 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34456.852316 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31294.897684 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.108617 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.011284 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3559.151087 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 369.756870 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 8080 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34451.562921 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31290.016168 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 665 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 255945499 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.917830 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7428 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 658 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 255699500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.918564 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7422 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 232458500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.917830 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7428 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 232234500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.918564 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7422 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 15 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4685 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 14 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4741 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3880.725891 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 618 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 3928.907957 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 639 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 74849853 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 55363768 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 124922222 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 92376215 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 269292098 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 9673248 # Number of cycles rename is blocking
|
||||
system.cpu.memDep0.conflictingLoads 73373175 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 55113413 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 125889658 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 92903281 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 273143210 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 10612512 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 1504479 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 137416112 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 8012015 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:IQFullEvents 2173514 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 139438532 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 7156113 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 682754738 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 518229128 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 335302113 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 95729398 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 15215664 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 10747190 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 75769772 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 369791 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 37587 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 23404736 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 258 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 3105 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:RenameLookups 690877715 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 524876259 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 339660686 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 96195896 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 15996729 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 10389927 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 80128345 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 368569 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 37570 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 22417777 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 259 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 3102 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -152,12 +152,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -46,3 +46,6 @@ Writing to chair.cook.ppm
|
|||
12 8 14
|
||||
13 8 14
|
||||
14 8 14
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,14 +7,15 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 24 2010 23:12:40
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 02:20:32
|
||||
M5 executing on SC2B0619
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 11:52:05
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.566667
|
||||
Exiting @ tick 567347489000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 860135 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 198216 # Number of bytes of host memory used
|
||||
host_seconds 463.49 # Real time elapsed on the host
|
||||
host_tick_rate 1224083493 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1188061 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213244 # Number of bytes of host memory used
|
||||
host_seconds 335.56 # Real time elapsed on the host
|
||||
host_tick_rate 1690751695 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_seconds 0.567352 # Number of seconds simulated
|
||||
sim_ticks 567351850000 # Number of ticks simulated
|
||||
sim_seconds 0.567347 # Number of seconds simulated
|
||||
sim_ticks 567347489000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
|
||||
|
|
@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 #
|
|||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 185584000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55961.075070 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52961.075070 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73517493 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 181146000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 3237 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 171435000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3237 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
|
||||
|
|
@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 233870000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_avg_miss_latency 54796.274182 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 51796.274182 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 168271033 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 229432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses 4187 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 221078000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 216871000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 4187 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.802954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3288.899192 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.802957 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3288.911680 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 54796.274182 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 51796.274182 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 168270956 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_hits 168271033 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 229432000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 4264 # number of overall misses
|
||||
system.cpu.dcache.overall_misses 4187 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 221078000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 216871000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 4187 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3288.899192 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3288.911680 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 625 # number of writebacks
|
||||
|
|
@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 3673 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.876526 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1795.124700 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.876529 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1795.130856 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
|
||||
|
|
@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 1769 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1795.124700 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1795.130856 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -164,12 +164,13 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 166504000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 128080000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 166348000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.999063 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 3199 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 127960000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999063 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 3199 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
|
|
@ -180,20 +181,20 @@ system.cpu.l2cache.ReadReq_misses 4038 # nu
|
|||
system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses 35 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 5824000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1820000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4480000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 35 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1400000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.120240 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.125220 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -202,44 +203,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 376480000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 588 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 376324000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.924856 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7237 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 289600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 289480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.924856 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7237 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.101996 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.011352 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3342.203160 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 371.972955 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.103673 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.011078 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3397.172145 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 362.997313 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 585 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7240 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 588 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 376324000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.924856 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7237 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 289600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 289480000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.924856 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7237 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 15 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 14 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4544 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3714.176115 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 3760.169458 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 569 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1134703700 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1134694978 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 398664609 # Number of instructions executed
|
||||
system.cpu.num_refs 174183455 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
|
||||
cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:37:41
|
||||
M5 compiled Aug 26 2010 13:52:30
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:52:33
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
|
||||
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -18,4 +20,4 @@ info: Increasing stack size by one page.
|
|||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.520000
|
||||
Exiting @ tick 525836291000 because target called exit()
|
||||
Exiting @ tick 525827779000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1023413 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 218276 # Number of bytes of host memory used
|
||||
host_seconds 336.52 # Real time elapsed on the host
|
||||
host_tick_rate 1562566741 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 898977 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 219380 # Number of bytes of host memory used
|
||||
host_seconds 383.10 # Real time elapsed on the host
|
||||
host_tick_rate 1372552338 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 344399678 # Number of instructions simulated
|
||||
sim_seconds 0.525836 # Number of seconds simulated
|
||||
sim_ticks 525836291000 # Number of ticks simulated
|
||||
sim_seconds 0.525828 # Number of seconds simulated
|
||||
sim_ticks 525827779000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 94586725 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 49727.442439 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46727.442439 # average ReadReq mshr miss latency
|
||||
|
|
@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 75091000 #
|
|||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1607 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 82063572 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 82060523 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 170744000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000037 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 3049 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 161597000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000037 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3049 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55985.492228 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52985.492228 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 82060677 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 162078000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000035 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2895 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 153393000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2895 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 39438.673365 # Average number of references to valid blocks.
|
||||
|
|
@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 176650297 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 53835.051546 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 50835.051546 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 176645641 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 250656000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000026 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 4656 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 53751.665926 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 50751.665926 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 176645795 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 241990000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 4502 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 236688000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4656 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 228484000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4502 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.751811 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3079.417400 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.751814 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3079.430321 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 176650297 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 53835.051546 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 50835.051546 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 53751.665926 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 50751.665926 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 176645641 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 250656000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000026 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 4656 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 176645795 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 241990000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 4502 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 236688000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4656 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 228484000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4502 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4479 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3079.417400 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3079.430321 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 176645818 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 974 # number of writebacks
|
||||
|
|
@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 15603 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.862302 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1765.994016 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.862305 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1766.000778 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 348627536 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
|
||||
|
|
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 13796 # number of replacements
|
||||
system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1765.994016 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1766.000778 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 348611933 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -150,12 +150,13 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 149344000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 2872 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 114880000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 2872 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 1 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 149292000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.999652 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 2871 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 114840000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999652 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 2871 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 17210 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
|
|
@ -166,20 +167,20 @@ system.cpu.l2cache.ReadReq_misses 3977 # nu
|
|||
system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231087 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 177 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses 23 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 9204000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1196000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 177 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7080000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 23 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 920000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 177 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 23 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 974 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 974 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.776587 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.717391 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 20082 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 13233 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 356148000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.341052 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 6849 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 13234 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 356096000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.341002 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 6848 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 273960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.341052 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 6849 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 273920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.341002 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 6848 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.091337 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.010370 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2992.938866 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 339.814124 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.095645 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.010365 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3134.105136 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 339.639233 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 20082 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 13233 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 356148000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.341052 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 6849 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 13234 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 356096000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.341002 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 6848 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 273960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.341052 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 6849 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 273920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.341002 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 6848 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 48 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4758 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4876 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3332.752990 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 13211 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 3473.744369 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 13250 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1051672582 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1051655558 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 344399678 # Number of instructions executed
|
||||
system.cpu.num_refs 177028576 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -353,7 +353,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -2,3 +2,6 @@ warn: Sockets disabled, not accepting gdb connections
|
|||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(0, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simerr
|
||||
Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jun 6 2010 03:04:38
|
||||
M5 revision ba1a0193c050 7448 default tip
|
||||
M5 started Jun 6 2010 03:07:52
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 12:01:20
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -1392,3 +1392,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 702688811500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,340 +1,340 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 150652 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214040 # Number of bytes of host memory used
|
||||
host_seconds 12101.02 # Real time elapsed on the host
|
||||
host_tick_rate 57884111 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 105247 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214344 # Number of bytes of host memory used
|
||||
host_seconds 17321.56 # Real time elapsed on the host
|
||||
host_tick_rate 40567294 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1823043370 # Number of instructions simulated
|
||||
sim_seconds 0.700457 # Number of seconds simulated
|
||||
sim_ticks 700456762500 # Number of ticks simulated
|
||||
sim_seconds 0.702689 # Number of seconds simulated
|
||||
sim_ticks 702688811500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 237313176 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 290294551 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 3578 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 28357853 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 231827098 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 346133867 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 49328779 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.BTBHits 239396241 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 292393914 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 3599 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 28358143 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 232710596 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 347019771 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 49329086 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 266706457 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 69311011 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 67430429 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1302157693 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.542814 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.203929 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1305107182 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.539328 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.193562 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 596380613 45.80% 45.80% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 273242120 20.98% 66.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 173533589 13.33% 80.11% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 65306568 5.02% 85.13% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 48690140 3.74% 88.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 33944722 2.61% 91.47% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 18456166 1.42% 92.89% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 23292764 1.79% 94.68% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 69311011 5.32% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 596079504 45.67% 45.67% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 274005611 20.99% 66.67% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 176024939 13.49% 80.16% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 67867193 5.20% 85.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 46132467 3.53% 88.89% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 33942844 2.60% 91.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 19726349 1.51% 93.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 23897846 1.83% 94.83% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 67430429 5.17% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1302157693 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1305107182 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 2008987604 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 511595302 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 722390433 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 28346017 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 28346322 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 686852992 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 694586134 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.768448 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.768448 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 9 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 463363512 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 37524.078898 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34794.219854 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 461428955 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 72592469500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.004175 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1934557 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 475286 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 50774196000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003149 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1459271 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 0.770896 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.770896 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 8 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 8 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 463358852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 37466.685698 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34710.185206 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 461425148 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 72449480000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.004173 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1933704 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 474303 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 50656079000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003150 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1459401 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 38582.382670 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36523.414699 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 210235446 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 21584913985 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 559450 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 484668 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2731293998 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 74782 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4879.241379 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 38589.512736 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.349360 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 210236618 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 21543675991 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002648 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 558278 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 484005 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2712773000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000352 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 74273 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6041.666667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 438.740100 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_refs 438.700297 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 141498 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 72500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 14500 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 674158408 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 37761.475202 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34878.514626 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 671664401 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 94177383485 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003699 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2494007 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 959954 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 53505489998 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002276 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1534053 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 674153748 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 37718.232311 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34798.041826 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 671661766 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 93993155991 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003696 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2491982 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 958308 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 53368852000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002275 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1533674 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999780 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.099733 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 674158408 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 37761.475202 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34878.514626 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.104320 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 674153748 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 37718.232311 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34798.041826 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 671664401 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 94177383485 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003699 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2494007 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 959954 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 53505489998 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002276 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1534053 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 671661766 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 93993155991 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003696 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2491982 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 958308 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 53368852000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002275 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1533674 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 1526826 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1530922 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 1526954 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1531050 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.099733 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 671676872 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 274383000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 74589 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 32140341 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 12074 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 30417175 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2923062124 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 711773443 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 558159581 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 98598096 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 45812 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 84328 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 772918649 # DTB accesses
|
||||
system.cpu.dcache.tagsinuse 4095.104320 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 671672090 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 274011000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 74616 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 31207203 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 12052 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 30419221 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2934529925 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 711825403 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 561989361 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 100109049 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 45710 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 85215 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 772921338 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 772293170 # DTB hits
|
||||
system.cpu.dtb.data_misses 625479 # DTB misses
|
||||
system.cpu.dtb.data_hits 772287215 # DTB hits
|
||||
system.cpu.dtb.data_misses 634123 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 514591069 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 514592222 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 514003488 # DTB read hits
|
||||
system.cpu.dtb.read_misses 587581 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 258327580 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 513995856 # DTB read hits
|
||||
system.cpu.dtb.read_misses 596366 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 258329116 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 258289682 # DTB write hits
|
||||
system.cpu.dtb.write_misses 37898 # DTB write misses
|
||||
system.cpu.fetch.Branches 346133867 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 346369631 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 922290632 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 4326238 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3015904698 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 28794725 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.247077 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 346369631 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 286641955 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.152813 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1400755789 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.153055 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.032526 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dtb.write_hits 258291359 # DTB write hits
|
||||
system.cpu.dtb.write_misses 37757 # DTB write misses
|
||||
system.cpu.fetch.Branches 347019771 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 347236210 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 925540339 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 4572630 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3016868050 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 28795074 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.246923 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 347236210 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 288725327 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.146660 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1405216231 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.146907 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.027321 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 824834992 58.88% 58.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 53206817 3.80% 62.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 38924738 2.78% 65.46% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 62366133 4.45% 69.91% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 120532729 8.60% 78.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 35808657 2.56% 81.08% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 38526871 2.75% 83.83% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7024237 0.50% 84.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 219530615 15.67% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 826912311 58.85% 58.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 54085812 3.85% 62.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 40125133 2.86% 65.55% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 63577185 4.52% 70.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 121409089 8.64% 78.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 34600240 2.46% 81.18% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 37932193 2.70% 83.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7024441 0.50% 84.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 219549827 15.62% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1400755789 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 346369631 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 15843.963981 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11642.396973 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 346358970 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 168912500 # number of ReadReq miss cycles
|
||||
system.cpu.fetch.rateDist::total 1405216231 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 347236210 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 15852.092893 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11646.295350 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 347225531 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 169284500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 10661 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 882 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 113851000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 10679 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 894 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 113959000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 9779 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 9785 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 35418.649146 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 35489.118050 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 346369631 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 15843.963981 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11642.396973 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 346358970 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 168912500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 347236210 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 15852.092893 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11646.295350 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 347225531 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 169284500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 10661 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 882 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 113851000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 10679 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 894 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 113959000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 9779 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 9785 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.788131 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1614.092315 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 346369631 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 15843.963981 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11642.396973 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.787162 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1612.107078 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 347236210 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 15852.092893 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11646.295350 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 346358970 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 168912500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 347225531 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 169284500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 10661 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 882 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 113851000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 10679 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 894 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 113959000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 9779 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 9785 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 8106 # number of replacements
|
||||
system.cpu.icache.sampled_refs 9779 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 8113 # number of replacements
|
||||
system.cpu.icache.sampled_refs 9784 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1614.092315 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 346358970 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1612.107078 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 347225531 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 157737 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 273840918 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 328413541 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.427157 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 773454371 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 258328581 # Number of stores executed
|
||||
system.cpu.idleCycles 161393 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 274718833 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 329034713 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.424505 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 773457001 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 258330075 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1628963056 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1998305294 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.696273 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1632862772 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2000954749 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.695811 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1134203072 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.426430 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1999262446 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 30877558 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 3458881 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 652332333 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 52328 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 302847672 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2706062248 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 515125790 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 84024827 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1999323821 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 131467 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1136164328 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.423784 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2001905607 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 30878599 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 3451748 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 655963109 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 64 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 51733 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 302851236 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2713712461 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 515126926 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 84126603 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2001967300 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 131046 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 2941 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 98598096 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 141241 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 1380 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 100109049 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 140868 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 63 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 50635810 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 214 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 50632865 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 227 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 3618 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 4111 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 140737031 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 92052541 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 3618 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 787831 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 30089727 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.301325 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.301325 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 3782 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 4125 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 144367807 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 92056105 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 3782 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 787958 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 30090641 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.297191 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.297191 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1201800948 57.69% 57.69% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 17591 0.00% 57.69% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.69% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851361 1.34% 59.02% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254692 0.40% 59.42% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.35% 59.77% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.77% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.77% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.77% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 555085010 26.64% 86.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 283131644 13.59% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1203926458 57.71% 57.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 17656 0.00% 57.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851408 1.34% 59.05% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254704 0.40% 59.44% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.35% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 555703221 26.64% 86.43% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 283133054 13.57% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 2083348648 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 37044117 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.017781 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 2086093903 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 35524455 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.017029 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 7263 0.02% 0.02% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 27908776 75.34% 75.36% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 9128078 24.64% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 5029 0.01% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 26764066 75.34% 75.35% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 8755360 24.65% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1400755789 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.487303 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.636763 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1405216231 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.484536 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637275 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 530170444 37.85% 37.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 284246633 20.29% 58.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 272843485 19.48% 77.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 155156600 11.08% 88.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 63055400 4.50% 93.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 50914622 3.63% 96.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 32393130 2.31% 99.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 9012045 0.64% 99.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 2963430 0.21% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 532926303 37.92% 37.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 283749414 20.19% 58.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 275573113 19.61% 77.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 156459284 11.13% 88.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 63140415 4.49% 93.36% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 47210297 3.36% 96.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 32913048 2.34% 99.06% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 10225878 0.73% 99.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 3018479 0.21% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1400755789 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.487136 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2377648640 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2083348648 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 554578210 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 12403574 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 512095612 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1405216231 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.484365 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2384677684 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2086093903 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 561606840 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 12399741 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 517624785 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 346369835 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 347236419 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 346369631 # ITB hits
|
||||
system.cpu.itb.fetch_misses 204 # ITB misses
|
||||
system.cpu.itb.fetch_hits 347236210 # ITB hits
|
||||
system.cpu.itb.fetch_misses 209 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
|
|
@ -343,106 +343,106 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 71651 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.884984 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.644583 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2514297000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 71649 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 35091.445798 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.513824 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2514267000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 71651 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297535500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 71649 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297462000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 71651 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1469050 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34290.352977 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.454128 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 28927 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 49382326000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.980309 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1440123 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 44644467000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980309 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1440123 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 3136 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34061.702806 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.830357 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 106817500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 71649 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1469186 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34207.393582 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.426347 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 29045 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 49263470000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.980231 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1440141 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 44644985000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980231 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1440141 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 2624 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34296.875000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31001.905488 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 89995000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 3136 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97331500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 2624 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 81349000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 3136 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6458.333333 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 2624 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 74616 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 74616 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7200 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.023460 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.023753 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 77500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 36000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 1540701 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34328.294441 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.939162 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 28927 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 51896623000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.981225 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1511774 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 1540835 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34249.291899 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.904557 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 29045 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 51777737000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.981150 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1511790 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 46942002500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.981225 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1511774 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 46942447000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.981150 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1511790 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.927763 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.046370 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 30400.923469 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 1519.457016 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 1540701 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34328.294441 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.939162 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.927958 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.046323 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 30407.323461 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 1517.897239 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 1540835 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34249.291899 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.904557 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 28927 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 51896623000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.981225 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1511774 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 29045 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 51777737000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.981150 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1511790 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 46942002500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.981225 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1511774 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 46942447000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.981150 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1511790 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 1474248 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1506806 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 1474292 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1506959 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 31920.380484 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 35349 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 31925.220700 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 35795 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 66899 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 118618588 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 21042992 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 652332333 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 302847672 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 1400913526 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 20115016 # Number of cycles rename is blocking
|
||||
system.cpu.memDep0.conflictingLoads 126385471 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 12290638 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 655963109 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 302851236 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 1405377624 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 20016233 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 673890 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 725392322 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 11324949 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:IQFullEvents 673555 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 725805122 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 10749358 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 3294871470 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2827359257 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1880881832 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 543088621 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 98598096 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 13538505 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 495912762 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 23229 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 2930 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 27590681 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 73 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 4075 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:RenameLookups 3307765426 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2838518766 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1890285688 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 546657671 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 100109049 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 12606278 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 505316618 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 21878 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 2883 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 26993135 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 69 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 4180 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -152,12 +152,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cwd=build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -2,3 +2,6 @@ warn: Sockets disabled, not accepting gdb connections
|
|||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(0, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 24 2010 23:12:54
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 01:51:28
|
||||
M5 executing on SC2B0619
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 11:52:14
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -1390,3 +1392,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 2814926000000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1237577 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 198020 # Number of bytes of host memory used
|
||||
host_seconds 1623.32 # Real time elapsed on the host
|
||||
host_tick_rate 1734066560 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1265087 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213100 # Number of bytes of host memory used
|
||||
host_seconds 1588.02 # Real time elapsed on the host
|
||||
host_tick_rate 1772597573 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_seconds 2.814951 # Number of seconds simulated
|
||||
sim_ticks 2814951154000 # Number of ticks simulated
|
||||
sim_seconds 2.814926 # Number of seconds simulated
|
||||
sim_ticks 2814926000000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 55392.232299 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.232299 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 55392.203496 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.203496 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 80772510000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 80772468000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 76397934000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 76397892000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.692460 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.692460 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 210720109 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 4188049000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000355 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 74787 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3963688000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 210720566 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 4162480000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000353 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 74330 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3939490000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000353 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 74330 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 55421.867488 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 84960559000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 55421.682690 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52421.682690 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 720332400 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 84934948000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002123 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1532522 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 80361622000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 80337382000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002123 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1532522 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999804 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.198740 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.999806 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.205038 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 55421.682690 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52421.682690 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 720331943 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 84960559000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1532979 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 720332400 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 84934948000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002123 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1532522 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 80361622000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 80337382000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002123 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1532522 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 1526048 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.198740 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4095.205038 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 1054514000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 74589 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 1049839000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 74616 # number of writebacks
|
||||
system.cpu.dtb.data_accesses 722298387 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 721864922 # DTB hits
|
||||
|
|
@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 10596 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.721885 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1478.420115 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.721886 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1478.422015 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
|
||||
|
|
@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 9046 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1478.420115 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1478.422015 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -173,27 +173,27 @@ system.cpu.l2cache.ReadExReq_mshr_misses 71952 # nu
|
|||
system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 29320 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 74852336000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.980038 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1439468 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 57578720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980038 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51578.130511 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 29321 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 74852284000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.980037 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1439467 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 57578680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980037 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1439467 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 2378 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 146224000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 123656000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 2835 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113400000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 2378 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 95120000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 2378 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 74616 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 74616 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.023744 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.023963 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -202,44 +202,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 29320 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 78593840000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_hits 29321 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 78593788000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1511420 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses 1511419 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 60456800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 60456760000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1511420 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 1511419 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.926943 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.046880 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 30374.076068 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 1536.161417 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.927128 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.046829 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 30380.118149 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 1534.487101 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 29320 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 78593840000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_hits 29321 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 78593788000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1511420 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses 1511419 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 60456800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 60456760000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 1511419 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 1473608 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 1473631 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1506296 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 31910.237485 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 35763 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 31914.605250 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 36095 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 66899 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5629902308 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5629852000 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2008987605 # Number of instructions executed
|
||||
system.cpu.num_refs 722823898 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
|
||||
cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:43:18
|
||||
M5 compiled Aug 26 2010 13:52:30
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 14:03:19
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
|
||||
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -1390,4 +1392,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 2371369572000 because target called exit()
|
||||
Exiting @ tick 2371349716000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1398740 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215468 # Number of bytes of host memory used
|
||||
host_seconds 1310.23 # Real time elapsed on the host
|
||||
host_tick_rate 1809883950 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1110314 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 216744 # Number of bytes of host memory used
|
||||
host_seconds 1650.59 # Real time elapsed on the host
|
||||
host_tick_rate 1436666087 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1832675505 # Number of instructions simulated
|
||||
sim_seconds 2.371370 # Number of seconds simulated
|
||||
sim_ticks 2371369572000 # Number of ticks simulated
|
||||
sim_seconds 2.371350 # Number of seconds simulated
|
||||
sim_ticks 2371349716000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 620364065 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 55313.788145 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52313.788145 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 55313.730657 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52313.730657 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 618902904 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 80822350000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 80822266000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1461161 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 76438867000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 76438783000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1461161 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 276945663 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.799022 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.799022 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 276871028 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 4179545000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 74635 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3955640000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 74635 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.434541 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.434541 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 276871387 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 4159414000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000268 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 74276 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3936586000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000268 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 74276 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 583.970170 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 897309728 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 55347.126181 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52347.126181 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 895773932 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 85001895000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.001712 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1535796 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 55346.901240 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52346.901240 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 895774291 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 84981680000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.001711 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1535437 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 80394507000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.001712 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1535796 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 80375369000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.001711 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1535437 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999747 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4094.964018 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.999748 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4094.966832 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 897309728 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 55347.126181 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52347.126181 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 55346.901240 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52346.901240 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 895773932 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 85001895000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.001712 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1535796 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 895774291 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 84981680000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.001711 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1535437 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 80394507000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.001712 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1535796 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 80375369000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.001711 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1535437 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 1529845 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1533941 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.964018 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.966832 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 895775787 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 995704000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 74508 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 993999000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 74582 # number of writebacks
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 19803 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.679846 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1392.324951 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.679847 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1392.325794 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1390241555 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 18784.729586 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 15784.729586 # average overall mshr miss latency
|
||||
|
|
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 18364 # number of replacements
|
||||
system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1392.324951 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1392.325794 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1390221752 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -150,36 +150,37 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3784560000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 72780 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2911200000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 72780 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 1 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3784508000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.999986 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 72779 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2911160000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999986 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 72779 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1480964 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 41420 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 74856288000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.972032 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1439544 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 57581760000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.972032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1439544 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 1855 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51579.514825 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 41422 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 74856184000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.972030 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1439542 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 57581680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.972030 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1439542 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 1496 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 95680000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 77792000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 1855 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 74200000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 1496 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 59840000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 1855 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 74508 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 74508 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 1496 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 74582 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 74582 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.032124 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.032374 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 1553744 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 41420 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 78640848000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.973342 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1512324 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 41423 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 78640692000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.973340 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1512321 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 60492960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.973342 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1512324 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 60492840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.973340 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1512321 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.927309 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.046837 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 30386.057269 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 1534.770026 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.927467 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.046803 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 30391.242944 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 1533.635543 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 1553744 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 41420 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 78640848000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.973342 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1512324 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 41423 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 78640692000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.973340 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1512321 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 60492960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.973342 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1512324 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 60492840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.973340 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1512321 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 1472870 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1505525 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 1472894 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1505603 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 31920.827295 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 48363 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 31924.878487 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 48742 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 66101 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 4742739144 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4742699432 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1832675505 # Number of instructions executed
|
||||
system.cpu.num_refs 908401146 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -186,7 +186,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -4,3 +4,6 @@ warn: Prefetching currently unimplemented
|
|||
For more information see: http://www.m5sim.org/warn/8028fa22
|
||||
warn: Write Hints currently unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/cfb3293b
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jun 25 2010 15:39:41
|
||||
M5 revision 93b1ca421839+ 7482+ default qtip tip update_regr
|
||||
M5 started Jun 25 2010 16:11:25
|
||||
M5 executing on zooks
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 11:52:06
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 104900991500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 46297 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 167032 # Number of bytes of host memory used
|
||||
host_seconds 1908.12 # Real time elapsed on the host
|
||||
host_tick_rate 55055354 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 31368 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 223704 # Number of bytes of host memory used
|
||||
host_seconds 2816.26 # Real time elapsed on the host
|
||||
host_tick_rate 37248320 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_seconds 0.105052 # Number of seconds simulated
|
||||
sim_ticks 105052358500 # Number of ticks simulated
|
||||
sim_seconds 0.104901 # Number of seconds simulated
|
||||
sim_ticks 104900991500 # Number of ticks simulated
|
||||
system.cpu.AGEN-Unit.agens 35224018 # Number of Address Generations
|
||||
system.cpu.Branch-Predictor.BTBHitPct 41.015608 # BTB Hit Percentage
|
||||
system.cpu.Branch-Predictor.BTBHits 4719981 # Number of BTB hits
|
||||
|
|
@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 434959
|
|||
system.cpu.Execution-Unit.predictedTakenIncorrect 217237 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.Mult-Div-Unit.multiplies 41101 # Number of Multipy Operations Executed
|
||||
system.cpu.RegFile-Manager.regFileAccesses 156428920 # Number of Total Accesses (Read+Write) to the Register File
|
||||
system.cpu.RegFile-Manager.regFileReads 103882039 # Number of Reads from Register File
|
||||
system.cpu.RegFile-Manager.regFileAccesses 156429013 # Number of Total Accesses (Read+Write) to the Register File
|
||||
system.cpu.RegFile-Manager.regFileReads 103882132 # Number of Reads from Register File
|
||||
system.cpu.RegFile-Manager.regFileWrites 52546881 # Number of Writes to Register File
|
||||
system.cpu.RegFile-Manager.regForwards 2136326 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.activity 84.633296 # Percentage of cycles cpu is active
|
||||
system.cpu.RegFile-Manager.regForwards 2136233 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.activity 84.755939 # Percentage of cycles cpu is active
|
||||
system.cpu.comBranches 13754477 # Number of Branches instructions committed
|
||||
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
|
||||
system.cpu.comInts 30457224 # Number of Integer instructions committed
|
||||
|
|
@ -42,28 +42,28 @@ system.cpu.comStores 14844619 # Nu
|
|||
system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread)
|
||||
system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total)
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.cpi 2.378346 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi_total 2.378346 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 2.374919 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi_total 2.374919 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 38171.526841 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35064.773064 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 38051.171708 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34943.916006 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2319531000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 2312217500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2130746000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2123402000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56426.999259 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53426.999259 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 8452369500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 8002990500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56416.363760 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53416.289024 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 14466192 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 8303642500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010072 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 147185 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7862076500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010072 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 147185 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||
|
|
@ -73,42 +73,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 51158.585005 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 48127.776538 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 10771900500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 51049.814620 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 48018.420205 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 34682064 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 10615860000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005960 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 207951 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10133736500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 9985478500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005960 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 207951 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.995308 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4076.781631 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.995330 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4076.871208 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 51158.585005 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 48127.776538 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 51049.814620 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 48018.420205 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 34679456 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 10771900500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 210559 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 34682064 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 10615860000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005960 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 207951 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10133736500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 9985478500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005960 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 207951 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 200248 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4076.781631 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4076.871208 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 838762000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147714 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 834930000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 149164 # number of writebacks
|
||||
system.cpu.dtb.data_accesses 34987415 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 34890015 # DTB hits
|
||||
|
|
@ -126,14 +126,14 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 14613377 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 97023272 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 19069.814885 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15852.089330 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 19062.290643 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15844.379626 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 96943862 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1514334000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1513736500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000818 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 79410 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1586 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1233673000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1233073000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000802 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 77824 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
|
|
@ -145,31 +145,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 4000 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 97023272 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 19069.814885 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 15852.089330 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 19062.290643 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 15844.379626 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 96943862 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1514334000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1513736500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000818 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 79410 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1586 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 1233673000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 1233073000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000802 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 77824 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.914669 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1873.241202 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.914717 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1873.340733 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 97023272 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 19069.814885 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 15852.089330 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 19062.290643 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 15844.379626 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 96943862 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1514334000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1513736500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000818 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 79410 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1586 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 1233673000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 1233073000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000802 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 77824 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 75778 # number of replacements
|
||||
system.cpu.icache.sampled_refs 77824 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1873.241202 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1873.340733 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 96943862 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 32286171 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.ipc 0.420460 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.ipc_total 0.420460 # IPC: Total IPC of All Threads
|
||||
system.cpu.idleCycles 31982342 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.ipc 0.421067 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.ipc_total 0.421067 # IPC: Total IPC of All Threads
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
|
|
@ -201,104 +201,105 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52436.396941 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.233323 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 7528713000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743153500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52436.707450 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.226443 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 54 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 7525926000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.999624 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 143524 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5740992500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999624 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143524 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 138590 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52301.497653 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.842643 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 95122 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2273441500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.313645 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 43468 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1738930500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313645 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 43468 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51889.300080 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.654867 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 322492000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52302.271309 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.863791 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 95311 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2263590000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.312281 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 43279 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1731370500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.312281 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 43279 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 3607 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51817.854172 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.356529 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 186907000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248616500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 3607 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 144288500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 3607 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 149164 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 149164 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.637249 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.646134 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 282168 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52405.047421 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.304492 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 95122 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9802154500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.662889 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 187046 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52405.560939 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.300836 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 95365 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9789516000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.662028 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 186803 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 7482084000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.662889 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 187046 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 7472363000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.662028 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 186803 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.083128 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.473986 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2723.922410 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15531.583322 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.089575 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.471967 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2935.193659 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15465.399858 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 282168 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52405.047421 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.304492 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52405.560939 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.300836 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 95122 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9802154500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.662889 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 187046 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 95365 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9789516000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.662028 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 186803 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 7482084000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.662889 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 187046 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 7472363000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.662028 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 186803 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 147731 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 172937 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 147725 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 173054 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18255.505732 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 110204 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 18400.593517 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 111816 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 120636 # number of writebacks
|
||||
system.cpu.numCycles 210104718 # number of cpu cycles simulated
|
||||
system.cpu.runCycles 177818547 # Number of cycles cpu stages are processed.
|
||||
system.cpu.l2cache.writebacks 120606 # number of writebacks
|
||||
system.cpu.numCycles 209801984 # number of cpu cycles simulated
|
||||
system.cpu.runCycles 177819642 # Number of cycles cpu stages are processed.
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
|
||||
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
|
||||
system.cpu.stage-0.idleCycles 113077434 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-0.idleCycles 112774700 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-0.runCycles 97027284 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage-0.utilization 46.180440 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-1.idleCycles 121740642 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-1.runCycles 88364076 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage-1.utilization 42.057159 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-2.idleCycles 120288932 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-0.utilization 46.247076 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-1.idleCycles 121437923 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-1.runCycles 88364061 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage-1.utilization 42.117839 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-2.idleCycles 119986198 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage-2.utilization 42.748105 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-3.idleCycles 174873448 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-2.utilization 42.809789 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-3.idleCycles 174570714 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-3.runCycles 35231270 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage-3.utilization 16.768434 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-4.idleCycles 121764045 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-3.utilization 16.792630 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-4.idleCycles 121461311 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-4.runCycles 88340673 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage-4.utilization 42.046021 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.threadCycles 210104718 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.stage-4.utilization 42.106691 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.threadCycles 209801984 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -353,7 +353,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,2 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simerr
|
||||
Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,11 +7,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jun 6 2010 03:04:38
|
||||
M5 revision ba1a0193c050 7448 default tip
|
||||
M5 started Jun 6 2010 03:07:19
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 11:53:46
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 27109454000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,340 +1,340 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 172331 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 216300 # Number of bytes of host memory used
|
||||
host_seconds 461.86 # Real time elapsed on the host
|
||||
host_tick_rate 58843672 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 111480 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 216720 # Number of bytes of host memory used
|
||||
host_seconds 713.95 # Real time elapsed on the host
|
||||
host_tick_rate 37970836 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_seconds 0.027177 # Number of seconds simulated
|
||||
sim_ticks 27177245500 # Number of ticks simulated
|
||||
sim_seconds 0.027109 # Number of seconds simulated
|
||||
sim_ticks 27109454000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 8069483 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 14149168 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 34397 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 454823 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 10566027 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 16273288 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 1942431 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.BTBHits 8023938 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 14145639 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 34256 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 455419 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 10571328 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 16274912 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 1940184 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 13754477 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 3319944 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 3318027 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 51827032 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.704529 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.326613 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 51708884 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.708423 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.329205 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 22597378 43.60% 43.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 11350095 21.90% 65.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 5102840 9.85% 75.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 3559000 6.87% 82.21% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 2567186 4.95% 87.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 1515845 2.92% 90.09% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 1002832 1.93% 92.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 811912 1.57% 93.59% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 3319944 6.41% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 22519798 43.55% 43.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 11308699 21.87% 65.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 5100268 9.86% 75.28% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 3555628 6.88% 82.16% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 2564108 4.96% 87.12% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 1506181 2.91% 90.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 1020225 1.97% 92.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 815950 1.58% 93.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 3318027 6.42% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 51827032 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 51708884 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 88340672 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 20379399 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 359545 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 360224 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 8408904 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 8384811 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.682916 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.682916 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 0.681213 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.681213 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 20447523 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 30372.255855 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20950.835512 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20297704 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4550341000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.007327 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 149819 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 88240 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1290131500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003012 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61579 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 20456575 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 30286.204567 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20855.715214 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20307098 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4527091000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.007307 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 149477 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 87887 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1284503500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003011 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61590 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 32253.546396 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35751.235092 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 13562946 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 33880124994 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.071881 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1050431 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 900647 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5354962997 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 149784 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3083 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 32227.418613 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35731.214318 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 13566176 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 33748584999 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.071660 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1047201 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 900041 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5258205499 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010070 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 147160 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 165.176300 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_refs 165.209324 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 18498 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 35060900 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 32018.717762 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 31439.251416 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 33860650 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 38430465994 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.034233 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1200250 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 988887 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 6645094497 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006028 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 211363 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 35069952 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 31984.941646 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 33873274 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 38275675999 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.034123 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1196678 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 987928 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 6542708999 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005952 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 208750 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.995485 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4077.505020 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 35060900 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 32018.717762 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 31439.251416 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.995492 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4077.536069 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 35069952 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 31984.941646 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 33860650 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 38430465994 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.034233 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1200250 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 988887 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 6645094497 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006028 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 211363 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 33873274 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 38275675999 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.034123 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1196678 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 987928 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 6542708999 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005952 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 208750 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 200975 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 205071 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 200988 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 205084 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4077.505020 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33872869 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 182118000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147751 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 3544786 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 96141 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3662025 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 101883380 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 28549595 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 19586782 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1306643 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 281833 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 145869 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 36634667 # DTB accesses
|
||||
system.cpu.dtb.data_acv 32 # DTB access violations
|
||||
system.cpu.dtb.data_hits 36459913 # DTB hits
|
||||
system.cpu.dtb.data_misses 174754 # DTB misses
|
||||
system.cpu.dcache.tagsinuse 4077.536069 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33881789 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 181403000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 149251 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 3489554 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 96109 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3659886 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 101890177 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 28536030 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 19538571 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1305079 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 281240 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 144729 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 36643462 # DTB accesses
|
||||
system.cpu.dtb.data_acv 34 # DTB access violations
|
||||
system.cpu.dtb.data_hits 36467174 # DTB hits
|
||||
system.cpu.dtb.data_misses 176288 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 21560876 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 29 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 21402283 # DTB read hits
|
||||
system.cpu.dtb.read_misses 158593 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 15073791 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 3 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 15057630 # DTB write hits
|
||||
system.cpu.dtb.write_misses 16161 # DTB write misses
|
||||
system.cpu.fetch.Branches 16273288 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 13390069 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 33318554 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 152706 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 103441312 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 571617 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.299392 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 13390069 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 10011914 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.903087 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 53133675 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.946813 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.939021 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dtb.read_accesses 21569273 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 32 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 21411172 # DTB read hits
|
||||
system.cpu.dtb.read_misses 158101 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 15074189 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 2 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 15056002 # DTB write hits
|
||||
system.cpu.dtb.write_misses 18187 # DTB write misses
|
||||
system.cpu.fetch.Branches 16274912 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 13386326 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 33268098 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 152194 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 103463438 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 573170 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.300170 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 13386326 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 9964122 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.908254 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 53013963 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.951626 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.945013 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 33232285 62.54% 62.54% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1906283 3.59% 66.13% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1507954 2.84% 68.97% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 1896878 3.57% 72.54% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 3940139 7.42% 79.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1882924 3.54% 83.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 690153 1.30% 84.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1104079 2.08% 86.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 6972980 13.12% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 33159204 62.55% 62.55% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1896528 3.58% 66.13% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1503537 2.84% 68.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 1853022 3.50% 72.46% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 3942692 7.44% 79.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1853723 3.50% 83.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 688430 1.30% 84.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1103809 2.08% 86.77% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 7013018 13.23% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 53133675 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 13390069 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9552.030813 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6056.454886 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 13301016 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 850637000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.006651 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 89053 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 2816 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 522290500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.006440 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 86237 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 53013963 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 13386326 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9552.485505 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6054.988859 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 13297330 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 850133000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.006648 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 88996 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 2824 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 521770500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.006437 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 86172 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 154.239714 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 154.313284 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 13390069 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9552.030813 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6056.454886 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 13301016 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 850637000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.006651 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 89053 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 2816 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 522290500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.006440 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 86237 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 13386326 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9552.485505 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6054.988859 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 13297330 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 850133000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.006648 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 88996 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 2824 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 521770500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.006437 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 86172 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.936831 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1918.630870 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 13390069 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9552.030813 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6056.454886 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.936859 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1918.688120 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 13386326 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9552.485505 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6054.988859 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 13301016 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 850637000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.006651 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 89053 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 2816 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 522290500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.006440 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 86237 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 13297330 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 850133000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.006648 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 88996 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 2824 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 521770500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.006437 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 86172 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 84189 # number of replacements
|
||||
system.cpu.icache.sampled_refs 86236 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 84124 # number of replacements
|
||||
system.cpu.icache.sampled_refs 86171 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1918.630870 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 13301016 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1918.688120 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 13297330 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 1220817 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14763362 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 9403936 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.562245 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 36977571 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 15306943 # Number of stores executed
|
||||
system.cpu.idleCycles 1204946 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14764091 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 9400465 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.566510 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 36986360 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 15307304 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 42200934 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 84440980 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.765693 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 42224308 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 84456261 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.765793 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 32312963 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.553523 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 84676788 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 400577 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 625766 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 23022182 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 5008 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 344811 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 16353481 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 99092373 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 21670628 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 531948 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 84915051 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 11175 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 32335073 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.557690 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 84693859 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 401805 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 605778 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 23014883 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 5009 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 349401 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 16347988 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 99082046 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 21679056 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 539226 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 84934458 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 11054 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 9016 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1306643 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 43564 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 8978 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1305079 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 42917 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 953335 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 730 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 953186 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 19282 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1358 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2642783 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1508862 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 19282 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 131988 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 268589 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.464309 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.464309 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 20710 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1355 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2635484 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1503369 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 20710 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 131758 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 270047 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.467970 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.467970 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 47956060 56.12% 56.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 42959 0.05% 56.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 47968991 56.12% 56.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 42906 0.05% 56.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122263 0.14% 56.32% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.32% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122397 0.14% 56.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 52 0.00% 56.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38515 0.05% 56.51% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.51% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 21777529 25.49% 81.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 15387138 18.01% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122147 0.14% 56.31% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.31% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122353 0.14% 56.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38520 0.05% 56.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 21790369 25.49% 82.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 15388261 18.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 85446999 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 982918 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011503 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 85473684 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 995540 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011647 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 100696 10.24% 10.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 446429 45.42% 55.66% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 435793 44.34% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 102737 10.32% 10.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 453943 45.60% 55.92% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 438860 44.08% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 53133675 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.608151 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.716289 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 53013963 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.612286 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.719350 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 17599811 33.12% 33.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 14135768 26.60% 59.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 8101815 15.25% 74.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 4767583 8.97% 83.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 4587960 8.63% 92.58% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 2114458 3.98% 96.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 1132800 2.13% 98.69% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 463918 0.87% 99.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 229562 0.43% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 17564950 33.13% 33.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 14012876 26.43% 59.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 8103290 15.29% 74.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 4796735 9.05% 83.90% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 4597424 8.67% 92.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 2085134 3.93% 96.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 1155738 2.18% 98.68% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 468299 0.88% 99.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 229517 0.43% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 53133675 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.572032 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 89683429 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 85446999 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 5008 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 9879316 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 48902 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 6828439 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 53013963 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.576455 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 89676572 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 85473684 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 5009 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 9869392 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 46778 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 6797277 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 13417164 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 13413339 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 13390069 # ITB hits
|
||||
system.cpu.itb.fetch_misses 27095 # ITB misses
|
||||
system.cpu.itb.fetch_hits 13386326 # ITB hits
|
||||
system.cpu.itb.fetch_misses 27013 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
|
|
@ -343,106 +343,107 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 143493 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.441443 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.837093 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 4926895499 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 143493 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481550000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143493 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 147815 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34139.493240 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.309786 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 103139 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1525216000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.302243 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 44676 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1386533500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302243 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 44676 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 6336 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34034.485480 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31031.960227 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 215642500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 143495 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.046084 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.824393 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 61 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 4924813000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.999575 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 143434 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4479705500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999575 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143434 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 147761 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34138.356934 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.221173 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 103271 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1518815500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.301094 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 44490 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1380712500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.301094 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 44490 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 3671 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 33969.081994 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31027.649142 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 124700500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 6336 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196618500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 3671 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113902500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 6336 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147751 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 147751 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 3671 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 149251 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 149251 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.679657 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.688286 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 291308 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34288.918467 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.176623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 103139 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 6452111499 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.645945 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 188169 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 291256 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34288.480982 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 103332 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 6443628500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.645219 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 187924 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 5868083500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.645945 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 188169 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 5860418000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.645219 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 187924 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.090420 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.474090 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2962.888778 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15534.990261 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 291308 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34288.918467 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.176623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.096999 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.471977 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3178.468873 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15465.728229 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 291256 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34288.480982 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 103139 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 6452111499 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.645945 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 188169 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 103332 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 6443628500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.645219 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 187924 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 5868083500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.645945 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 188169 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 5860418000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.645219 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 187924 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 148882 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 174101 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 148884 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 174227 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18497.879039 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 118329 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 18644.197102 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 119918 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 120652 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 12671277 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 11281308 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 23022182 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 16353481 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 54354492 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 2040280 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.writebacks 120621 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 12607383 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 11255649 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 23014883 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 16347988 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 54218909 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 2001211 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 60824 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 28947603 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1285549 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 34 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 121774399 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 101069730 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 60794101 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 19336245 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1306643 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 1420628 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 8247220 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 82276 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 5281 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 2797354 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 5278 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 42409 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 58273 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 28932787 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1273359 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 32 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 121782078 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 101070010 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 60804975 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 19289152 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1305079 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 1405067 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 8258094 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 80667 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 5283 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 2766751 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 5281 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 41950 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -152,12 +152,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,2 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 24 2010 23:12:40
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 02:21:01
|
||||
M5 executing on SC2B0619
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 11:57:42
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 135015129000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1182325 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 200332 # Number of bytes of host memory used
|
||||
host_seconds 74.72 # Real time elapsed on the host
|
||||
host_tick_rate 1809050434 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1159310 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215356 # Number of bytes of host memory used
|
||||
host_seconds 76.20 # Real time elapsed on the host
|
||||
host_tick_rate 1771821789 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_seconds 0.135169 # Number of seconds simulated
|
||||
sim_ticks 135168766000 # Number of ticks simulated
|
||||
sim_seconds 0.135015 # Number of seconds simulated
|
||||
sim_ticks 135015129000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 37754.336306 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34754.336306 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 2294180000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2111882000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55984.400584 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52984.400584 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 14466192 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 8240064000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010072 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 147185 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7798509000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010072 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 147185 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 50657.337546 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 47657.337546 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 34682064 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 10534244000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005960 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 207951 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 9910391000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005960 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 207951 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.995818 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4078.872537 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.995838 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4078.950714 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 50657.337546 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 47657.337546 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 34679456 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 210559 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 34682064 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 10534244000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005960 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 207951 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 9910391000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005960 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 207951 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 200248 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4078.950714 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147714 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 943578000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 149164 # number of writebacks
|
||||
system.cpu.dtb.data_accesses 34987415 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 34890015 # DTB hits
|
||||
|
|
@ -90,13 +90,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 14613377 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 18802.449108 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15802.449108 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1437184000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1207876000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
|
|
@ -108,31 +108,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 18802.449108 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 15802.449108 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1437184000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 1207876000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.913950 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1871.768668 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.913991 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1871.853872 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 18802.449108 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 15802.449108 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 88361638 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1437184000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 76436 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 1207876000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 74391 # number of replacements
|
||||
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1871.853872 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -164,36 +164,37 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 54 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 7463248000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.999624 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 143524 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5740960000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999624 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143524 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 94094 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2241616000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.314194 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 43108 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1724320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.314194 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 43108 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 3607 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51596.340449 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 186108000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 3607 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 144280000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 3607 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 149164 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 149164 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.639727 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -202,44 +203,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 94148 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9704864000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.664691 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 186632 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 7465280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.664691 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 186632 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.081795 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.475328 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2680.267907 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15575.557767 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.088307 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.473299 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2893.659899 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15509.045444 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 93905 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 186875 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 94148 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9704864000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.664691 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 186632 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 7465280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.664691 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 186632 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 147561 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 147555 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 172883 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 18402.705343 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 110598 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 120634 # number of writebacks
|
||||
system.cpu.l2cache.writebacks 120604 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 270337532 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 270030258 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 88340673 # Number of instructions executed
|
||||
system.cpu.num_refs 35321418 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
|
||||
cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,12 +7,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:39:36
|
||||
M5 compiled Aug 26 2010 13:52:30
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:53:04
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
|
||||
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 133556162000 because target called exit()
|
||||
Exiting @ tick 133464153000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1745846 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 217668 # Number of bytes of host memory used
|
||||
host_seconds 56.13 # Real time elapsed on the host
|
||||
host_tick_rate 2379327214 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1245224 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 218772 # Number of bytes of host memory used
|
||||
host_seconds 78.70 # Real time elapsed on the host
|
||||
host_tick_rate 1695886374 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 97997303 # Number of instructions simulated
|
||||
sim_seconds 0.133556 # Number of seconds simulated
|
||||
sim_ticks 133556162000 # Number of ticks simulated
|
||||
sim_seconds 0.133464 # Number of seconds simulated
|
||||
sim_ticks 133464153000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 27164439 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 35927.990796 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32927.990796 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 35865.411818 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32865.411818 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 27111418 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1904938000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 1901620000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 53021 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1745875000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1742557000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001952 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 53021 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 19865820 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.910387 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.910387 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 19754229 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 6249086000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005617 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 111591 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5914313000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005617 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 111591 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55969.020638 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52969.020638 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 19755779 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 6158887000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005539 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 110041 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5828764000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005539 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 110041 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 292.838112 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 47030259 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 49534.809127 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 46534.809127 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 46865647 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 8154024000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003500 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 164612 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 49432.160773 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 46432.160773 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 46867197 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 8060507000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003467 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 163062 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7660188000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.003500 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 164612 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7571321000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.003467 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 163062 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.995356 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4076.978068 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.995361 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4076.997954 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 47030259 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 49534.809127 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 46534.809127 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 49432.160773 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 46432.160773 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 46865647 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 8154024000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003500 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 164612 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 46867197 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 8060507000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003467 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 163062 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7660188000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.003500 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 164612 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7571321000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.003467 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 163062 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 155959 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 160055 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4076.978068 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4076.997954 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 46870204 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 1080546000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 109433 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 1079446000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 110614 # number of writebacks
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -83,13 +83,13 @@ system.cpu.dtb.write_accesses 0 # DT
|
|||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 78097320 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24226.782314 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21226.782314 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24224.561032 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21224.561032 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 78078412 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 458080000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 458038000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000242 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 401356000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 401314000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 18908 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
|
|
@ -101,31 +101,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 78097320 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 24226.782314 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 21226.782314 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 24224.561032 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 21224.561032 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 78078412 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 458080000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 458038000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000242 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 401356000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 401314000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 18908 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.847875 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1736.448416 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.847896 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1736.491216 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 78097320 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 24226.782314 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 21226.782314 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 24224.561032 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 21224.561032 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 78078412 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 458080000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 458038000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000242 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 18908 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 401356000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 401314000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 18908 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 16890 # number of replacements
|
||||
system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1736.448416 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1736.491216 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 78078412 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -150,36 +150,37 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.l2cache.ReadExReq_accesses 107034 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5565768000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 107034 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4281360000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 107034 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 81 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5561556000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.999243 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 106953 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4278120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999243 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 106953 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 71929 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 39643 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1678872000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.448859 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 32286 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1291440000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.448859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32286 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 4557 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51885.889840 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 39723 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1674712000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.447747 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 32206 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1288240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.447747 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32206 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 3007 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51878.949119 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 236444000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 156000000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 4557 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 182280000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 3007 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 120280000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 4557 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 109433 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 109433 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 3007 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 110614 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 110614 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.358187 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.368048 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 178963 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 39643 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 7244640000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.778485 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 139320 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 39804 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 7236268000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.777585 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 139159 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 5572800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.778485 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 139320 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 5566360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.777585 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 139159 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.064995 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.477989 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2129.749713 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15662.741873 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.070819 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.476669 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2320.602092 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15619.501011 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 178963 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 39643 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 7244640000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.778485 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 139320 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 39804 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 7236268000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.777585 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 139159 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 5572800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.778485 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 139320 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 5566360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.777585 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 139159 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 114093 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 132791 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 114078 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 132866 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 17792.491585 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 47564 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 17940.103104 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 48901 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 88579 # number of writebacks
|
||||
system.cpu.l2cache.writebacks 88549 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 267112324 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 266928306 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 97997303 # Number of instructions executed
|
||||
system.cpu.num_refs 47871034 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,12 +152,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex bendian.raw
|
||||
cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
|
||||
cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/vortex
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simout
|
||||
Redirecting stderr to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,12 +7,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 25 2010 03:11:27
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 03:34:57
|
||||
M5 executing on SC2B0619
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
|
||||
M5 compiled Aug 26 2010 13:03:41
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:06:02
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 203376692000 because target called exit()
|
||||
Exiting @ tick 203281649000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,43 +1,43 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 755710 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202292 # Number of bytes of host memory used
|
||||
host_seconds 180.15 # Real time elapsed on the host
|
||||
host_tick_rate 1128944281 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1039608 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 220432 # Number of bytes of host memory used
|
||||
host_seconds 130.95 # Real time elapsed on the host
|
||||
host_tick_rate 1552328099 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 136139203 # Number of instructions simulated
|
||||
sim_seconds 0.203377 # Number of seconds simulated
|
||||
sim_ticks 203376692000 # Number of ticks simulated
|
||||
sim_seconds 0.203282 # Number of seconds simulated
|
||||
sim_ticks 203281649000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 38539.616255 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35539.616255 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 1753514000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1617017000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_hits 15879 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 2072000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.002325 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 37 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 1961000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002325 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 37 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55967.131927 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52967.131927 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 20756479 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 6034656000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005168 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 107825 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5711181000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005168 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 107825 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
|
||||
|
|
@ -47,50 +47,50 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 50795.504944 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 47795.504944 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 57942281 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 7788170000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002639 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 153324 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7328198000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002639 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 153324 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.997952 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4087.609698 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.997956 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4087.629454 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 50795.504944 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 47795.504944 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 57940701 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 154904 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 57942281 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 7788170000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002639 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 153324 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7328198000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002639 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 153324 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4087.609698 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4087.629454 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 778280000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 107279 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 776960000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 108328 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 16931.987339 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13931.987339 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 3166688000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2605616000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
|
|
@ -102,31 +102,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 16931.987339 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 13931.987339 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 3166688000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 2605616000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.001390 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.978865 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 2004.715107 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.978873 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 2004.731937 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 16931.987339 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 13931.987339 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 134366560 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 3166688000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 187024 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 2605616000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.001390 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -134,44 +134,45 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 184976 # number of replacements
|
||||
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 2004.715107 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 2004.731937 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 144812317000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.warmup_cycle 144738462000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 84 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5464940000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.999201 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 105095 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4203800000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999201 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 105095 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 192883 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2061280000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.170478 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 39640 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1585600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170478 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 39640 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 2683 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51689.899366 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 138684000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 2683 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 107320000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 107279 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 2683 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 108328 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 108328 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 1.433874 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 1.441131 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -180,44 +181,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 192967 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 7526220000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.428588 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 144735 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 5789400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.428588 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 144735 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.120206 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.469380 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3938.922202 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15380.640176 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.127128 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.467489 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 4165.731733 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15318.691405 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 192777 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 144925 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 192967 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 7526220000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.428588 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 144735 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 5789400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.428588 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 144735 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 120487 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 139197 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 120481 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 139283 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 19319.562378 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 199591 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 19484.423138 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 200725 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 87414 # number of writebacks
|
||||
system.cpu.l2cache.writebacks 87388 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 406753384 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 406563298 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 136139203 # Number of instructions executed
|
||||
system.cpu.num_refs 58160249 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -353,7 +353,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,2 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simerr
|
||||
Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jun 6 2010 03:04:38
|
||||
M5 revision ba1a0193c050 7448 default tip
|
||||
M5 started Jun 6 2010 03:30:51
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 12:05:40
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -30,3 +30,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 732922365000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,54 +1,54 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 192033 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 206980 # Number of bytes of host memory used
|
||||
host_seconds 9040.35 # Real time elapsed on the host
|
||||
host_tick_rate 81902195 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 115207 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 207548 # Number of bytes of host memory used
|
||||
host_seconds 15068.91 # Real time elapsed on the host
|
||||
host_tick_rate 48638035 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_seconds 0.740425 # Number of seconds simulated
|
||||
sim_ticks 740424887500 # Number of ticks simulated
|
||||
sim_seconds 0.732922 # Number of seconds simulated
|
||||
sim_ticks 732922365000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 300304269 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 307023866 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 161 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 19915568 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 268271856 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 347819261 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 23893430 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.BTBHits 297651815 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 304473054 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 146 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 19905340 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 266187209 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 345286425 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 23890708 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 214632552 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 63188477 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 63402454 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1374695730 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.323769 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.099460 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1362326064 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.335789 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.108307 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 733755921 53.38% 53.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 260590847 18.96% 72.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 127148586 9.25% 81.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 73808717 5.37% 86.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 48837558 3.55% 90.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 32392808 2.36% 92.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 24165844 1.76% 94.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 10806972 0.79% 95.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 63188477 4.60% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 722221726 53.01% 53.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 260663635 19.13% 72.15% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 126275090 9.27% 81.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 73614843 5.40% 86.82% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 49214339 3.61% 90.43% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 31342415 2.30% 92.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 24208215 1.78% 94.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 11383347 0.84% 95.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 63402454 4.65% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1374695730 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1362326064 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 1819780126 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 445666361 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 19915049 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 19904825 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 631770816 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 616386841 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.853003 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.853003 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 0.844359 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.844359 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
|
||||
|
|
@ -59,292 +59,292 @@ system.cpu.dcache.LoadLockedReq_misses 1 # nu
|
|||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 523747084 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16905.655994 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11269.981612 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 513424902 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 174503258000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.019708 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 10322182 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 3045892 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 82003654500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013893 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7276290 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 521630579 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16446.832647 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11014.947389 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 511650921 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 164133765000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.019132 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 9979658 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 2703270 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 80149031000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013949 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7276388 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 33742.228480 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.275529 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 155297365 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 183258665559 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.033791 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 5431137 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 3182597 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 83540626157 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2248540 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6330.872599 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 30366.853399 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 73.096818 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 156412 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 65334 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 990224445 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 1983988000 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 32545.971387 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34322.334946 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 155766779 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 161484094789 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.030870 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 4961723 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 2963011 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 68600462724 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.012435 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1998712 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5974.555782 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 30410.724976 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 72.882698 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 121015 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 65147 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 723010868 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 1981167500 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 684475586 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 22710.257030 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 17380.287171 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 668722267 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 357761923559 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.023015 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 15753319 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 6228489 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 165544280657 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.013916 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9524830 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 682359081 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 21793.023000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 16037.508353 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 667417700 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 325617859789 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.021897 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 14941381 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 5666281 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 148749493724 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.013593 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9275100 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.997494 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_%::1 -0.003143 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4085.737319 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_blocks::1 -12.874688 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 684475586 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 22710.257030 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 17380.287171 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.997469 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_%::1 -0.002947 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4085.632664 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_blocks::1 -12.069593 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 682359081 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 21793.023000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 16037.508353 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 668722267 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 357761923559 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.023015 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 15753319 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 6228489 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 165544280657 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.013916 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9524830 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 667417700 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 325617859789 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.021897 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 14941381 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 5666281 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 148749493724 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.013593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9275100 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 9156903 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9160999 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 9156983 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9161079 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4079.299976 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 669639874 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7084220000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2245460 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 97965081 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 741 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 54990106 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2817972216 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 726420898 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 545630418 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 93906879 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 1735 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 4679333 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 771953785 # DTB accesses
|
||||
system.cpu.dcache.tagsinuse 4079.597867 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 667684156 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7084801000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2367711 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 93349702 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 598 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 54504022 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2803113220 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 722066213 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 542175542 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 91814713 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 1721 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 4734607 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 769403639 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 755880744 # DTB hits
|
||||
system.cpu.dtb.data_misses 16073041 # DTB misses
|
||||
system.cpu.dtb.data_hits 753449541 # DTB hits
|
||||
system.cpu.dtb.data_misses 15954098 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 569575118 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 567301584 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 560292416 # DTB read hits
|
||||
system.cpu.dtb.read_misses 9282702 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 202378667 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 558063709 # DTB read hits
|
||||
system.cpu.dtb.read_misses 9237875 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 202102055 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 195588328 # DTB write hits
|
||||
system.cpu.dtb.write_misses 6790339 # DTB write misses
|
||||
system.cpu.fetch.Branches 347819261 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 356032734 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 917156426 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 8668632 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2872343822 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 28362919 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.234878 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 356032734 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 324197699 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.939659 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1468602609 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.955835 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.862588 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dtb.write_hits 195385832 # DTB write hits
|
||||
system.cpu.dtb.write_misses 6716223 # DTB write misses
|
||||
system.cpu.fetch.Branches 345286425 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 353801341 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 911477048 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 8513687 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2856997588 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 28043242 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.235555 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 353801341 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 321542523 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.949045 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1454140777 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.964732 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.867668 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 907478951 61.79% 61.79% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 48285594 3.29% 65.08% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 31293098 2.13% 67.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 51463172 3.50% 70.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 124103039 8.45% 79.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 68291233 4.65% 83.82% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 47448055 3.23% 87.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 37389871 2.55% 89.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 152849596 10.41% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 896465106 61.65% 61.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 48268270 3.32% 64.97% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 30594278 2.10% 67.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 50900501 3.50% 70.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 123419810 8.49% 79.06% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 68033881 4.68% 83.74% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 46960603 3.23% 86.97% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 36759628 2.53% 89.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 152738700 10.50% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1468602609 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 356032734 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35280.127694 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35449.450549 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 356031481 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 44206000 # number of ReadReq miss cycles
|
||||
system.cpu.fetch.rateDist::total 1454140777 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 353801341 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35355.537721 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35450.495050 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 353800095 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 44053000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1253 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32259000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 1246 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32224500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 391243.385714 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 389219.026403 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 356032734 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35280.127694 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35449.450549 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 356031481 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 44206000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 353801341 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35355.537721 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35450.495050 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 353800095 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 44053000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1253 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 32259000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 1246 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 32224500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.349473 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 715.720591 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 356032734 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35280.127694 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35449.450549 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.349132 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 715.022199 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 353801341 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35355.537721 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35450.495050 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 356031481 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 44206000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 353800095 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 44053000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1253 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 32259000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 1246 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 32224500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 715.720591 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 356031481 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 715.022199 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 353800095 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 12247167 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 283205490 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 130221162 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.544186 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 773252228 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 202589844 # Number of stores executed
|
||||
system.cpu.idleCycles 11703954 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 281582966 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 129524501 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.553744 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 770699454 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 202312987 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1537746587 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2247853705 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.811174 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1532271545 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2239351820 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.811403 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1247380184 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.517949 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2269524166 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 21734619 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 17681894 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 621844790 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 1243290213 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.527687 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2260914368 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 21706879 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 16198055 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 619677157 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 21649497 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 234635839 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2626124753 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 570662384 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 37709808 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2286707552 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 438059 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 21613314 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 233108974 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2613111960 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 568386467 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 37669869 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2277546807 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 471616 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 36964 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 93906879 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 800629 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 28495 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 91814713 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 777432 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 361620 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 36313428 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 213767 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 285764 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 36261369 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 212351 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 2870017 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 18 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 176178429 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 73730857 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 2870017 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 3392458 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 18342161 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.172329 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.172329 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 2343036 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 14 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 174010796 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 72203992 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 2343036 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 3386842 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 18320037 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.184330 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.184330 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1537413633 66.14% 66.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 96 0.00% 66.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 239 0.00% 66.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 20 0.00% 66.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 141 0.00% 66.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 17 0.00% 66.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 581325773 25.01% 91.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 205677417 8.85% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1530874605 66.12% 66.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 97 0.00% 66.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% 66.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 66.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 138 0.00% 66.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% 66.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 578961528 25.01% 91.13% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 205380015 8.87% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 2324417360 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 13099894 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.005636 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 2315216676 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 13456867 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.005812 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 2747666 20.97% 20.97% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 20.97% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 20.97% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 20.97% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 20.97% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 20.97% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 20.97% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 20.97% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 20.97% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 8624380 65.84% 86.81% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 1727848 13.19% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 2756939 20.49% 20.49% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 20.49% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 20.49% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 20.49% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 20.49% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 20.49% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 20.49% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 20.49% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 20.49% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 8882759 66.01% 86.50% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 1817169 13.50% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1468602609 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.582741 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.758662 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1454140777 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.592154 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.762923 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 577211692 39.30% 39.30% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 268561729 18.29% 57.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 245516096 16.72% 74.31% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 137351239 9.35% 83.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 112900190 7.69% 91.35% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 73000831 4.97% 96.32% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 43951863 2.99% 99.31% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 8418123 0.57% 99.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 1690846 0.12% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 566783737 38.98% 38.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 267408405 18.39% 57.37% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 245316156 16.87% 74.24% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 135509048 9.32% 83.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 112013237 7.70% 91.26% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 72675996 5.00% 96.26% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 44106984 3.03% 99.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 8043729 0.55% 99.84% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 2283485 0.16% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1468602609 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.569651 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2495903546 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2324417360 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1454140777 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.579442 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2483587414 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2315216676 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 740504039 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1264443 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 728311196 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1117432 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 323242086 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 316872766 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 356032768 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 353801377 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 356032734 # ITB hits
|
||||
system.cpu.itb.fetch_misses 34 # ITB misses
|
||||
system.cpu.itb.fetch_hits 353801341 # ITB hits
|
||||
system.cpu.itb.fetch_misses 36 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
|
|
@ -353,106 +353,107 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1884709 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.194422 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.521684 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 65230144918 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1884709 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 59293928362 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1884709 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7277200 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34313.246356 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31139.092194 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5388273 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 64815217500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.259568 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1888927 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 58819472000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259568 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1888927 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 363845 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34326.565768 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.856148 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 12489549322 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 1884690 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.794335 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31398.574681 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 174907 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 59072651008 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.907196 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1709783 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53684749213 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.907196 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1709783 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7277298 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34312.855500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31137.095153 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5437284 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 63136134500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.252843 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1840014 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 57292691000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252843 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1840014 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 114023 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34289.699008 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31224.543680 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3909814350 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 363845 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11374106205 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 114023 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3560316144 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 363845 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2245460 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2245460 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11887.575431 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 114023 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2367711 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2367711 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11849.162556 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.418021 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 39831 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.526283 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 27449 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 473494017 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 325247663 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 9161909 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34461.554431 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.627299 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5388273 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 130045362418 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.411883 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3773636 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 9161988 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34426.978644 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31263.038482 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5612191 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 122208785508 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.387448 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3549797 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 118113400362 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.411883 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3773636 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 110977440213 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.387448 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3549797 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.452605 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.337458 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 14830.970465 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 11057.808672 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 9161909 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34461.554431 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.627299 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.481343 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.322273 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 15772.655639 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 10560.226030 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 9161988 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34426.978644 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31263.038482 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 5388273 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 130045362418 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.411883 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3773636 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 5612191 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 122208785508 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.387448 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3549797 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 118113400362 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.411883 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3773636 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 110977440213 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.387448 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3549797 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 2759709 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2784305 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 2708907 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2733538 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 25888.779137 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6732509 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 154525864500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1195751 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 123998073 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 64478030 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 621844790 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 234635839 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 1480849776 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 67789415 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.tagsinuse 26332.881669 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6905691 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 152081139500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1176798 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 124506463 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 62743482 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 619677157 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 233108974 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 1465844731 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 63989148 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 5483545 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 745501679 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 20525033 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 1073372 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 3564600090 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2755431831 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2063008571 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 531263306 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 93906879 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 30140307 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 686805608 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 1023 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:IQFullEvents 5522165 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 740664434 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 19930963 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 1000685 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 3545348406 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2741098331 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2053584906 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 528288951 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 91814713 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 29382701 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 677381943 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 830 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 61497352 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 59537135 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 46 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 461191 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.timesIdled 436319 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -152,12 +152,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,2 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 24 2010 23:12:40
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 02:20:02
|
||||
M5 executing on SC2B0619
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 12:06:37
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -28,3 +30,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 2705279137000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1190978 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 191664 # Number of bytes of host memory used
|
||||
host_seconds 1527.97 # Real time elapsed on the host
|
||||
host_tick_rate 1785366772 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1235575 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 206704 # Number of bytes of host memory used
|
||||
host_seconds 1472.82 # Real time elapsed on the host
|
||||
host_tick_rate 1836801554 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_seconds 2.727991 # Number of seconds simulated
|
||||
sim_ticks 2727990505000 # Number of ticks simulated
|
||||
sim_seconds 2.705279 # Number of seconds simulated
|
||||
sim_ticks 2705279137000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 24619.494258 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21619.494258 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 177812180000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 156144938000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 52453.824926 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49453.824926 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 158727823 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 104943266000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.012448 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2000679 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 98941229000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.012448 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2000679 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 30657.334367 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 596101072 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 282755446000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.015237 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9223093 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 255086167000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.015237 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9223093 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.996068 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4079.892573 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.996035 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4079.758997 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 30657.334367 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 595853949 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9470216 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 596101072 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 282755446000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.015237 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9223093 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 255086167000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.015237 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9223093 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4079.758997 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2244708 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 40990273000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2365949 # number of writebacks
|
||||
system.cpu.dtb.data_accesses 611922547 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 605324165 # DTB hits
|
||||
|
|
@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 802 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.298700 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 611.737435 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.298761 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 611.862910 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
|
|
@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 611.862910 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -164,36 +164,37 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 168921 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 89460748000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.910592 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1720399 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68815960000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.910592 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1720399 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5396262 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 95001608000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.252928 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1826954 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 73078160000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252928 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1826954 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 111359 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51964.511176 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 5786716000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 111359 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4454360000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 111359 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2365949 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2365949 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.515193 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -202,44 +203,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 5565183 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 184462356000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.389283 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3547353 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 141894120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.389283 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3547353 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.438454 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.335641 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 14367.257286 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 10998.286802 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.466649 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.320836 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 15291.153152 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 10513.160578 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 5348043 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3764493 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 5565183 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 184462356000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.389283 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3547353 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 141894120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.389283 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3547353 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 2751986 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 2701645 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2726277 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1194738 # number of writebacks
|
||||
system.cpu.l2cache.tagsinuse 25804.313731 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6857112 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 596452524000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1175830 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5455981010 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5410558274 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1819780127 # Number of instructions executed
|
||||
system.cpu.num_refs 613169725 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
|
||||
cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:41:22
|
||||
M5 compiled Aug 26 2010 13:52:30
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 14:05:19
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
|
||||
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -29,4 +31,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 2495902189000 because target called exit()
|
||||
Exiting @ tick 2473217439000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1693548 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210380 # Number of bytes of host memory used
|
||||
host_seconds 1005.94 # Real time elapsed on the host
|
||||
host_tick_rate 2481166849 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1470110 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211484 # Number of bytes of host memory used
|
||||
host_seconds 1158.83 # Real time elapsed on the host
|
||||
host_tick_rate 2134239180 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1703605163 # Number of instructions simulated
|
||||
sim_seconds 2.495902 # Number of seconds simulated
|
||||
sim_ticks 2495902189000 # Number of ticks simulated
|
||||
sim_seconds 2.473217 # Number of seconds simulated
|
||||
sim_ticks 2473217439000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 482384248 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 24911.078403 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21911.078403 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 24630.043664 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21630.043664 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 475158152 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 180009844000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 177979060000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.014980 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 7226096 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 158331556000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 156300772000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014980 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7226096 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 172586108 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.839740 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.839740 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 170339765 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 125794848000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.013016 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2246343 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 119055819000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.013016 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2246343 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 52467.599202 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49467.599202 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 170586898 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 104893749000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.011584 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1999210 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 98896119000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011584 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1999210 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 70.854389 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 654970356 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 32283.627480 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 29283.627480 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 645497917 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 305804692000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.014462 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9472439 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 30662.702029 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 27662.702029 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 645745050 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 282872809000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.014085 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9225306 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 277387375000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.014462 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9472439 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 255196891000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.014085 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9225306 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.997080 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4084.040360 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.997054 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4083.932190 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 654970356 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 32283.627480 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 29283.627480 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 30662.702029 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 27662.702029 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 645497917 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 305804692000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.014462 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9472439 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 645745050 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 282872809000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.014085 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9225306 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 277387375000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.014462 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9472439 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 255196891000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.014085 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9225306 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 9111149 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9115245 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4084.040360 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4083.932190 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 645855111 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 25923946000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2243257 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 25923011000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2365751 # number of writebacks
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 638 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.251129 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 514.312841 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.251186 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 514.428387 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1544565415 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency
|
||||
|
|
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 7 # number of replacements
|
||||
system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 514.312841 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 514.428387 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1544564777 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -150,36 +150,37 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.l2cache.ReadExReq_accesses 1889149 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 98235748000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1889149 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 75565960000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1889149 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 168141 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 89492416000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.910996 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1721008 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68840320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.910996 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1721008 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7226734 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5348868 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 97649032000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.259850 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1877866 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 75114640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259850 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1877866 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 357194 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.591505 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5397220 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 95134728000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.253159 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1829514 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 73180560000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.253159 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1829514 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 110061 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51957.950591 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 18555368000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 5718544000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 357194 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14287760000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 110061 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4402440000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 357194 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2243257 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2243257 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 110061 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2365751 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2365751 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.405017 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.511929 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 9115883 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5348868 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 195884780000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.413236 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3767015 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 5565361 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 184627144000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.389487 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3550522 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 150680600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.413236 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3767015 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 142020880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.389487 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3550522 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.425307 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.349424 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 13936.465557 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 11449.922093 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.457042 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.333046 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 14976.359071 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 10913.242343 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 9115883 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 5348868 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 195884780000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.413236 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3767015 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 5565361 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 184627144000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.389487 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3550522 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 150680600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.413236 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3767015 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 142020880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.389487 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3550522 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 2752487 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2779653 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 2702712 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2729930 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 25386.387650 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6685114 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 562275129000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1196151 # number of writebacks
|
||||
system.cpu.l2cache.tagsinuse 25889.601414 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6857391 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 555158623000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1177576 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 4991804378 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4946434878 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1703605163 # Number of instructions executed
|
||||
system.cpu.num_refs 660773876 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
|
||||
cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled May 2 2010 23:23:01
|
||||
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||
M5 started May 2 2010 23:23:02
|
||||
M5 executing on burrito
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
|
||||
M5 compiled Aug 26 2010 13:20:12
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:20:23
|
||||
M5 executing on zizzer
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -29,4 +31,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 5988071419000 because target called exit()
|
||||
Exiting @ tick 5965358694000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1729585 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 225072 # Number of bytes of host memory used
|
||||
host_seconds 2690.43 # Real time elapsed on the host
|
||||
host_tick_rate 2225692892 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 828534 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210088 # Number of bytes of host memory used
|
||||
host_seconds 5616.34 # Real time elapsed on the host
|
||||
host_tick_rate 1062144168 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 4653327945 # Number of instructions simulated
|
||||
sim_seconds 5.988071 # Number of seconds simulated
|
||||
sim_ticks 5988071419000 # Number of ticks simulated
|
||||
sim_seconds 5.965359 # Number of seconds simulated
|
||||
sim_ticks 5965358694000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 25017.777193 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.777193 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 24735.540403 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21735.540403 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 180699652000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 178661098000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 159031102000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 156992548000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.839821 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.839821 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 436280849 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 125858968000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005125 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2247488 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 119116504000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005125 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2247488 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 52475.088886 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49475.088886 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 436528587 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 104937059000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.004560 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1999750 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 98937809000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004560 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1999750 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
|
|
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 32370.399029 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 29370.399029 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1668242748 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 306558620000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9470338 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 30750.347733 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 27750.347733 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1668490486 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 283598157000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005497 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9222600 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 278147606000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9470338 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 255930357000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005497 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9222600 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.997262 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4084.783575 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.997251 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4084.741632 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 32370.399029 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 29370.399029 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 30750.347733 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 27750.347733 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1668242748 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 306558620000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9470338 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 1668490486 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 283598157000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005497 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9222600 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 278147606000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9470338 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 255930357000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005497 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9222600 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4084.783575 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4084.741632 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 58864073000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2244395 # number of writebacks
|
||||
system.cpu.dcache.warmup_cycle 58862918000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2365669 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
|
|
@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 675 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.271276 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 555.572992 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.271287 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 555.595041 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
|
|
@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 10 # number of replacements
|
||||
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 555.572992 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 555.595041 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -132,36 +132,37 @@ system.cpu.idle_fraction 0 # Pe
|
|||
system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 98271004000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1889827 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 75593080000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1889827 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_hits 167830 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 89543844000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.911193 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1721997 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68879880000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.911193 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1721997 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5328094 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 98562412000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.262397 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1895431 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 75817240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262397 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1895431 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 357661 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.659935 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5376631 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 96038488000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.255678 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1846894 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 73875760000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.255678 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1846894 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 109923 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51961.682268 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 18579652000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 5711784000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 357661 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14306440000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 109923 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4396920000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 357661 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2244395 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2244395 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 109923 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2365669 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2365669 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.381264 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.486980 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -170,44 +171,44 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5328094 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 196833416000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.415353 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3785258 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 5544461 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 185582332000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.391611 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3568891 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 151410320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.415353 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3785258 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 142755640000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.391611 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3568891 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.437808 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.347808 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 14346.083027 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 11396.963852 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.472057 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.330298 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 15468.376741 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 10823.217602 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 5328094 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 196833416000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.415353 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3785258 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 5544461 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 185582332000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.391611 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3568891 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 151410320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.415353 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3785258 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 142755640000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.391611 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3568891 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 2772035 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2798208 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 2721965 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2748168 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 25743.046878 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6663271 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 4737794502000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1199204 # number of writebacks
|
||||
system.cpu.l2cache.tagsinuse 26291.594343 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6834640 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 1346606710000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1180493 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 11976142838 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 11930717388 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 4653327945 # Number of instructions executed
|
||||
system.cpu.num_refs 1677713086 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -186,7 +186,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=twolf smred
|
||||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -4,3 +4,6 @@ warn: Prefetching currently unimplemented
|
|||
For more information see: http://www.m5sim.org/warn/8028fa22
|
||||
warn: Write Hints currently unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/cfb3293b
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,11 +7,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jun 25 2010 15:39:41
|
||||
M5 revision 93b1ca421839+ 7482+ default qtip tip update_regr
|
||||
M5 started Jun 25 2010 15:39:42
|
||||
M5 executing on zooks
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 12:18:42
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
|
||||
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
|
||||
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -26,4 +30,4 @@ Authors: Carl Sechen, Bill Swartz
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124
|
||||
122 123 124 Exiting @ tick 98337080000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 48476 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 156444 # Number of bytes of host memory used
|
||||
host_seconds 1895.84 # Real time elapsed on the host
|
||||
host_tick_rate 51872539 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 33745 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211108 # Number of bytes of host memory used
|
||||
host_seconds 2723.45 # Real time elapsed on the host
|
||||
host_tick_rate 36107563 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_seconds 0.098342 # Number of seconds simulated
|
||||
sim_ticks 98342168000 # Number of ticks simulated
|
||||
sim_seconds 0.098337 # Number of seconds simulated
|
||||
sim_ticks 98337080000 # Number of ticks simulated
|
||||
system.cpu.AGEN-Unit.agens 26537108 # Number of Address Generations
|
||||
system.cpu.Branch-Predictor.BTBHitPct 64.034182 # BTB Hit Percentage
|
||||
system.cpu.Branch-Predictor.BTBHits 5496951 # Number of BTB hits
|
||||
|
|
@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 409064
|
|||
system.cpu.Execution-Unit.predictedTakenIncorrect 1911977 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed
|
||||
system.cpu.RegFile-Manager.regFileAccesses 185972249 # Number of Total Accesses (Read+Write) to the Register File
|
||||
system.cpu.RegFile-Manager.regFileReads 117544888 # Number of Reads from Register File
|
||||
system.cpu.RegFile-Manager.regFileAccesses 185972267 # Number of Total Accesses (Read+Write) to the Register File
|
||||
system.cpu.RegFile-Manager.regFileReads 117544906 # Number of Reads from Register File
|
||||
system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File
|
||||
system.cpu.RegFile-Manager.regForwards 2843109 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.activity 95.455386 # Percentage of cycles cpu is active
|
||||
system.cpu.RegFile-Manager.regForwards 2843091 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.activity 95.460360 # Percentage of cycles cpu is active
|
||||
system.cpu.comBranches 10240685 # Number of Branches instructions committed
|
||||
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
|
||||
system.cpu.comInts 43625545 # Number of Integer instructions committed
|
||||
|
|
@ -42,28 +42,28 @@ system.cpu.comStores 6502695 # Nu
|
|||
system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
|
||||
system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.cpi 2.140128 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi_total 2.140128 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 2.140018 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi_total 2.140018 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 51549.473684 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48523.157895 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 51551.578947 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48525.263158 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 24486000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 24487000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 23048500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 23049500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56219.741797 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53219.741797 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 104512500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 98935500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56221.371882 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53221.371882 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6499339 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 99174500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000271 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1764 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 93882500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000271 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1764 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
|
||||
|
|
@ -73,39 +73,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 55269.280206 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52263.924593 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 128998500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 55230.683341 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 26495062 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 123661500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2239 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 121984000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 116932000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2239 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.352015 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 1441.851487 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_%::0 0.352018 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 1441.865798 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 55269.280206 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52263.924593 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 55230.683341 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 26494967 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 128998500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2334 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 26495062 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 123661500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2239 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 121984000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 116932000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2239 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1441.851487 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1441.865798 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 104 # number of writebacks
|
||||
|
|
@ -126,10 +126,10 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 6501103 # DTB write hits
|
||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 101762751 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 27218.382183 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 27218.266790 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.018072 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 101754085 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 235874500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 235873500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000085 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 8666 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 89 # number of ReadReq MSHR hits
|
||||
|
|
@ -145,10 +145,10 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 2000 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 101762751 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 27218.382183 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 27218.266790 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 101754085 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 235874500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 235873500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000085 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 8666 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 89 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -158,14 +158,14 @@ system.cpu.icache.demand_mshr_misses 8577 # nu
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.697630 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1428.745723 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_%::0 0.697638 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1428.763035 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 101762751 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 27218.382183 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 27218.266790 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 101754085 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 235874500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 235873500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000085 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 8666 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 89 # number of overall MSHR hits
|
||||
|
|
@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 6743 # number of replacements
|
||||
system.cpu.icache.sampled_refs 8577 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1428.745723 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1428.763035 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 101754085 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 8938543 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.ipc 0.467262 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.ipc_total 0.467262 # IPC: Total IPC of All Threads
|
||||
system.cpu.idleCycles 8928298 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.ipc 0.467286 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.ipc_total 0.467286 # IPC: Total IPC of All Threads
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
|
|
@ -201,48 +201,48 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52212.528604 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.819222 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 91267500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 91275000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69930000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 9052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52167.646099 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52167.809337 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5989 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 159789500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 159790000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.338378 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 122581500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338378 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52265.765766 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40009.009009 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 5801500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52250 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40062.500000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 836000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4441000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 641000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 1.971947 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 1.912000 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 10800 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52183.953440 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52185.616296 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5989 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 251057000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 251065000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.445463 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -252,16 +252,16 @@ system.cpu.l2cache.demand_mshr_misses 4811 # nu
|
|||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.061824 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::0 0.063287 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2025.851218 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13.722274 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::0 2073.775621 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13.721424 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 10800 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52183.953440 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52185.616296 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 5989 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 251057000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 251065000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.445463 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 4811 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -271,34 +271,34 @@ system.cpu.l2cache.overall_mshr_misses 4811 # nu
|
|||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 3030 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3125 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 2039.573492 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2087.497045 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 5975 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 196684337 # number of cpu cycles simulated
|
||||
system.cpu.runCycles 187745794 # Number of cycles cpu stages are processed.
|
||||
system.cpu.numCycles 196674161 # number of cpu cycles simulated
|
||||
system.cpu.runCycles 187745863 # Number of cycles cpu stages are processed.
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
|
||||
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
|
||||
system.cpu.stage-0.idleCycles 94921538 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-0.idleCycles 94911362 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-0.runCycles 101762799 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage-0.utilization 51.739147 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-1.idleCycles 104523823 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-0.utilization 51.741824 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-1.idleCycles 104513647 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-1.runCycles 92160514 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage-1.utilization 46.857068 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-2.idleCycles 103191853 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-1.utilization 46.859493 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-2.idleCycles 103181677 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage-2.utilization 47.534280 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-3.idleCycles 170147206 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-2.utilization 47.536740 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-3.idleCycles 170137030 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage-3.utilization 13.492244 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-4.idleCycles 104781281 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-3.utilization 13.492942 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage-4.idleCycles 104771105 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage-4.utilization 46.726169 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.threadCycles 196684337 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.stage-4.utilization 46.728587 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.threadCycles 196674161 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -353,7 +353,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=twolf smred
|
||||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue