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gem5/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
Steve Reinhardt 9e45ada171 stats: update stats for preceding coherence changes 
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00

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---------- Begin Simulation Statistics ----------
host_inst_rate 1308474 # Simulator instruction rate (inst/s)
host_mem_usage 210192 # Number of bytes of host memory used
host_seconds 1237.60 # Real time elapsed on the host
host_tick_rate 1465826235 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619366787 # Number of instructions simulated
sim_seconds 1.814106 # Number of seconds simulated
sim_ticks 1814105620000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 20817.236451 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17817.236451 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4107782000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3515804000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 54292.890290 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51292.890290 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 187878126 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 16718464000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001636 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 307931 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 15794671000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001636 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 307931 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 41219.114233 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency
system.cpu.dcache.demand_hits 606722925 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 20826246000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000832 # miss rate for demand accesses
system.cpu.dcache.demand_misses 505257 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 19310475000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000832 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 505257 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.903534 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 41219.114233 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 606722925 # number of overall hits
system.cpu.dcache.overall_miss_latency 20826246000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000832 # miss rate for overall accesses
system.cpu.dcache.overall_misses 505257 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 19310475000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000832 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 505257 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 437952 # number of replacements
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.903534 # Cycle average of tags in use
system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 306200 # number of writebacks
system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 722 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.322353 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 660.178535 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1186516018 # number of overall hits
system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 722 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 660.178535 # Cycle average of tags in use
system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12516 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 12074712000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.948856 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 232206 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9288240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.948856 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 232206 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 165297 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1703052000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.165369 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32751 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1310040000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165369 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32751 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 63209 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 3286868000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 63209 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528360000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 63209 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 306200 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 306200 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 3.450731 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 177813 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 13777764000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.598408 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 264957 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 10598280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.598408 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 264957 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.053631 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.452717 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1757.366037 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14834.623829 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 177813 # number of overall hits
system.cpu.l2cache.overall_miss_latency 13777764000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.598408 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 264957 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 10598280000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.598408 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 264957 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 81078 # number of replacements
system.cpu.l2cache.sampled_refs 96612 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 16591.989866 # Cycle average of tags in use
system.cpu.l2cache.total_refs 333382 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 61253 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 3628211240 # number of cpu cycles simulated
system.cpu.num_insts 1619366787 # Number of instructions executed
system.cpu.num_refs 607228182 # Number of memory references
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------
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