9e45ada171
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
34 lines
1.3 KiB
Text
Executable file
34 lines
1.3 KiB
Text
Executable file
Redirecting stdout to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simout
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Redirecting stderr to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simerr
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M5 Simulator System
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Aug 26 2010 13:52:30
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M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
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M5 started Aug 26 2010 14:05:19
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M5 executing on zizzer
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command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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spec_init
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Loading Input Data
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Input data 1048576 bytes in length
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Compressing Input Data, level 7
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info: Increasing stack size by one page.
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info: Increasing stack size by one page.
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info: Increasing stack size by one page.
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Compressed data 198546 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 9
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Compressed data 198677 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Exiting @ tick 2473217439000 because target called exit()
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