Stats: Update stats for previous set of patches.
This commit is contained in:
Ali Saidi
parent
77853b9f52
commit
9b67f3723e
38 changed files with 2057 additions and 2034 deletions
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Nov 15 2010 08:52:32
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M5 revision f440cdaf1c2d+ 7743+ default tip
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M5 started Nov 15 2010 08:53:40
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M5 compiled Jan 17 2011 16:24:53
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M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
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M5 started Jan 17 2011 16:40:29
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M5 executing on zizzer
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
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Global frequency set at 1000000000000 ticks per second
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@ -1,9 +1,9 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 195051 # Simulator instruction rate (inst/s)
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host_mem_usage 206584 # Number of bytes of host memory used
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host_seconds 2899.51 # Real time elapsed on the host
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host_tick_rate 56140502 # Simulator tick rate (ticks/s)
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host_inst_rate 207877 # Simulator instruction rate (inst/s)
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host_mem_usage 206352 # Number of bytes of host memory used
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host_seconds 2720.61 # Real time elapsed on the host
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host_tick_rate 59832123 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 565552443 # Number of instructions simulated
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sim_seconds 0.162780 # Number of seconds simulated
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@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 40819876 # DT
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system.cpu.dtb.write_misses 27547 # DTB write misses
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system.cpu.fetch.Branches 76295210 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 65560315 # Number of cache lines fetched
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system.cpu.fetch.Cycles 195638983 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.Cycles 130078631 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 1304986 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 697895611 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 4169829 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.234351 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 65560315 # Number of cycles fetch is stalled on an Icache miss
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@ -5,10 +5,10 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Jan 15 2011 04:38:18
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M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip
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M5 started Jan 15 2011 04:38:23
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M5 executing on tater
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M5 compiled Jan 17 2011 21:17:52
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M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
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M5 started Jan 17 2011 21:17:55
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M5 executing on zizzer
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command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@ -43,4 +43,4 @@ Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Exiting @ tick 601459117000 because target called exit()
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Exiting @ tick 601458924000 because target called exit()
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@ -1,63 +1,63 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 115319 # Simulator instruction rate (inst/s)
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host_mem_usage 220936 # Number of bytes of host memory used
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host_seconds 12188.85 # Real time elapsed on the host
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host_tick_rate 49345009 # Simulator tick rate (ticks/s)
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host_inst_rate 144426 # Simulator instruction rate (inst/s)
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host_mem_usage 207996 # Number of bytes of host memory used
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host_seconds 9732.45 # Real time elapsed on the host
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host_tick_rate 61799305 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1405604152 # Number of instructions simulated
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sim_seconds 0.601459 # Number of seconds simulated
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sim_ticks 601459117000 # Number of ticks simulated
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sim_ticks 601458924000 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 98804472 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 100538302 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 98804590 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 100538418 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 5348297 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 105813027 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 105813027 # Number of BP lookups
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system.cpu.BPredUnit.condIncorrect 5348296 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 105813144 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 105813144 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 86248929 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 21327805 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_lim_events 21328117 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 1172142381 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::samples 1172142071 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.270770 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.680117 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 418030405 35.66% 35.66% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 498323124 42.51% 78.18% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 52996988 4.52% 82.70% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 103673812 8.84% 91.54% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 32915552 2.81% 94.35% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 8294276 0.71% 95.06% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 25634202 2.19% 97.25% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 10946217 0.93% 98.18% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 21327805 1.82% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 418029830 35.66% 35.66% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 498322942 42.51% 78.18% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 52997650 4.52% 82.70% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 103674512 8.84% 91.54% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 32914783 2.81% 94.35% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 8294110 0.71% 95.06% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 25633990 2.19% 97.25% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 10946137 0.93% 98.18% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 21328117 1.82% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 1172142381 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 1172142071 # Number of insts commited each cycle
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system.cpu.commit.COM:count 1489523295 # Number of instructions committed
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system.cpu.commit.COM:loads 402512844 # Number of loads committed
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system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
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system.cpu.commit.COM:refs 569360986 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 5348297 # The number of times a branch was mispredicted
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system.cpu.commit.branchMispredicts 5348296 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 219358890 # The number of squashed insts skipped by commit
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system.cpu.commit.commitSquashedInsts 219357232 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
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system.cpu.cpi 0.855802 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.855802 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 295702052 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 14658.314544 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.427114 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 294883757 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 11994825500 # number of ReadReq miss cycles
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system.cpu.cpi 0.855801 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.855801 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 295701881 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 14657.940821 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.771391 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 294883584 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 11994549000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.002767 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 818295 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 604804 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1593801500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_misses 818297 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 604806 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1593875000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 213491 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
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@ -71,50 +71,50 @@ system.cpu.dcache.SwapReq_mshr_miss_latency 246000 #
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system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 15552.195709 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.845351 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 165080578 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 27468879045 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.010586 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1766238 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1498173 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 3438428299 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_avg_miss_latency 15553.543798 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12825.966833 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 165080859 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 27466889545 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.010584 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1765957 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1497892 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 3438192799 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 268065 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 955.151567 # Average number of references to valid blocks.
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system.cpu.dcache.avg_refs 955.151791 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 462548868 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 15269.181916 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 10449.936869 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 459964335 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 39463704545 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.005588 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2584533 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2102977 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 5032229799 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_accesses 462548697 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 15269.953551 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 10449.600460 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 459964443 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 39461438545 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.005587 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2584254 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2102698 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 5032067799 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.001041 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 481556 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999859 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4095.424477 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 462548868 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 15269.181916 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 10449.936869 # average overall mshr miss latency
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system.cpu.dcache.occ_blocks::0 4095.424247 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 462548697 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 15269.953551 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 10449.600460 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 459964335 # number of overall hits
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system.cpu.dcache.overall_miss_latency 39463704545 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.005588 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2584533 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2102977 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 5032229799 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_hits 459964443 # number of overall hits
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system.cpu.dcache.overall_miss_latency 39461438545 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.005587 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2584254 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2102698 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 5032067799 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.001041 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 481556 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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@ -122,129 +122,130 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
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system.cpu.dcache.replacements 477467 # number of replacements
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system.cpu.dcache.sampled_refs 481563 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.424477 # Cycle average of tags in use
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system.cpu.dcache.total_refs 459965654 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 132267000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tagsinuse 4095.424247 # Cycle average of tags in use
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system.cpu.dcache.total_refs 459965762 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 132304000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 428418 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 393632591 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 1750743071 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 405697785 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 351108006 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 30410701 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 21703388 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 105813027 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 173096803 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 548235394 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1429408 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 1755979705 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 6170644 # Number of cycles fetch has spent squashing
|
||||
system.cpu.decode.DECODE:BlockedCycles 393633604 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 1750740297 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 405697462 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 351107020 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 30410517 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 21703374 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 105813144 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 173097327 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 375137003 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1429156 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 1755978912 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 6170643 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 173096803 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 98804472 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.icacheStallCycles 173097327 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 98804590 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.459766 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1202552471 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.464003 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 1202551977 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.463999 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.699994 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 827413927 68.80% 68.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 82887157 6.89% 75.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 45822503 3.81% 79.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 22740108 1.89% 81.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 827414974 68.80% 68.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 82887161 6.89% 75.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 45821959 3.81% 79.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 22740624 1.89% 81.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 33832197 2.81% 84.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 32824411 2.73% 86.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 14992283 1.25% 88.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7935666 0.66% 88.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 134104219 11.15% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 32823900 2.73% 86.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 14990247 1.25% 88.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7935660 0.66% 88.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 134105255 11.15% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1202552471 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 173096803 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35063.545151 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35058.732612 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 173095009 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 62904000 # number of ReadReq miss cycles
|
||||
system.cpu.fetch.rateDist::total 1202551977 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 173097327 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35070.194986 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35059.073359 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 173095532 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 62951000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1794 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses 1795 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 45366000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 45401500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1294 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1295 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 133870.849961 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 133767.799073 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 173096803 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35063.545151 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35058.732612 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 173095009 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 62904000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 173097327 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35070.194986 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35059.073359 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 173095532 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 62951000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1794 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses 1795 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 45366000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 45401500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1294 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 1295 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.509485 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1043.425085 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 173096803 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35063.545151 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35058.732612 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.509893 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1044.260820 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 173097327 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35070.194986 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35059.073359 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 173095009 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 62904000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 173095532 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 62951000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1794 # number of overall misses
|
||||
system.cpu.icache.overall_misses 1795 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 45366000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 45401500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1294 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 1295 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 158 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1293 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 1294 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1043.425085 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 173095009 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1044.260820 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 173095532 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 365764 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 89387997 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 102270118 # number of nop insts executed
|
||||
system.cpu.idleCycles 365872 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 89387996 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 102270134 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.226826 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 590483044 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 169844841 # Number of stores executed
|
||||
system.cpu.iew.EXEC:refs 590482875 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 169844843 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1212158273 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1472499084 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.958320 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1212153101 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1472498717 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.958322 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1161635414 # num instructions producing a value
|
||||
system.cpu.iew.WB:producers 1161632680 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.224106 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1473870749 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 5524544 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2522826 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 468104285 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:sent 1473870381 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 5524543 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2523096 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 468104279 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 2975263 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 4542157 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 188277600 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 1708973999 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 420638203 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6158150 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1475771768 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 67057 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 4542154 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 188276128 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 1708972338 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 420638032 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6157621 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1475771230 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 66958 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 9806 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 30410701 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 130988 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 9816 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 30410517 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 130917 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 40442 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 124904328 # Number of loads that had data forwarded from stores
|
||||
|
|
@ -253,18 +254,18 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu
|
|||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 832421 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 264 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 65591441 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 21429458 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 65591435 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 21427986 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 648482 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 648481 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.168495 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.168495 # IPC: Total IPC of All Threads
|
||||
system.cpu.ipc 1.168496 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.168496 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 884685428 59.70% 59.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 884685423 59.70% 59.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618266 0.18% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618241 0.18% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.87% # Type of FU issued
|
||||
|
|
@ -290,165 +291,165 @@ system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.87%
|
|||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 423845992 28.60% 88.48% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 170780232 11.52% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 423844959 28.60% 88.48% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 170780228 11.52% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1481929918 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 3245029 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1481928851 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 3245613 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.002190 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 213200 6.57% 6.57% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.57% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.57% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 176159 5.43% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 2529947 77.96% 89.96% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 325723 10.04% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 176489 5.44% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 2530154 77.96% 89.96% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 325770 10.04% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1202552471 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1202551977 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.232320 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.127769 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.127764 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 320557937 26.66% 26.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 511599256 42.54% 69.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 219311183 18.24% 87.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 94899588 7.89% 95.33% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 39949785 3.32% 98.65% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 10701869 0.89% 99.54% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 5167481 0.43% 99.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 226815 0.02% 99.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 138557 0.01% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 320557298 26.66% 26.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 511598029 42.54% 69.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 219313490 18.24% 87.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 94900060 7.89% 95.33% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 39948235 3.32% 98.65% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 10701841 0.89% 99.54% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 5167806 0.43% 99.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 227063 0.02% 99.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 138155 0.01% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1202552471 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.231946 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 1603627961 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1481929918 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 3075920 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 200595189 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 67507 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 832249 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 279093354 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1202551977 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.231945 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 1603626285 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1481928851 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 3075919 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 200593512 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 68539 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 832248 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 279087097 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 268080 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.623615 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31319.356706 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.350752 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31318.935009 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 207610 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2080629000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2080612500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.225567 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 60470 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893881500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893856000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225567 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 60470 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 214777 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34036.417352 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.032810 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 214778 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34037.381235 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.958432 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 181098 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1146312500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.156809 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33679 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1044218500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156809 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33679 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1146379000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.156813 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33680 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1044247000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156813 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33680 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 428418 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 428418 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 5.114484 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.114449 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 482857 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34274.835633 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.916696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 482858 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34275.002655 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.617100 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 388708 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3226941500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.194983 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 94149 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_miss_latency 3226991500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.194985 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 94150 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2938100000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.194983 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 94149 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2938103000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.194985 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 94150 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.060598 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::0 0.060606 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.478382 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1985.676117 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15675.618625 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 482857 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34274.835633 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.916696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_blocks::0 1985.934249 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15675.618246 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 482858 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34275.002655 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.617100 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 388708 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3226941500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.194983 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 94149 # number of overall misses
|
||||
system.cpu.l2cache.overall_miss_latency 3226991500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.194985 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 94150 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2938100000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.194983 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 94149 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2938103000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.194985 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 94150 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 75916 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 91428 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 75917 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 91429 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 17661.294741 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 467607 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 17661.552495 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 467609 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 59275 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 406523724 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 165665166 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 468104285 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 188277600 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 1202918235 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 123850375 # Number of cycles rename is blocking
|
||||
system.cpu.memDep0.conflictingStores 165663867 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 468104279 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 188276128 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 1202917849 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 123850519 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers
|
||||
system.cpu.rename.RENAME:IQFullEvents 134234499 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 443701065 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 41034727 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:IQFullEvents 134234465 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 443700933 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 41034559 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 2924510246 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 1732032824 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1445195719 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 329589441 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 30410701 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 217220623 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 200425267 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 57780266 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:RenameLookups 2924501033 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 1732030714 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1445194568 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 329588798 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 30410517 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 217220436 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 200424116 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 57780774 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 385268446 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 385267398 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 11396 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.timesIdled 11390 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -5,13 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Dec 1 2010 12:54:21
|
||||
M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase
|
||||
M5 started Dec 3 2010 12:06:07
|
||||
M5 compiled Jan 17 2011 17:11:38
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 17:12:29
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 118370500
|
||||
Exiting @ tick 1900831708500 because m5_exit instruction encountered
|
||||
Exiting @ tick 1900831034500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Dec 1 2010 12:54:21
|
||||
M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase
|
||||
M5 started Dec 3 2010 12:04:42
|
||||
M5 compiled Jan 17 2011 17:11:38
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 17:11:41
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1865725201500 because m5_exit instruction encountered
|
||||
Exiting @ tick 1866702838500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:44:21
|
||||
M5 compiled Jan 17 2011 16:24:53
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 16:25:09
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 158570 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213052 # Number of bytes of host memory used
|
||||
host_seconds 2368.51 # Real time elapsed on the host
|
||||
host_tick_rate 57558166 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 178067 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212832 # Number of bytes of host memory used
|
||||
host_seconds 2109.17 # Real time elapsed on the host
|
||||
host_tick_rate 64635199 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 375574819 # Number of instructions simulated
|
||||
sim_seconds 0.136327 # Number of seconds simulated
|
||||
|
|
@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 80299022 # DT
|
|||
system.cpu.dtb.write_misses 1470 # DTB write misses
|
||||
system.cpu.fetch.Branches 62456368 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 64427463 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 168595579 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 104167812 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1484985 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 548969588 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 304 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 6021463 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.229068 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 64427463 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 08:53:40
|
||||
M5 compiled Jan 17 2011 16:24:53
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 16:24:57
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 221847 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213388 # Number of bytes of host memory used
|
||||
host_seconds 8217.59 # Real time elapsed on the host
|
||||
host_tick_rate 85165348 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 156459 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213156 # Number of bytes of host memory used
|
||||
host_seconds 11651.86 # Real time elapsed on the host
|
||||
host_tick_rate 60063670 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1823043370 # Number of instructions simulated
|
||||
sim_seconds 0.699854 # Number of seconds simulated
|
||||
|
|
@ -12,7 +12,7 @@ system.cpu.BPredUnit.BTBCorrect 0 # Nu
|
|||
system.cpu.BPredUnit.BTBHits 236956975 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 289938750 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 831 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 28355381 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condIncorrect 28355380 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 231810934 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 346110000 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 49326422 # Number of times the RAS was used to get a target.
|
||||
|
|
@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 258285727 # DT
|
|||
system.cpu.dtb.write_misses 37879 # DTB write misses
|
||||
system.cpu.fetch.Branches 346110000 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 346350693 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 922065710 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 575714813 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 4322310 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3016744002 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 28792194 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.247273 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 346350693 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:43:59
|
||||
M5 compiled Jan 17 2011 16:24:53
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 16:25:07
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 163173 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215808 # Number of bytes of host memory used
|
||||
host_seconds 487.78 # Real time elapsed on the host
|
||||
host_tick_rate 55274619 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 227615 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215572 # Number of bytes of host memory used
|
||||
host_seconds 349.68 # Real time elapsed on the host
|
||||
host_tick_rate 77104293 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_seconds 0.026962 # Number of seconds simulated
|
||||
|
|
@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 15053637 # DT
|
|||
system.cpu.dtb.write_misses 17557 # DTB write misses
|
||||
system.cpu.fetch.Branches 16280778 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 13394904 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 33285903 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 19864093 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 154345 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 103458756 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 26906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 576280 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.301925 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 13394904 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 08:53:40
|
||||
M5 compiled Jan 17 2011 16:24:53
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 16:24:57
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 144806 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 206568 # Number of bytes of host memory used
|
||||
host_seconds 11988.72 # Real time elapsed on the host
|
||||
host_tick_rate 60389347 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 148199 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 206348 # Number of bytes of host memory used
|
||||
host_seconds 11714.26 # Real time elapsed on the host
|
||||
host_tick_rate 61804258 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_seconds 0.723991 # Number of seconds simulated
|
||||
|
|
@ -153,9 +153,10 @@ system.cpu.dtb.write_hits 194797036 # DT
|
|||
system.cpu.dtb.write_misses 6192363 # DTB write misses
|
||||
system.cpu.fetch.Branches 344584799 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 354412327 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 911372250 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 556959890 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 8690810 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2851036906 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 28190849 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.237976 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 354412327 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:43:59
|
||||
M5 compiled Jan 17 2011 16:24:53
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 16:30:09
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 130193 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210712 # Number of bytes of host memory used
|
||||
host_seconds 646.58 # Real time elapsed on the host
|
||||
host_tick_rate 62840883 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 134338 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210480 # Number of bytes of host memory used
|
||||
host_seconds 626.63 # Real time elapsed on the host
|
||||
host_tick_rate 64841631 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_seconds 0.040632 # Number of seconds simulated
|
||||
|
|
@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 7182981 # DT
|
|||
system.cpu.dtb.write_misses 1041 # DTB write misses
|
||||
system.cpu.fetch.Branches 19564106 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 19059447 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 49623738 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 30564219 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 482133 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 167632917 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 2031289 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.240750 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 19059447 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:43:59
|
||||
M5 compiled Jan 17 2011 16:24:53
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 16:24:57
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 34451 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203748 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
host_tick_rate 66857161 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 10121 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203516 # Number of bytes of host memory used
|
||||
host_seconds 0.63 # Real time elapsed on the host
|
||||
host_tick_rate 19665204 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 6386 # Number of instructions simulated
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
|
|
@ -143,9 +143,10 @@ system.cpu.dtb.write_hits 1051 # DT
|
|||
system.cpu.dtb.write_misses 25 # DTB write misses
|
||||
system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1774 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 4193 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 2385 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 13186 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 503 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.089503 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1774 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:43:59
|
||||
M5 compiled Jan 17 2011 16:24:53
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 16:48:46
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 60581 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202656 # Number of bytes of host memory used
|
||||
host_inst_rate 61982 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202420 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_tick_rate 184013511 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 188319059 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_seconds 0.000007 # Number of seconds simulated
|
||||
|
|
@ -143,9 +143,10 @@ system.cpu.dtb.write_hits 351 # DT
|
|||
system.cpu.dtb.write_misses 17 # DTB write misses
|
||||
system.cpu.fetch.Branches 926 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 782 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1799 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 988 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5752 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 249 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.063420 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 782 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 14 2010 23:58:18
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 14 2010 23:58:34
|
||||
M5 compiled Jan 17 2011 21:17:36
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 21:17:39
|
||||
M5 executing on zizzer
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 72923 # Simulator instruction rate (inst/s)
|
||||
host_inst_rate 35741 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204488 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 179666090 # Simulator tick rate (ticks/s)
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_tick_rate 88262097 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5169 # Number of instructions simulated
|
||||
sim_seconds 0.000013 # Number of seconds simulated
|
||||
|
|
@ -136,9 +136,10 @@ system.cpu.dtb.write_hits 0 # DT
|
|||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 1744 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1555 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 4407 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 2837 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 11052 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 393 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.068205 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1555 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: allowing mmap of file @ fd 17040520. This will break if not /dev/zero.
|
||||
warn: allowing mmap of file @ fd 16206088. This will break if not /dev/zero.
|
||||
For more information see: http://www.m5sim.org/warn/3a2134f6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 15 2010 00:01:15
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 00:01:17
|
||||
M5 compiled Jan 17 2011 17:18:01
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 17:18:03
|
||||
M5 executing on zizzer
|
||||
command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 15746 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202164 # Number of bytes of host memory used
|
||||
host_seconds 0.37 # Real time elapsed on the host
|
||||
host_tick_rate 31829526 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 12762 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202140 # Number of bytes of host memory used
|
||||
host_seconds 0.45 # Real time elapsed on the host
|
||||
host_tick_rate 25804848 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5800 # Number of instructions simulated
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
|
|
@ -136,9 +136,10 @@ system.cpu.dtb.write_hits 0 # DT
|
|||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 2100 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1490 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 3561 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 2070 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.089487 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:43:59
|
||||
M5 compiled Jan 17 2011 16:24:53
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 16:24:57
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 115372 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204236 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_tick_rate 127463354 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 10660 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204092 # Number of bytes of host memory used
|
||||
host_seconds 1.20 # Real time elapsed on the host
|
||||
host_tick_rate 11797749 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 12773 # Number of instructions simulated
|
||||
sim_seconds 0.000014 # Number of seconds simulated
|
||||
|
|
@ -213,9 +213,10 @@ system.cpu.dtb.write_hits 2080 # DT
|
|||
system.cpu.dtb.write_misses 54 # DTB write misses
|
||||
system.cpu.fetch.Branches 5341 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 3993 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 9162 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 611 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 29881 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 1641 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.188868 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 3993 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 15 2011 04:38:18
|
||||
M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip
|
||||
M5 started Jan 15 2011 04:38:23
|
||||
M5 executing on tater
|
||||
M5 compiled Jan 17 2011 21:17:52
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 21:18:06
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 46971 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 216748 # Number of bytes of host memory used
|
||||
host_seconds 0.31 # Real time elapsed on the host
|
||||
host_tick_rate 60590117 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 91156 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203828 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_tick_rate 117504787 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 14449 # Number of instructions simulated
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
|
|
@ -126,9 +126,10 @@ system.cpu.decode.DECODE:SquashCycles 1178 # Nu
|
|||
system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 5172 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 4077 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 11611 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 7506 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 23982 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 826 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.138611 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 4077 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
|
|||
boot_cpu_frequency=500
|
||||
boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
|
||||
init_param=0
|
||||
kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
|
@ -155,7 +155,7 @@ type=ExeTracer
|
|||
|
||||
[system.diskmem]
|
||||
type=PhysicalMemory
|
||||
file=/chips/pd/randd/dist/disks/ael-arm.ext2
|
||||
file=/dist/m5/system/disks/ael-arm.ext2
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -30,8 +30,14 @@ warn: Returning thumbEE disabled for now since we don't support CP14config regis
|
|||
For more information see: http://www.m5sim.org/warn/7998f2ea
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/21b09adb
|
||||
warn: Complete acc isn't called on normal stores in O3.
|
||||
For more information see: http://www.m5sim.org/warn/138d8573
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/21b09adb
|
||||
warn: Complete acc isn't called on normal stores in O3.
|
||||
For more information see: http://www.m5sim.org/warn/138d8573
|
||||
warn: Complete acc isn't called on normal stores in O3.
|
||||
For more information see: http://www.m5sim.org/warn/138d8573
|
||||
warn: Need to flush all TLBs in MP
|
||||
For more information see: http://www.m5sim.org/warn/6cccf999
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
|
|
|
|||
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 15 2010 11:17:32
|
||||
M5 revision e459beb39dd0 7713 default ext/amba_kmi_pl050.patch qtip tip
|
||||
M5 started Oct 15 2010 11:17:48
|
||||
M5 executing on aus-bc3-b4
|
||||
command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing
|
||||
M5 compiled Jan 17 2011 18:36:49
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 18:36:52
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 120261685000 because m5_exit instruction encountered
|
||||
Exiting @ tick 114721074000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -1,254 +1,254 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 571745 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 384580 # Number of bytes of host memory used
|
||||
host_seconds 88.62 # Real time elapsed on the host
|
||||
host_tick_rate 1356995451 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1461109 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 340352 # Number of bytes of host memory used
|
||||
host_seconds 34.61 # Real time elapsed on the host
|
||||
host_tick_rate 3314430509 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 50669854 # Number of instructions simulated
|
||||
sim_seconds 0.120262 # Number of seconds simulated
|
||||
sim_ticks 120261685000 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses::0 100213 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 100213 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15144.474290 # average LoadLockedReq miss latency
|
||||
sim_insts 50572425 # Number of instructions simulated
|
||||
sim_seconds 0.114721 # Number of seconds simulated
|
||||
sim_ticks 114721074000 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses::0 100214 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 100214 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15147.115385 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12144.474290 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12147.115385 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
|
||||
system.cpu.dcache.LoadLockedReq_hits::0 95001 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 95001 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 78933000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052009 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses::0 5212 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 5212 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63297000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052009 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_hits::0 95014 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 95014 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 78765000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051889 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses::0 5200 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 5200 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63165000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051889 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 5212 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 5200 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310267000 # number of LoadLockedReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_accesses::0 7824422 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 7824422 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::0 15793.989050 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_accesses::0 7824780 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 7824780 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::0 15798.342892 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12793.661656 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12798.015358 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_hits::0 7587704 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7587704 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3738721500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate::0 0.030254 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses::0 236718 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 236718 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3028490000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030254 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_hits::0 7588163 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7588163 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3738156500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate::0 0.030239 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses::0 236617 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 236617 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3028228000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030239 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 236718 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 43432839000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.StoreCondReq_accesses::0 100212 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 100212 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits::0 100212 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 100212 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses::0 6671650 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6671650 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::0 40817.981450 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_mshr_misses 236617 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38190415500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.StoreCondReq_accesses::0 100213 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 100213 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits::0 100213 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 100213 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses::0 6671860 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6671860 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::0 40836.063764 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37817.693965 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37835.781907 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_hits::0 6499467 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6499467 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 7028162500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate::0 0.025808 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses::0 172183 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 172183 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 6511564000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025808 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_hits::0 6499787 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6499787 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 7026784000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate::0 0.025791 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses::0 172073 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 172073 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 6510516500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025791 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 172183 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 172073 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926046500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 34.639363 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 34.660375 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses::0 14496072 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::0 14496640 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 14496072 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency::0 26331.273340 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses::total 14496640 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency::0 26340.112310 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23330.962751 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits::0 14087171 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits::0 14087950 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 14087171 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 10766884000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate::0 0.028208 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_hits::total 14087950 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 10764940500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate::0 0.028192 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses::0 408901 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::0 408690 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 408901 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 408690 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 9540054000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate::0 0.028208 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 9538744500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate::0 0.028192 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 408901 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 408690 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.994782 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 509.328153 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses::0 14496072 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.occ_%::0 0.994530 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 509.199113 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses::0 14496640 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 14496072 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency::0 26331.273340 # average overall miss latency
|
||||
system.cpu.dcache.overall_accesses::total 14496640 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency::0 26340.112310 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23330.962751 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits::0 14087171 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::0 14087950 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 14087171 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 10766884000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate::0 0.028208 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits::total 14087950 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 10764940500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate::0 0.028192 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses::0 408901 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::0 408690 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 408901 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 408690 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 9540054000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate::0 0.028208 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 9538744500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate::0 0.028192 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 408901 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 44358885500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_misses 408690 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 39116462000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 411855 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 412367 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 411628 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 412140 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 509.328153 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14284130 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 509.199113 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14284927 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 383037 # number of writebacks
|
||||
system.cpu.dtb.accesses 15524365 # DTB accesses
|
||||
system.cpu.dcache.writebacks 382676 # number of writebacks
|
||||
system.cpu.dtb.accesses 15524935 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.flush_entries 2228 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 2199 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.hits 15518843 # DTB hits
|
||||
system.cpu.dtb.hits 15519414 # DTB hits
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.misses 5522 # DTB misses
|
||||
system.cpu.dtb.misses 5521 # DTB misses
|
||||
system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.prefetch_faults 756 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.read_accesses 8739944 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 8735402 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4542 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 6784421 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 6783441 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 8740303 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 8735762 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4541 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 6784632 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 6783652 # DTB write hits
|
||||
system.cpu.dtb.write_misses 980 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses::0 41542689 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 41542689 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::0 14799.146758 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_accesses::0 41543801 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 41543801 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::0 14800.791885 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11797.848096 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11799.492843 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.ReadReq_hits::0 41109166 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 41109166 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 6415770500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate::0 0.010436 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses::0 433523 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 433523 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 5114638500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010436 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_hits::0 41110405 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 41110405 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 6414604000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate::0 0.010432 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses::0 433396 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 433396 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 5113853000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010432 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 433523 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 433396 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 94.826020 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 94.856667 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses::0 41542689 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::0 41543801 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 41542689 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency::0 14799.146758 # average overall miss latency
|
||||
system.cpu.icache.demand_accesses::total 41543801 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency::0 14800.791885 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11797.848096 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits::0 41109166 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits::0 41110405 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 41109166 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 6415770500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate::0 0.010436 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_hits::total 41110405 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 6414604000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate::0 0.010432 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses::0 433523 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::0 433396 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 433523 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 433396 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 5114638500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate::0 0.010436 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_latency 5113853000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate::0 0.010432 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 433523 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 433396 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.948287 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 485.522726 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses::0 41542689 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_%::0 0.945788 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 484.243503 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses::0 41543801 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 41542689 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency::0 14799.146758 # average overall miss latency
|
||||
system.cpu.icache.overall_accesses::total 41543801 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency::0 14800.791885 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11797.848096 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits::0 41109166 # number of overall hits
|
||||
system.cpu.icache.overall_hits::0 41110405 # number of overall hits
|
||||
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 41109166 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 6415770500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate::0 0.010436 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_hits::total 41110405 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 6414604000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate::0 0.010432 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses::0 433523 # number of overall misses
|
||||
system.cpu.icache.overall_misses::0 433396 # number of overall misses
|
||||
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 433523 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 433396 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 5114638500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate::0 0.010436 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_latency 5113853000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate::0 0.010432 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 433523 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 433396 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 433010 # number of replacements
|
||||
system.cpu.icache.sampled_refs 433522 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 432883 # number of replacements
|
||||
system.cpu.icache.sampled_refs 433395 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 485.522726 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 41109166 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 484.243503 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 41110405 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 33595 # number of writebacks
|
||||
system.cpu.icache.writebacks 33555 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 41545508 # DTB accesses
|
||||
system.cpu.itb.accesses 41546620 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB
|
||||
|
|
@ -256,9 +256,9 @@ system.cpu.itb.flush_tlb 2 # Nu
|
|||
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.hits 41542689 # DTB hits
|
||||
system.cpu.itb.inst_accesses 41545508 # ITB inst accesses
|
||||
system.cpu.itb.inst_hits 41542689 # ITB inst hits
|
||||
system.cpu.itb.hits 41543801 # DTB hits
|
||||
system.cpu.itb.inst_accesses 41546620 # ITB inst accesses
|
||||
system.cpu.itb.inst_hits 41543801 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 2819 # ITB inst misses
|
||||
system.cpu.itb.misses 2819 # DTB misses
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
|
|
@ -272,9 +272,9 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 240523370 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 50669854 # Number of instructions executed
|
||||
system.cpu.num_refs 16289326 # Number of memory references
|
||||
system.cpu.numCycles 229442148 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 50572425 # Number of instructions executed
|
||||
system.cpu.num_refs 16289993 # Number of memory references
|
||||
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
||||
|
|
@ -344,140 +344,140 @@ system.iocache.warmup_cycle 0 # Cy
|
|||
system.iocache.writebacks 0 # number of writebacks
|
||||
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
|
||||
system.l2c.LoadLockedReq_mshr_uncacheable_latency 234160000 # number of LoadLockedReq MSHR uncacheable cycles
|
||||
system.l2c.ReadExReq_accesses::0 170437 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 170437 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::0 170323 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 170323 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_hits::0 62185 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 62185 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::0 62071 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 62071 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_miss_latency 5629104000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_rate::0 0.635144 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::0 0.635569 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_misses::0 108252 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 108252 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_mshr_miss_latency 4330080000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_rate::0 0.635144 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::0 0.635569 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_misses 108252 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadReq_accesses::0 673342 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::1 5664 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 679006 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_avg_miss_latency::0 52102.216096 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::1 26560864.864865 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 26612967.080961 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_accesses::0 673101 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::1 5652 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 678753 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_avg_miss_latency::0 52096.523258 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::1 28127657.142857 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 28179753.666115 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_hits::0 654480 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::1 5627 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 660107 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_latency 982752000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_rate::0 0.028013 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::1 0.006532 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.034545 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses::0 18862 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::1 37 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 18899 # number of ReadReq misses
|
||||
system.l2c.ReadReq_mshr_miss_latency 755960000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::0 0.028067 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::1 3.336688 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 3.364755 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_misses 18899 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency 33155867000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.UpgradeReq_accesses::0 1746 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1746 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_avg_miss_latency::0 721.804511 # average UpgradeReq miss latency
|
||||
system.l2c.ReadReq_hits::0 654204 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::1 5617 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 659821 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_latency 984468000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_rate::0 0.028075 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::1 0.006192 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.034267 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses::0 18897 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::1 35 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 18932 # number of ReadReq misses
|
||||
system.l2c.ReadReq_mshr_miss_latency 757280000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::0 0.028127 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::1 3.349611 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 3.377737 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_misses 18932 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency 29199338000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.UpgradeReq_accesses::0 1750 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1750 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_avg_miss_latency::0 660.126947 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_miss_latency 1248000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_rate::0 0.990263 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_misses::0 1729 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1729 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_mshr_miss_latency 69160000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::0 0.990263 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_latency 1144000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_rate::0 0.990286 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_misses::0 1733 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1733 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_mshr_miss_latency 69320000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::0 0.990286 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_misses 1729 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses 1733 # number of UpgradeReq MSHR misses
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.Writeback_accesses::0 416632 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 416632 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits::0 416632 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 416632 # number of Writeback hits
|
||||
system.l2c.Writeback_accesses::0 416231 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 416231 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits::0 416231 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 416231 # number of Writeback hits
|
||||
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_refs 6.976763 # Average number of references to valid blocks.
|
||||
system.l2c.avg_refs 6.975292 # Average number of references to valid blocks.
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.demand_accesses::0 843779 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::1 5664 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 849443 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency::0 52015.167487 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::1 178698810.810811 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 178750825.978298 # average overall miss latency
|
||||
system.l2c.demand_accesses::0 843424 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::1 5652 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 849076 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency::0 52014.345374 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::1 188959200 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 189011214.345374 # average overall miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_hits::0 716665 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::1 5627 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 722292 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 6611856000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate::0 0.150648 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::1 0.006532 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.157181 # miss rate for demand accesses
|
||||
system.l2c.demand_misses::0 127114 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::1 37 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 127151 # number of demand (read+write) misses
|
||||
system.l2c.demand_hits::0 716275 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::1 5617 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 721892 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 6613572000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate::0 0.150753 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::1 0.006192 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.156946 # miss rate for demand accesses
|
||||
system.l2c.demand_misses::0 127149 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::1 35 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 127184 # number of demand (read+write) misses
|
||||
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_miss_latency 5086040000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_rate::0 0.150692 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::1 22.448976 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 22.599668 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_misses 127151 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_miss_latency 5087360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_rate::0 0.150795 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::1 22.502477 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 22.653272 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_misses 127184 # number of demand (read+write) MSHR misses
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.occ_%::0 0.087309 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::1 0.478511 # Average percentage of cache occupancy
|
||||
system.l2c.occ_blocks::0 5721.907765 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 31359.701032 # Average occupied blocks per context
|
||||
system.l2c.overall_accesses::0 843779 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::1 5664 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 849443 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency::0 52015.167487 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::1 178698810.810811 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 178750825.978298 # average overall miss latency
|
||||
system.l2c.occ_%::0 0.086431 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::1 0.477933 # Average percentage of cache occupancy
|
||||
system.l2c.occ_blocks::0 5664.361976 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 31321.847814 # Average occupied blocks per context
|
||||
system.l2c.overall_accesses::0 843424 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::1 5652 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 849076 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency::0 52014.345374 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::1 188959200 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 189011214.345374 # average overall miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_hits::0 716665 # number of overall hits
|
||||
system.l2c.overall_hits::1 5627 # number of overall hits
|
||||
system.l2c.overall_hits::total 722292 # number of overall hits
|
||||
system.l2c.overall_miss_latency 6611856000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate::0 0.150648 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::1 0.006532 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.157181 # miss rate for overall accesses
|
||||
system.l2c.overall_misses::0 127114 # number of overall misses
|
||||
system.l2c.overall_misses::1 37 # number of overall misses
|
||||
system.l2c.overall_misses::total 127151 # number of overall misses
|
||||
system.l2c.overall_hits::0 716275 # number of overall hits
|
||||
system.l2c.overall_hits::1 5617 # number of overall hits
|
||||
system.l2c.overall_hits::total 721892 # number of overall hits
|
||||
system.l2c.overall_miss_latency 6613572000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate::0 0.150753 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::1 0.006192 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.156946 # miss rate for overall accesses
|
||||
system.l2c.overall_misses::0 127149 # number of overall misses
|
||||
system.l2c.overall_misses::1 35 # number of overall misses
|
||||
system.l2c.overall_misses::total 127184 # number of overall misses
|
||||
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_miss_latency 5086040000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_rate::0 0.150692 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::1 22.448976 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 22.599668 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_misses 127151 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_uncacheable_latency 33895711000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_miss_latency 5087360000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_rate::0 0.150795 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::1 22.502477 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 22.653272 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_misses 127184 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_uncacheable_latency 29939182000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.l2c.replacements 94181 # number of replacements
|
||||
system.l2c.sampled_refs 125790 # Sample count of references to valid blocks.
|
||||
system.l2c.replacements 94170 # number of replacements
|
||||
system.l2c.sampled_refs 125831 # Sample count of references to valid blocks.
|
||||
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.l2c.tagsinuse 37081.608797 # Cycle average of tags in use
|
||||
system.l2c.total_refs 877607 # Total number of references to valid blocks.
|
||||
system.l2c.tagsinuse 36986.209790 # Cycle average of tags in use
|
||||
system.l2c.total_refs 877708 # Total number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.writebacks 87612 # number of writebacks
|
||||
system.l2c.writebacks 87626 # number of writebacks
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
|
||||
build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 15 2011 04:38:18
|
||||
M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip
|
||||
M5 started Jan 15 2011 04:38:23
|
||||
M5 executing on tater
|
||||
M5 compiled Jan 17 2011 21:17:52
|
||||
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
|
||||
M5 started Jan 17 2011 21:19:18
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 82069 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 227196 # Number of bytes of host memory used
|
||||
host_seconds 14.05 # Real time elapsed on the host
|
||||
host_tick_rate 8360775 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 133732 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214280 # Number of bytes of host memory used
|
||||
host_seconds 8.62 # Real time elapsed on the host
|
||||
host_tick_rate 13623692 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1153323 # Number of instructions simulated
|
||||
sim_seconds 0.000117 # Number of seconds simulated
|
||||
|
|
@ -136,9 +136,10 @@ system.cpu0.decode.DECODE:SquashCycles 2062 # Nu
|
|||
system.cpu0.decode.DECODE:UnblockCycles 202 # Number of cycles decode is unblocking
|
||||
system.cpu0.fetch.Branches 92364 # Number of branches that fetch encountered
|
||||
system.cpu0.fetch.CacheLines 5264 # Number of cache lines fetched
|
||||
system.cpu0.fetch.Cycles 186834 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu0.fetch.Cycles 181529 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu0.fetch.IcacheSquashes 482 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu0.fetch.Insts 550067 # Number of instructions fetch has processed
|
||||
system.cpu0.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu0.fetch.SquashCycles 1232 # Number of cycles fetch has spent squashing
|
||||
system.cpu0.fetch.branchRate 0.393048 # Number of branch fetches per cycle
|
||||
system.cpu0.fetch.icacheStallCycles 5264 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
@ -509,9 +510,10 @@ system.cpu1.decode.DECODE:SquashCycles 1784 # Nu
|
|||
system.cpu1.decode.DECODE:UnblockCycles 8335 # Number of cycles decode is unblocking
|
||||
system.cpu1.fetch.Branches 44023 # Number of branches that fetch encountered
|
||||
system.cpu1.fetch.CacheLines 27242 # Number of cache lines fetched
|
||||
system.cpu1.fetch.Cycles 120404 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu1.fetch.Cycles 93139 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu1.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu1.fetch.Insts 234880 # Number of instructions fetch has processed
|
||||
system.cpu1.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu1.fetch.SquashCycles 1183 # Number of cycles fetch has spent squashing
|
||||
system.cpu1.fetch.branchRate 0.220190 # Number of branch fetches per cycle
|
||||
system.cpu1.fetch.icacheStallCycles 27242 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
@ -881,9 +883,10 @@ system.cpu2.decode.DECODE:SquashCycles 1740 # Nu
|
|||
system.cpu2.decode.DECODE:UnblockCycles 3898 # Number of cycles decode is unblocking
|
||||
system.cpu2.fetch.Branches 60491 # Number of branches that fetch encountered
|
||||
system.cpu2.fetch.CacheLines 17027 # Number of cache lines fetched
|
||||
system.cpu2.fetch.Cycles 138086 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu2.fetch.Cycles 121028 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu2.fetch.IcacheSquashes 224 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu2.fetch.Insts 343825 # Number of instructions fetch has processed
|
||||
system.cpu2.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu2.fetch.SquashCycles 1162 # Number of cycles fetch has spent squashing
|
||||
system.cpu2.fetch.branchRate 0.303000 # Number of branch fetches per cycle
|
||||
system.cpu2.fetch.icacheStallCycles 17027 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
@ -1253,9 +1256,10 @@ system.cpu3.decode.DECODE:SquashCycles 1792 # Nu
|
|||
system.cpu3.decode.DECODE:UnblockCycles 5492 # Number of cycles decode is unblocking
|
||||
system.cpu3.fetch.Branches 55399 # Number of branches that fetch encountered
|
||||
system.cpu3.fetch.CacheLines 20572 # Number of cache lines fetched
|
||||
system.cpu3.fetch.Cycles 133138 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu3.fetch.Cycles 112541 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu3.fetch.IcacheSquashes 221 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu3.fetch.Insts 309543 # Number of instructions fetch has processed
|
||||
system.cpu3.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu3.fetch.SquashCycles 1170 # Number of cycles fetch has spent squashing
|
||||
system.cpu3.fetch.branchRate 0.277870 # Number of branch fetches per cycle
|
||||
system.cpu3.fetch.icacheStallCycles 20572 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
|
|||
Loading…
Reference in a new issue