484 lines
53 KiB
Plaintext
484 lines
53 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1461109 # Simulator instruction rate (inst/s)
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host_mem_usage 340352 # Number of bytes of host memory used
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host_seconds 34.61 # Real time elapsed on the host
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host_tick_rate 3314430509 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 50572425 # Number of instructions simulated
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sim_seconds 0.114721 # Number of seconds simulated
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sim_ticks 114721074000 # Number of ticks simulated
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system.cpu.dcache.LoadLockedReq_accesses::0 100214 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 100214 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15147.115385 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12147.115385 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
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system.cpu.dcache.LoadLockedReq_hits::0 95014 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 95014 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 78765000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051889 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses::0 5200 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_misses::total 5200 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63165000 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051889 # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_misses 5200 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310267000 # number of LoadLockedReq MSHR uncacheable cycles
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system.cpu.dcache.ReadReq_accesses::0 7824780 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 7824780 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency::0 15798.342892 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12798.015358 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu.dcache.ReadReq_hits::0 7588163 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 7588163 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 3738156500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate::0 0.030239 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses::0 236617 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 236617 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 3028228000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030239 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 236617 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38190415500 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses::0 100213 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 100213 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits::0 100213 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 100213 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses::0 6671860 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6671860 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency::0 40836.063764 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37835.781907 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu.dcache.WriteReq_hits::0 6499787 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 6499787 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 7026784000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate::0 0.025791 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses::0 172073 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 172073 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 6510516500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025791 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 172073 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926046500 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 34.660375 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses::0 14496640 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 14496640 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::0 26340.112310 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency
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system.cpu.dcache.demand_hits::0 14087950 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 14087950 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 10764940500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate::0 0.028192 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu.dcache.demand_misses::0 408690 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 408690 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 9538744500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::0 0.028192 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 408690 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.994530 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 509.199113 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses::0 14496640 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 14496640 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::0 26340.112310 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits::0 14087950 # number of overall hits
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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system.cpu.dcache.overall_hits::total 14087950 # number of overall hits
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system.cpu.dcache.overall_miss_latency 10764940500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate::0 0.028192 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.dcache.overall_misses::0 408690 # number of overall misses
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system.cpu.dcache.overall_misses::1 0 # number of overall misses
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system.cpu.dcache.overall_misses::total 408690 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 9538744500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate::0 0.028192 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 408690 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 39116462000 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 411628 # number of replacements
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system.cpu.dcache.sampled_refs 412140 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 509.199113 # Cycle average of tags in use
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system.cpu.dcache.total_refs 14284927 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 382676 # number of writebacks
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system.cpu.dtb.accesses 15524935 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 2199 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 15519414 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 5521 # DTB misses
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system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 756 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 8740303 # DTB read accesses
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system.cpu.dtb.read_hits 8735762 # DTB read hits
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system.cpu.dtb.read_misses 4541 # DTB read misses
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system.cpu.dtb.write_accesses 6784632 # DTB write accesses
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system.cpu.dtb.write_hits 6783652 # DTB write hits
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system.cpu.dtb.write_misses 980 # DTB write misses
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system.cpu.icache.ReadReq_accesses::0 41543801 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 41543801 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency::0 14800.791885 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 11799.492843 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu.icache.ReadReq_hits::0 41110405 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 41110405 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 6414604000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate::0 0.010432 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses::0 433396 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 433396 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 5113853000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010432 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 433396 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 94.856667 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses::0 41543801 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 41543801 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency::0 14800.791885 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency
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system.cpu.icache.demand_hits::0 41110405 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 41110405 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 6414604000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate::0 0.010432 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu.icache.demand_misses::0 433396 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 433396 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 5113853000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate::0 0.010432 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 433396 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.945788 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 484.243503 # Average occupied blocks per context
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system.cpu.icache.overall_accesses::0 41543801 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 41543801 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency::0 14800.791885 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits::0 41110405 # number of overall hits
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system.cpu.icache.overall_hits::1 0 # number of overall hits
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system.cpu.icache.overall_hits::total 41110405 # number of overall hits
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system.cpu.icache.overall_miss_latency 6414604000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate::0 0.010432 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.icache.overall_misses::0 433396 # number of overall misses
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system.cpu.icache.overall_misses::1 0 # number of overall misses
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system.cpu.icache.overall_misses::total 433396 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 5113853000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate::0 0.010432 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 433396 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.replacements 432883 # number of replacements
|
|
system.cpu.icache.sampled_refs 433395 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 484.243503 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 41110405 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks 33555 # number of writebacks
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu.itb.accesses 41546620 # DTB accesses
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.hits 41543801 # DTB hits
|
|
system.cpu.itb.inst_accesses 41546620 # ITB inst accesses
|
|
system.cpu.itb.inst_hits 41543801 # ITB inst hits
|
|
system.cpu.itb.inst_misses 2819 # ITB inst misses
|
|
system.cpu.itb.misses 2819 # DTB misses
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu.numCycles 229442148 # number of cpu cycles simulated
|
|
system.cpu.num_insts 50572425 # Number of instructions executed
|
|
system.cpu.num_refs 16289993 # Number of memory references
|
|
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
|
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
|
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
system.iocache.overall_misses::1 0 # number of overall misses
|
|
system.iocache.overall_misses::total 0 # number of overall misses
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.writebacks 0 # number of writebacks
|
|
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
|
|
system.l2c.LoadLockedReq_mshr_uncacheable_latency 234160000 # number of LoadLockedReq MSHR uncacheable cycles
|
|
system.l2c.ReadExReq_accesses::0 170323 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 170323 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_hits::0 62071 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 62071 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_miss_latency 5629104000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_rate::0 0.635569 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses::0 108252 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 108252 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_mshr_miss_latency 4330080000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 0.635569 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_misses 108252 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadReq_accesses::0 673101 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::1 5652 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 678753 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_avg_miss_latency::0 52096.523258 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::1 28127657.142857 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 28179753.666115 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_hits::0 654204 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::1 5617 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 659821 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_latency 984468000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_rate::0 0.028075 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::1 0.006192 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.034267 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses::0 18897 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::1 35 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 18932 # number of ReadReq misses
|
|
system.l2c.ReadReq_mshr_miss_latency 757280000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.028127 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::1 3.349611 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 3.377737 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_misses 18932 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 29199338000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.UpgradeReq_accesses::0 1750 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 1750 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 660.126947 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_miss_latency 1144000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_rate::0 0.990286 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses::0 1733 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 1733 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency 69320000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 0.990286 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_misses 1733 # number of UpgradeReq MSHR misses
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.Writeback_accesses::0 416231 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 416231 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits::0 416231 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 416231 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 6.975292 # Average number of references to valid blocks.
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses::0 843424 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::1 5652 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 849076 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency::0 52014.345374 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::1 188959200 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 189011214.345374 # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
system.l2c.demand_hits::0 716275 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::1 5617 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 721892 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 6613572000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate::0 0.150753 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::1 0.006192 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.156946 # miss rate for demand accesses
|
|
system.l2c.demand_misses::0 127149 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::1 35 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 127184 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 5087360000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate::0 0.150795 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::1 22.502477 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 22.653272 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 127184 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.occ_%::0 0.086431 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::1 0.477933 # Average percentage of cache occupancy
|
|
system.l2c.occ_blocks::0 5664.361976 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::1 31321.847814 # Average occupied blocks per context
|
|
system.l2c.overall_accesses::0 843424 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::1 5652 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 849076 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency::0 52014.345374 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::1 188959200 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 189011214.345374 # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits::0 716275 # number of overall hits
|
|
system.l2c.overall_hits::1 5617 # number of overall hits
|
|
system.l2c.overall_hits::total 721892 # number of overall hits
|
|
system.l2c.overall_miss_latency 6613572000 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate::0 0.150753 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::1 0.006192 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.156946 # miss rate for overall accesses
|
|
system.l2c.overall_misses::0 127149 # number of overall misses
|
|
system.l2c.overall_misses::1 35 # number of overall misses
|
|
system.l2c.overall_misses::total 127184 # number of overall misses
|
|
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 5087360000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate::0 0.150795 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::1 22.502477 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 22.653272 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 127184 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 29939182000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.replacements 94170 # number of replacements
|
|
system.l2c.sampled_refs 125831 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 36986.209790 # Cycle average of tags in use
|
|
system.l2c.total_refs 877708 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 87626 # number of writebacks
|
|
|
|
---------- End Simulation Statistics ----------
|