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ARM: Decode the thumb versions of the mcr and mrc instructions.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:08 -05:00
parent 625a43e7c7
commit 8c1be04af6
2 changed files with 39 additions and 6 deletions
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14
src/arch/arm/isa/decoder/thumb.isa
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@ -90,9 +90,12 @@
}
0x1: decode LTCOPROC {
0xa, 0xb: WarnUnimpl::Core_to_extension_transfer();
default: decode CPNUM {
15: McrMrc15::mcrMrc15();
default: decode HTOPCODE_4 {
0x0: WarnUnimpl::mcr(); // mcr2
0x1: WarnUnimpl::mrc(); // mrc2
0x0: WarnUnimpl::mcr();
0x1: WarnUnimpl::mrc();
}
}
}
}
@ -155,9 +158,12 @@
}
0x1: decode LTCOPROC {
0xa, 0xb: WarnUnimpl::Core_to_extension_transfer();
default: decode CPNUM {
15: McrMrc15::mcr2Mrc215();
default: decode HTOPCODE_4 {
0x0: WarnUnimpl::mcr(); // mcr2
0x1: WarnUnimpl::mrc(); // mrc2
0x0: WarnUnimpl::mcr2();
0x1: WarnUnimpl::mrc2();
}
}
}
}

27
src/arch/arm/isa/formats/misc.isa
View file

@ -77,3 +77,30 @@ def format ArmMsrMrs() {{
}
'''
}};
def format McrMrc15() {{
decode_block = '''
{
const uint32_t opc1 = bits(machInst, 23, 21);
const uint32_t crn = bits(machInst, 19, 16);
const uint32_t opc2 = bits(machInst, 7, 5);
const uint32_t crm = bits(machInst, 3, 0);
const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
const bool isRead = bits(machInst, 20);
if (miscReg == MISCREG_NOP) {
return new NopInst(machInst);
} else if (miscReg == NUM_MISCREGS) {
return new Unknown(machInst);
} else {
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
} else {
return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
}
}
}
'''
}};