diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa index da8248683..e8e2d5919 100644 --- a/src/arch/arm/isa/decoder/thumb.isa +++ b/src/arch/arm/isa/decoder/thumb.isa @@ -90,9 +90,12 @@ } 0x1: decode LTCOPROC { 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); - default: decode HTOPCODE_4 { - 0x0: WarnUnimpl::mcr(); // mcr2 - 0x1: WarnUnimpl::mrc(); // mrc2 + default: decode CPNUM { + 15: McrMrc15::mcrMrc15(); + default: decode HTOPCODE_4 { + 0x0: WarnUnimpl::mcr(); + 0x1: WarnUnimpl::mrc(); + } } } } @@ -155,9 +158,12 @@ } 0x1: decode LTCOPROC { 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); - default: decode HTOPCODE_4 { - 0x0: WarnUnimpl::mcr(); // mcr2 - 0x1: WarnUnimpl::mrc(); // mrc2 + default: decode CPNUM { + 15: McrMrc15::mcr2Mrc215(); + default: decode HTOPCODE_4 { + 0x0: WarnUnimpl::mcr2(); + 0x1: WarnUnimpl::mrc2(); + } } } } diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 36bccbba4..897ecf3e3 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -77,3 +77,30 @@ def format ArmMsrMrs() {{ } ''' }}; + +def format McrMrc15() {{ + decode_block = ''' + { + const uint32_t opc1 = bits(machInst, 23, 21); + const uint32_t crn = bits(machInst, 19, 16); + const uint32_t opc2 = bits(machInst, 7, 5); + const uint32_t crm = bits(machInst, 3, 0); + const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2); + const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); + + const bool isRead = bits(machInst, 20); + + if (miscReg == MISCREG_NOP) { + return new NopInst(machInst); + } else if (miscReg == NUM_MISCREGS) { + return new Unknown(machInst); + } else { + if (isRead) { + return new Mrc15(machInst, rt, (IntRegIndex)miscReg); + } else { + return new Mcr15(machInst, (IntRegIndex)miscReg, rt); + } + } + } + ''' +}};