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ruby: move files from ruby/system to ruby/structures

Browse source 
The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures.  This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.

The directory ruby/systems has the glue code that holds these structures
together.

--HG--
rename : src/mem/ruby/system/MachineID.hh => src/mem/ruby/common/MachineID.hh
rename : src/mem/ruby/buffers/MessageBuffer.cc => src/mem/ruby/network/MessageBuffer.cc
rename : src/mem/ruby/buffers/MessageBuffer.hh => src/mem/ruby/network/MessageBuffer.hh
rename : src/mem/ruby/buffers/MessageBufferNode.cc => src/mem/ruby/network/MessageBufferNode.cc
rename : src/mem/ruby/buffers/MessageBufferNode.hh => src/mem/ruby/network/MessageBufferNode.hh
rename : src/mem/ruby/system/AbstractReplacementPolicy.hh => src/mem/ruby/structures/AbstractReplacementPolicy.hh
rename : src/mem/ruby/system/BankedArray.cc => src/mem/ruby/structures/BankedArray.cc
rename : src/mem/ruby/system/BankedArray.hh => src/mem/ruby/structures/BankedArray.hh
rename : src/mem/ruby/system/Cache.py => src/mem/ruby/structures/Cache.py
rename : src/mem/ruby/system/CacheMemory.cc => src/mem/ruby/structures/CacheMemory.cc
rename : src/mem/ruby/system/CacheMemory.hh => src/mem/ruby/structures/CacheMemory.hh
rename : src/mem/ruby/system/DirectoryMemory.cc => src/mem/ruby/structures/DirectoryMemory.cc
rename : src/mem/ruby/system/DirectoryMemory.hh => src/mem/ruby/structures/DirectoryMemory.hh
rename : src/mem/ruby/system/DirectoryMemory.py => src/mem/ruby/structures/DirectoryMemory.py
rename : src/mem/ruby/system/LRUPolicy.hh => src/mem/ruby/structures/LRUPolicy.hh
rename : src/mem/ruby/system/MemoryControl.cc => src/mem/ruby/structures/MemoryControl.cc
rename : src/mem/ruby/system/MemoryControl.hh => src/mem/ruby/structures/MemoryControl.hh
rename : src/mem/ruby/system/MemoryControl.py => src/mem/ruby/structures/MemoryControl.py
rename : src/mem/ruby/system/MemoryNode.cc => src/mem/ruby/structures/MemoryNode.cc
rename : src/mem/ruby/system/MemoryNode.hh => src/mem/ruby/structures/MemoryNode.hh
rename : src/mem/ruby/system/MemoryVector.hh => src/mem/ruby/structures/MemoryVector.hh
rename : src/mem/ruby/system/PerfectCacheMemory.hh => src/mem/ruby/structures/PerfectCacheMemory.hh
rename : src/mem/ruby/system/PersistentTable.cc => src/mem/ruby/structures/PersistentTable.cc
rename : src/mem/ruby/system/PersistentTable.hh => src/mem/ruby/structures/PersistentTable.hh
rename : src/mem/ruby/system/PseudoLRUPolicy.hh => src/mem/ruby/structures/PseudoLRUPolicy.hh
rename : src/mem/ruby/system/RubyMemoryControl.cc => src/mem/ruby/structures/RubyMemoryControl.cc
rename : src/mem/ruby/system/RubyMemoryControl.hh => src/mem/ruby/structures/RubyMemoryControl.hh
rename : src/mem/ruby/system/RubyMemoryControl.py => src/mem/ruby/structures/RubyMemoryControl.py
rename : src/mem/ruby/system/SparseMemory.cc => src/mem/ruby/structures/SparseMemory.cc
rename : src/mem/ruby/system/SparseMemory.hh => src/mem/ruby/structures/SparseMemory.hh
rename : src/mem/ruby/system/TBETable.hh => src/mem/ruby/structures/TBETable.hh
rename : src/mem/ruby/system/TimerTable.cc => src/mem/ruby/structures/TimerTable.cc
rename : src/mem/ruby/system/TimerTable.hh => src/mem/ruby/structures/TimerTable.hh
rename : src/mem/ruby/system/WireBuffer.cc => src/mem/ruby/structures/WireBuffer.cc
rename : src/mem/ruby/system/WireBuffer.hh => src/mem/ruby/structures/WireBuffer.hh
rename : src/mem/ruby/system/WireBuffer.py => src/mem/ruby/structures/WireBuffer.py
rename : src/mem/ruby/recorder/CacheRecorder.cc => src/mem/ruby/system/CacheRecorder.cc
rename : src/mem/ruby/recorder/CacheRecorder.hh => src/mem/ruby/system/CacheRecorder.hh
This commit is contained in:
Nilay Vaish 2014-09-01 16:55:40 -05:00
parent 01f792a367
commit 82d136285d
60 changed files with 90 additions and 159 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
src/mem/ruby/SConscript
View file

@ -118,21 +118,21 @@ MakeInclude('slicc_interface/NetworkMessage.hh')
MakeInclude('slicc_interface/RubyRequest.hh')
# External types
MakeInclude('buffers/MessageBuffer.hh')
MakeInclude('common/Address.hh')
MakeInclude('common/DataBlock.hh')
MakeInclude('common/MachineID.hh')
MakeInclude('common/NetDest.hh')
MakeInclude('common/Set.hh')
MakeInclude('filters/GenericBloomFilter.hh')
MakeInclude('network/MessageBuffer.hh')
MakeInclude('structures/Prefetcher.hh')
MakeInclude('system/CacheMemory.hh')
MakeInclude('structures/CacheMemory.hh')
MakeInclude('system/DMASequencer.hh')
MakeInclude('system/DirectoryMemory.hh')
MakeInclude('system/MachineID.hh')
MakeInclude('system/MemoryControl.hh')
MakeInclude('system/WireBuffer.hh')
MakeInclude('system/PerfectCacheMemory.hh')
MakeInclude('system/PersistentTable.hh')
MakeInclude('structures/DirectoryMemory.hh')
MakeInclude('structures/MemoryControl.hh')
MakeInclude('structures/WireBuffer.hh')
MakeInclude('structures/PerfectCacheMemory.hh')
MakeInclude('structures/PersistentTable.hh')
MakeInclude('system/Sequencer.hh')
MakeInclude('system/TBETable.hh')
MakeInclude('system/TimerTable.hh')
MakeInclude('structures/TBETable.hh')
MakeInclude('structures/TimerTable.hh')

37
src/mem/ruby/buffers/SConscript
View file

@ -1,37 +0,0 @@
# -*- mode:python -*-
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
Import('*')
if env['PROTOCOL'] == 'None':
Return()
Source('MessageBuffer.cc')
Source('MessageBufferNode.cc')

0
src/mem/ruby/system/MachineID.hh → src/mem/ruby/common/MachineID.hh
View file

2
src/mem/ruby/common/NetDest.hh
View file

@ -38,7 +38,7 @@
#include <vector>
#include "mem/ruby/common/Set.hh"
#include "mem/ruby/system/MachineID.hh"
#include "mem/ruby/common/MachineID.hh"
class NetDest
{

2
src/mem/ruby/buffers/MessageBuffer.cc → src/mem/ruby/network/MessageBuffer.cc
View file

@ -32,7 +32,7 @@
#include "base/misc.hh"
#include "base/stl_helpers.hh"
#include "debug/RubyQueue.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/system/System.hh"
using namespace std;

4
src/mem/ruby/buffers/MessageBuffer.hh → src/mem/ruby/network/MessageBuffer.hh
View file

@ -41,11 +41,11 @@
#include <string>
#include <vector>
#include "mem/packet.hh"
#include "mem/ruby/buffers/MessageBufferNode.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/network/MessageBufferNode.hh"
#include "mem/ruby/slicc_interface/Message.hh"
#include "mem/packet.hh"
class MessageBuffer
{

2
src/mem/ruby/buffers/MessageBufferNode.cc → src/mem/ruby/network/MessageBufferNode.cc
View file

@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/buffers/MessageBufferNode.hh"
#include "mem/ruby/network/MessageBufferNode.hh"
void
MessageBufferNode::print(std::ostream& out) const

0
src/mem/ruby/buffers/MessageBufferNode.hh → src/mem/ruby/network/MessageBufferNode.hh
View file

2
src/mem/ruby/network/SConscript
View file

@ -39,5 +39,7 @@ SimObject('Network.py')
Source('BasicLink.cc')
Source('BasicRouter.cc')
Source('MessageBuffer.cc')
Source('MessageBufferNode.cc')
Source('Network.cc')
Source('Topology.cc')

2
src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
View file

@ -28,8 +28,8 @@
* Authors: Niket Agarwal
*/
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/garnet/BaseGarnetNetwork.hh"
#include "mem/ruby/network/MessageBuffer.hh"
using namespace std;

2
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
View file

@ -34,7 +34,7 @@
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh"
#include "mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh"
#include "mem/ruby/slicc_interface/NetworkMessage.hh"

2
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
View file

@ -34,7 +34,7 @@
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh"
#include "mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh"
#include "mem/ruby/slicc_interface/NetworkMessage.hh"

2
src/mem/ruby/network/simple/PerfectSwitch.cc
View file

@ -30,7 +30,7 @@
#include "base/cast.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/simple/PerfectSwitch.hh"
#include "mem/ruby/network/simple/SimpleNetwork.hh"
#include "mem/ruby/network/simple/Switch.hh"

2
src/mem/ruby/network/simple/SimpleNetwork.cc
View file

@ -31,8 +31,8 @@
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/simple/SimpleLink.hh"
#include "mem/ruby/network/simple/SimpleNetwork.hh"
#include "mem/ruby/network/simple/Switch.hh"

2
src/mem/ruby/network/simple/Switch.cc
View file

@ -30,7 +30,7 @@
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/simple/PerfectSwitch.hh"
#include "mem/ruby/network/simple/SimpleNetwork.hh"
#include "mem/ruby/network/simple/Switch.hh"

2
src/mem/ruby/network/simple/Throttle.cc
View file

@ -31,8 +31,8 @@
#include "base/cast.hh"
#include "base/cprintf.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/simple/Throttle.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/slicc_interface/NetworkMessage.hh"
#include "mem/ruby/system/System.hh"

2
src/mem/ruby/profiler/Profiler.hh
View file

@ -57,7 +57,7 @@
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/MachineID.hh"
#include "mem/ruby/common/MachineID.hh"
#include "params/RubySystem.hh"
class RubyRequest;

36
src/mem/ruby/recorder/SConscript
View file

@ -1,36 +0,0 @@
# -*- mode:python -*-
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
Import('*')
if env['PROTOCOL'] == 'None':
Return()
Source('CacheRecorder.cc')

6
src/mem/ruby/slicc_interface/AbstractController.hh
View file

@ -34,14 +34,14 @@
#include "base/callback.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/Histogram.hh"
#include "mem/ruby/common/MachineID.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/recorder/CacheRecorder.hh"
#include "mem/ruby/system/MachineID.hh"
#include "mem/ruby/system/CacheRecorder.hh"
#include "mem/packet.hh"
#include "params/RubyController.hh"
#include "sim/clocked_object.hh"

4
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
View file

@ -31,9 +31,9 @@
#include "mem/protocol/MachineType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/MachineID.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/system/DirectoryMemory.hh"
#include "mem/ruby/system/MachineID.hh"
#include "mem/ruby/structures/DirectoryMemory.hh"
// used to determine the home directory
// returns a value between 0 and total_directories_within_the_system

0
src/mem/ruby/system/AbstractReplacementPolicy.hh → src/mem/ruby/structures/AbstractReplacementPolicy.hh
View file

2
src/mem/ruby/system/BankedArray.cc → src/mem/ruby/structures/BankedArray.cc
View file

@ -30,7 +30,7 @@
*/
#include "base/intmath.hh"
#include "mem/ruby/system/BankedArray.hh"
#include "mem/ruby/structures/BankedArray.hh"
#include "mem/ruby/system/System.hh"
BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,

0
src/mem/ruby/system/BankedArray.hh → src/mem/ruby/structures/BankedArray.hh
View file

2
src/mem/ruby/system/Cache.py → src/mem/ruby/structures/Cache.py
View file

@ -34,7 +34,7 @@ from Controller import RubyController
class RubyCache(SimObject):
type = 'RubyCache'
cxx_class = 'CacheMemory'
cxx_header = "mem/ruby/system/CacheMemory.hh"
cxx_header = "mem/ruby/structures/CacheMemory.hh"
size = Param.MemorySize("capacity in bytes");
latency = Param.Cycles("");
assoc = Param.Int("");

2
src/mem/ruby/system/CacheMemory.cc → src/mem/ruby/structures/CacheMemory.cc
View file

@ -32,7 +32,7 @@
#include "debug/RubyResourceStalls.hh"
#include "debug/RubyStats.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/system/CacheMemory.hh"
#include "mem/ruby/structures/CacheMemory.hh"
#include "mem/ruby/system/System.hh"
using namespace std;

10
src/mem/ruby/system/CacheMemory.hh → src/mem/ruby/structures/CacheMemory.hh
View file

@ -34,16 +34,16 @@
#include "base/hashmap.hh"
#include "base/statistics.hh"
#include "mem/protocol/CacheResourceType.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/CacheResourceType.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/recorder/CacheRecorder.hh"
#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
#include "mem/ruby/system/BankedArray.hh"
#include "mem/ruby/system/LRUPolicy.hh"
#include "mem/ruby/system/PseudoLRUPolicy.hh"
#include "mem/ruby/structures/BankedArray.hh"
#include "mem/ruby/structures/LRUPolicy.hh"
#include "mem/ruby/structures/PseudoLRUPolicy.hh"
#include "mem/ruby/system/CacheRecorder.hh"
#include "params/RubyCache.hh"
#include "sim/sim_object.hh"

2
src/mem/ruby/system/DirectoryMemory.cc → src/mem/ruby/structures/DirectoryMemory.cc
View file

@ -30,7 +30,7 @@
#include "debug/RubyCache.hh"
#include "debug/RubyStats.hh"
#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
#include "mem/ruby/system/DirectoryMemory.hh"
#include "mem/ruby/structures/DirectoryMemory.hh"
#include "mem/ruby/system/System.hh"
using namespace std;

6
src/mem/ruby/system/DirectoryMemory.hh → src/mem/ruby/structures/DirectoryMemory.hh
View file

@ -32,11 +32,11 @@
#include <iostream>
#include <string>
#include "mem/ruby/common/Address.hh"
#include "mem/protocol/DirectoryRequestType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/slicc_interface/AbstractEntry.hh"
#include "mem/ruby/system/MemoryVector.hh"
#include "mem/ruby/system/SparseMemory.hh"
#include "mem/ruby/structures/MemoryVector.hh"
#include "mem/ruby/structures/SparseMemory.hh"
#include "params/RubyDirectoryMemory.hh"
#include "sim/sim_object.hh"

2
src/mem/ruby/system/DirectoryMemory.py → src/mem/ruby/structures/DirectoryMemory.py
View file

@ -34,7 +34,7 @@ from m5.SimObject import SimObject
class RubyDirectoryMemory(SimObject):
type = 'RubyDirectoryMemory'
cxx_class = 'DirectoryMemory'
cxx_header = "mem/ruby/system/DirectoryMemory.hh"
cxx_header = "mem/ruby/structures/DirectoryMemory.hh"
version = Param.Int(0, "")
size = Param.MemorySize("1GB", "capacity in bytes")
use_map = Param.Bool(False, "enable sparse memory")

2
src/mem/ruby/system/LRUPolicy.hh → src/mem/ruby/structures/LRUPolicy.hh
View file

@ -29,7 +29,7 @@
#ifndef __MEM_RUBY_SYSTEM_LRUPOLICY_HH__
#define __MEM_RUBY_SYSTEM_LRUPOLICY_HH__
#include "mem/ruby/system/AbstractReplacementPolicy.hh"
#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
/* Simple true LRU replacement policy */

2
src/mem/ruby/system/MemoryControl.cc → src/mem/ruby/structures/MemoryControl.cc
View file

@ -30,7 +30,7 @@
#include "debug/RubyStats.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
#include "mem/ruby/system/MemoryControl.hh"
#include "mem/ruby/structures/MemoryControl.hh"
#include "mem/ruby/system/System.hh"
using namespace std;

2
src/mem/ruby/system/MemoryControl.hh → src/mem/ruby/structures/MemoryControl.hh
View file

@ -37,7 +37,7 @@
#include "mem/protocol/MemoryControlRequestType.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/slicc_interface/Message.hh"
#include "mem/ruby/system/MemoryNode.hh"
#include "mem/ruby/structures/MemoryNode.hh"
#include "params/MemoryControl.hh"
#include "sim/clocked_object.hh"

2
src/mem/ruby/system/MemoryControl.py → src/mem/ruby/structures/MemoryControl.py
View file

@ -34,6 +34,6 @@ class MemoryControl(ClockedObject):
abstract = True
type = 'MemoryControl'
cxx_class = 'MemoryControl'
cxx_header = "mem/ruby/system/MemoryControl.hh"
cxx_header = "mem/ruby/structures/MemoryControl.hh"
version = Param.Int("");
ruby_system = Param.RubySystem("")

2
src/mem/ruby/system/MemoryNode.cc → src/mem/ruby/structures/MemoryNode.cc
View file

@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/system/MemoryNode.hh"
#include "mem/ruby/structures/MemoryNode.hh"
using namespace std;

0
src/mem/ruby/system/MemoryNode.hh → src/mem/ruby/structures/MemoryNode.hh
View file

0
src/mem/ruby/system/MemoryVector.hh → src/mem/ruby/structures/MemoryVector.hh
View file

0
src/mem/ruby/system/PerfectCacheMemory.hh → src/mem/ruby/structures/PerfectCacheMemory.hh
View file

2
src/mem/ruby/system/PersistentTable.cc → src/mem/ruby/structures/PersistentTable.cc
View file

@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/system/PersistentTable.hh"
#include "mem/ruby/structures/PersistentTable.hh"
using namespace std;

2
src/mem/ruby/system/PersistentTable.hh → src/mem/ruby/structures/PersistentTable.hh
View file

@ -34,8 +34,8 @@
#include "base/hashmap.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/MachineID.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/system/MachineID.hh"
class PersistentTableEntry
{

2
src/mem/ruby/structures/Prefetcher.hh
View file

@ -34,8 +34,8 @@
#include <bitset>
#include "base/statistics.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/slicc_interface/RubyRequest.hh"
#include "mem/ruby/system/System.hh"

2
src/mem/ruby/system/PseudoLRUPolicy.hh → src/mem/ruby/structures/PseudoLRUPolicy.hh
View file

@ -29,7 +29,7 @@
#ifndef __MEM_RUBY_SYSTEM_PSEUDOLRUPOLICY_HH__
#define __MEM_RUBY_SYSTEM_PSEUDOLRUPOLICY_HH__
#include "mem/ruby/system/AbstractReplacementPolicy.hh"
#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
/**
* Implementation of tree-based pseudo-LRU replacement

2
src/mem/ruby/system/RubyMemoryControl.cc → src/mem/ruby/structures/RubyMemoryControl.cc
View file

@ -113,7 +113,7 @@
#include "mem/ruby/profiler/Profiler.hh"
#include "mem/ruby/slicc_interface/NetworkMessage.hh"
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
#include "mem/ruby/system/RubyMemoryControl.hh"
#include "mem/ruby/structures/RubyMemoryControl.hh"
#include "mem/ruby/system/System.hh"
using namespace std;

4
src/mem/ruby/system/RubyMemoryControl.hh → src/mem/ruby/structures/RubyMemoryControl.hh
View file

@ -40,8 +40,8 @@
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/profiler/MemCntrlProfiler.hh"
#include "mem/ruby/slicc_interface/Message.hh"
#include "mem/ruby/system/MemoryControl.hh"
#include "mem/ruby/system/MemoryNode.hh"
#include "mem/ruby/structures/MemoryControl.hh"
#include "mem/ruby/structures/MemoryNode.hh"
#include "mem/ruby/system/System.hh"
#include "params/RubyMemoryControl.hh"
#include "sim/sim_object.hh"

2
src/mem/ruby/system/RubyMemoryControl.py → src/mem/ruby/structures/RubyMemoryControl.py
View file

@ -34,7 +34,7 @@ from MemoryControl import MemoryControl
class RubyMemoryControl(MemoryControl):
type = 'RubyMemoryControl'
cxx_class = 'RubyMemoryControl'
cxx_header = "mem/ruby/system/RubyMemoryControl.hh"
cxx_header = "mem/ruby/structures/RubyMemoryControl.hh"
version = Param.Int("");
banks_per_rank = Param.Int(8, "");

16
src/mem/ruby/structures/SConscript
View file

@ -33,5 +33,21 @@ Import('*')
if env['PROTOCOL'] == 'None':
Return()
SimObject('Cache.py')
SimObject('DirectoryMemory.py')
SimObject('MemoryControl.py')
SimObject('RubyMemoryControl.py')
SimObject('RubyPrefetcher.py')
SimObject('WireBuffer.py')
Source('DirectoryMemory.cc')
Source('SparseMemory.cc')
Source('CacheMemory.cc')
Source('MemoryControl.cc')
Source('WireBuffer.cc')
Source('RubyMemoryControl.cc')
Source('MemoryNode.cc')
Source('PersistentTable.cc')
Source('Prefetcher.cc')
Source('TimerTable.cc')
Source('BankedArray.cc')

4
src/mem/ruby/system/SparseMemory.cc → src/mem/ruby/structures/SparseMemory.cc
View file

@ -30,7 +30,7 @@
#include <queue>
#include "debug/RubyCache.hh"
#include "mem/ruby/system/SparseMemory.hh"
#include "mem/ruby/structures/SparseMemory.hh"
#include "mem/ruby/system/System.hh"
using namespace std;
@ -39,7 +39,7 @@ SparseMemory::SparseMemory(int number_of_levels)
{
int even_level_bits;
int extra;
m_total_number_of_bits = RubySystem::getMemorySizeBits()
m_total_number_of_bits = RubySystem::getMemorySizeBits()
- RubySystem::getBlockSizeBits();;
m_number_of_levels = number_of_levels;

2
src/mem/ruby/system/SparseMemory.hh → src/mem/ruby/structures/SparseMemory.hh
View file

@ -36,8 +36,8 @@
#include "base/hashmap.hh"
#include "base/statistics.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/recorder/CacheRecorder.hh"
#include "mem/ruby/slicc_interface/AbstractEntry.hh"
#include "mem/ruby/system/CacheRecorder.hh"
typedef void* SparseMemEntry;
typedef m5::hash_map<Address, SparseMemEntry> SparseMapType;

0
src/mem/ruby/system/TBETable.hh → src/mem/ruby/structures/TBETable.hh
View file

2
src/mem/ruby/system/TimerTable.cc → src/mem/ruby/structures/TimerTable.cc
View file

@ -27,8 +27,8 @@
*/
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/structures/TimerTable.hh"
#include "mem/ruby/system/System.hh"
#include "mem/ruby/system/TimerTable.hh"
TimerTable::TimerTable()
: m_next_time(0)

0
src/mem/ruby/system/TimerTable.hh → src/mem/ruby/structures/TimerTable.hh
View file

2
src/mem/ruby/system/WireBuffer.cc → src/mem/ruby/structures/WireBuffer.cc
View file

@ -35,8 +35,8 @@
#include "base/cprintf.hh"
#include "base/stl_helpers.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/structures/WireBuffer.hh"
#include "mem/ruby/system/System.hh"
#include "mem/ruby/system/WireBuffer.hh"
using namespace std;

4
src/mem/ruby/system/WireBuffer.hh → src/mem/ruby/structures/WireBuffer.hh
View file

@ -36,8 +36,8 @@
#include <string>
#include <vector>
#include "mem/ruby/buffers/MessageBufferNode.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/network/MessageBufferNode.hh"
#include "params/RubyWireBuffer.hh"
#include "sim/sim_object.hh"
@ -51,7 +51,7 @@
// separated by a network in real systems to simplify coherence.
/////////////////////////////////////////////////////////////////////////////
class Message;
class Message;
class WireBuffer : public SimObject
{

2
src/mem/ruby/system/WireBuffer.py → src/mem/ruby/structures/WireBuffer.py
View file

@ -32,4 +32,4 @@ from m5.SimObject import SimObject
class RubyWireBuffer(SimObject):
type = 'RubyWireBuffer'
cxx_class = 'WireBuffer'
cxx_header = "mem/ruby/system/WireBuffer.hh"
cxx_header = "mem/ruby/structures/WireBuffer.hh"

2
src/mem/ruby/recorder/CacheRecorder.cc → src/mem/ruby/system/CacheRecorder.cc
View file

@ -28,7 +28,7 @@
*/
#include "debug/RubyCacheTrace.hh"
#include "mem/ruby/recorder/CacheRecorder.hh"
#include "mem/ruby/system/CacheRecorder.hh"
#include "mem/ruby/system/Sequencer.hh"
#include "mem/ruby/system/System.hh"

0
src/mem/ruby/recorder/CacheRecorder.hh → src/mem/ruby/system/CacheRecorder.hh
View file

2
src/mem/ruby/system/RubyPort.hh
View file

@ -46,7 +46,7 @@
#include <string>
#include "mem/protocol/RequestStatus.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/system/System.hh"
#include "mem/mem_object.hh"
#include "mem/tport.hh"

16
src/mem/ruby/system/SConscript
View file

@ -33,26 +33,12 @@ Import('*')
if env['PROTOCOL'] == 'None':
Return()
SimObject('Cache.py')
SimObject('Sequencer.py')
SimObject('DirectoryMemory.py')
SimObject('MemoryControl.py')
SimObject('WireBuffer.py')
SimObject('RubySystem.py')
SimObject('RubyMemoryControl.py')
Source('CacheRecorder.cc')
Source('DMASequencer.cc')
Source('DirectoryMemory.cc')
Source('SparseMemory.cc')
Source('CacheMemory.cc')
Source('MemoryControl.cc')
Source('WireBuffer.cc')
Source('RubyMemoryControl.cc')
Source('MemoryNode.cc')
Source('PersistentTable.cc')
Source('RubyPort.cc')
Source('RubyPortProxy.cc')
Source('Sequencer.cc')
Source('System.cc')
Source('TimerTable.cc')
Source('BankedArray.cc')

2
src/mem/ruby/system/Sequencer.hh
View file

@ -36,7 +36,7 @@
#include "mem/protocol/RubyRequestType.hh"
#include "mem/protocol/SequencerRequestType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/system/CacheMemory.hh"
#include "mem/ruby/structures/CacheMemory.hh"
#include "mem/ruby/system/RubyPort.hh"
#include "params/RubySequencer.hh"

10
src/mem/ruby/system/System.hh
View file

@ -37,13 +37,13 @@
#include "base/callback.hh"
#include "base/output.hh"
#include "mem/packet.hh"
#include "mem/ruby/profiler/Profiler.hh"
#include "mem/ruby/recorder/CacheRecorder.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/system/MemoryControl.hh"
#include "mem/ruby/system/MemoryVector.hh"
#include "mem/ruby/system/SparseMemory.hh"
#include "mem/ruby/structures/MemoryControl.hh"
#include "mem/ruby/structures/MemoryVector.hh"
#include "mem/ruby/structures/SparseMemory.hh"
#include "mem/ruby/system/CacheRecorder.hh"
#include "mem/packet.hh"
#include "params/RubySystem.hh"
#include "sim/clocked_object.hh"

2
src/mem/slicc/symbols/Type.py
View file

@ -585,7 +585,7 @@ AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj)
for enum in self.enums.itervalues():
if enum.get("Primary"):
code('#include "mem/protocol/${{enum.ident}}_Controller.hh"')
code('#include "mem/ruby/system/MachineID.hh"')
code('#include "mem/ruby/common/MachineID.hh"')
code('''
// Code for output operator