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The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. --HG-- rename : src/mem/ruby/system/MachineID.hh => src/mem/ruby/common/MachineID.hh rename : src/mem/ruby/buffers/MessageBuffer.cc => src/mem/ruby/network/MessageBuffer.cc rename : src/mem/ruby/buffers/MessageBuffer.hh => src/mem/ruby/network/MessageBuffer.hh rename : src/mem/ruby/buffers/MessageBufferNode.cc => src/mem/ruby/network/MessageBufferNode.cc rename : src/mem/ruby/buffers/MessageBufferNode.hh => src/mem/ruby/network/MessageBufferNode.hh rename : src/mem/ruby/system/AbstractReplacementPolicy.hh => src/mem/ruby/structures/AbstractReplacementPolicy.hh rename : src/mem/ruby/system/BankedArray.cc => src/mem/ruby/structures/BankedArray.cc rename : src/mem/ruby/system/BankedArray.hh => src/mem/ruby/structures/BankedArray.hh rename : src/mem/ruby/system/Cache.py => src/mem/ruby/structures/Cache.py rename : src/mem/ruby/system/CacheMemory.cc => src/mem/ruby/structures/CacheMemory.cc rename : src/mem/ruby/system/CacheMemory.hh => src/mem/ruby/structures/CacheMemory.hh rename : src/mem/ruby/system/DirectoryMemory.cc => src/mem/ruby/structures/DirectoryMemory.cc rename : src/mem/ruby/system/DirectoryMemory.hh => src/mem/ruby/structures/DirectoryMemory.hh rename : src/mem/ruby/system/DirectoryMemory.py => src/mem/ruby/structures/DirectoryMemory.py rename : src/mem/ruby/system/LRUPolicy.hh => src/mem/ruby/structures/LRUPolicy.hh rename : src/mem/ruby/system/MemoryControl.cc => src/mem/ruby/structures/MemoryControl.cc rename : src/mem/ruby/system/MemoryControl.hh => src/mem/ruby/structures/MemoryControl.hh rename : src/mem/ruby/system/MemoryControl.py => src/mem/ruby/structures/MemoryControl.py rename : src/mem/ruby/system/MemoryNode.cc => src/mem/ruby/structures/MemoryNode.cc rename : src/mem/ruby/system/MemoryNode.hh => src/mem/ruby/structures/MemoryNode.hh rename : src/mem/ruby/system/MemoryVector.hh => src/mem/ruby/structures/MemoryVector.hh rename : src/mem/ruby/system/PerfectCacheMemory.hh => src/mem/ruby/structures/PerfectCacheMemory.hh rename : src/mem/ruby/system/PersistentTable.cc => src/mem/ruby/structures/PersistentTable.cc rename : src/mem/ruby/system/PersistentTable.hh => src/mem/ruby/structures/PersistentTable.hh rename : src/mem/ruby/system/PseudoLRUPolicy.hh => src/mem/ruby/structures/PseudoLRUPolicy.hh rename : src/mem/ruby/system/RubyMemoryControl.cc => src/mem/ruby/structures/RubyMemoryControl.cc rename : src/mem/ruby/system/RubyMemoryControl.hh => src/mem/ruby/structures/RubyMemoryControl.hh rename : src/mem/ruby/system/RubyMemoryControl.py => src/mem/ruby/structures/RubyMemoryControl.py rename : src/mem/ruby/system/SparseMemory.cc => src/mem/ruby/structures/SparseMemory.cc rename : src/mem/ruby/system/SparseMemory.hh => src/mem/ruby/structures/SparseMemory.hh rename : src/mem/ruby/system/TBETable.hh => src/mem/ruby/structures/TBETable.hh rename : src/mem/ruby/system/TimerTable.cc => src/mem/ruby/structures/TimerTable.cc rename : src/mem/ruby/system/TimerTable.hh => src/mem/ruby/structures/TimerTable.hh rename : src/mem/ruby/system/WireBuffer.cc => src/mem/ruby/structures/WireBuffer.cc rename : src/mem/ruby/system/WireBuffer.hh => src/mem/ruby/structures/WireBuffer.hh rename : src/mem/ruby/system/WireBuffer.py => src/mem/ruby/structures/WireBuffer.py rename : src/mem/ruby/recorder/CacheRecorder.cc => src/mem/ruby/system/CacheRecorder.cc rename : src/mem/ruby/recorder/CacheRecorder.hh => src/mem/ruby/system/CacheRecorder.hh
172 lines
6.1 KiB
C++
172 lines
6.1 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* Copyright (c) 2012 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_SYSTEM_MEMORY_CONTROL_HH__
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#define __MEM_RUBY_SYSTEM_MEMORY_CONTROL_HH__
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#include <iostream>
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#include <list>
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#include <string>
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#include "mem/protocol/MemoryMsg.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/ruby/common/Global.hh"
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#include "mem/ruby/profiler/MemCntrlProfiler.hh"
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#include "mem/ruby/slicc_interface/Message.hh"
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#include "mem/ruby/structures/MemoryControl.hh"
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#include "mem/ruby/structures/MemoryNode.hh"
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#include "mem/ruby/system/System.hh"
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#include "params/RubyMemoryControl.hh"
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#include "sim/sim_object.hh"
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// This constant is part of the definition of tFAW; see
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// the comments in header to RubyMemoryControl.cc
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#define ACTIVATE_PER_TFAW 4
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//////////////////////////////////////////////////////////////////////////////
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class RubyMemoryControl : public MemoryControl
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{
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public:
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typedef RubyMemoryControlParams Params;
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RubyMemoryControl(const Params *p);
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void init();
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void reset();
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~RubyMemoryControl();
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unsigned int drain(DrainManager *dm);
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void wakeup();
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void setConsumer(Consumer* consumer_ptr);
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Consumer* getConsumer() { return m_consumer_ptr; };
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void setDescription(const std::string& name) { m_description = name; };
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std::string getDescription() { return m_description; };
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// Called from the directory:
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void enqueue(const MsgPtr& message, Cycles latency);
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void enqueueMemRef(MemoryNode *memRef);
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void dequeue();
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const Message* peek();
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MemoryNode *peekNode();
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bool isReady();
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bool areNSlotsAvailable(int n) { return true; }; // infinite queue length
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void print(std::ostream& out) const;
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void regStats();
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const int getBank(const physical_address_t addr) const;
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const int getRank(const physical_address_t addr) const;
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// not used in Ruby memory controller
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const int getChannel(const physical_address_t addr) const;
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const int getRow(const physical_address_t addr) const;
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//added by SS
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int getBanksPerRank() { return m_banks_per_rank; };
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int getRanksPerDimm() { return m_ranks_per_dimm; };
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int getDimmsPerChannel() { return m_dimms_per_channel; }
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bool functionalReadBuffers(Packet *pkt);
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uint32_t functionalWriteBuffers(Packet *pkt);
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private:
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void enqueueToDirectory(MemoryNode *req, Cycles latency);
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const int getRank(int bank) const;
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bool queueReady(int bank);
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void issueRequest(int bank);
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bool issueRefresh(int bank);
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void markTfaw(int rank);
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void executeCycle();
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// Private copy constructor and assignment operator
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RubyMemoryControl (const RubyMemoryControl& obj);
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RubyMemoryControl& operator=(const RubyMemoryControl& obj);
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// data members
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Consumer* m_consumer_ptr; // Consumer to signal a wakeup()
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std::string m_description;
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int m_msg_counter;
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int m_banks_per_rank;
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int m_ranks_per_dimm;
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int m_dimms_per_channel;
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int m_bank_bit_0;
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int m_rank_bit_0;
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int m_dimm_bit_0;
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unsigned int m_bank_queue_size;
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int m_bank_busy_time;
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int m_rank_rank_delay;
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int m_read_write_delay;
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int m_basic_bus_busy_time;
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Cycles m_mem_ctl_latency;
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int m_refresh_period;
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int m_mem_random_arbitrate;
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int m_tFaw;
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Cycles m_mem_fixed_delay;
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int m_total_banks;
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int m_total_ranks;
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int m_refresh_period_system;
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// queues where memory requests live
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std::list<MemoryNode *> m_response_queue;
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std::list<MemoryNode *> m_input_queue;
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std::list<MemoryNode *>* m_bankQueues;
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// Each entry indicates number of address-bus cycles until bank
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// is reschedulable:
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int* m_bankBusyCounter;
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int* m_oldRequest;
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uint64* m_tfaw_shift;
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int* m_tfaw_count;
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// Each of these indicates number of address-bus cycles until
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// we can issue a new request of the corresponding type:
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int m_busBusyCounter_Write;
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int m_busBusyCounter_ReadNewRank;
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int m_busBusyCounter_Basic;
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int m_busBusy_WhichRank; // which rank last granted
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int m_roundRobin; // which bank queue was last granted
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int m_refresh_count; // cycles until next refresh
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int m_need_refresh; // set whenever m_refresh_count goes to zero
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int m_refresh_bank; // which bank to refresh next
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int m_ageCounter; // age of old requests; to detect starvation
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int m_idleCount; // watchdog timer for shutting down
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MemCntrlProfiler* m_profiler_ptr;
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};
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std::ostream& operator<<(std::ostream& out, const RubyMemoryControl& obj);
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#endif // __MEM_RUBY_SYSTEM_MEMORY_CONTROL_HH__
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