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Automated merge with ssh://hg@repo.m5sim.org/m5

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This commit is contained in:
Ali Saidi 2011-03-17 19:24:37 -05:00
commit 6daf44dae6
175 changed files with 9044 additions and 6417 deletions
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3
configs/common/Caches.py
View file

@ -34,6 +34,7 @@ class L1Cache(BaseCache):
latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
is_top_level = True
class L2Cache(BaseCache):
assoc = 8
@ -49,6 +50,7 @@ class PageTableWalkerCache(BaseCache):
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
is_top_level = True
class IOCache(BaseCache):
assoc = 8
@ -58,3 +60,4 @@ class IOCache(BaseCache):
size = '1kB'
tgts_per_mshr = 12
forward_snoops = False
is_top_level = True

11
configs/common/FSConfig.py
View file

@ -201,13 +201,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
self.membus = MemBus(bus_id=1)
self.membus.badaddr_responder.warn_access = "warn"
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'),
file = disk('ael-arm.ext2'))
self.bridge.side_a = self.iobus.port
self.bridge.side_b = self.membus.port
self.physmem.port = self.membus.port
self.diskmem.port = self.membus.port
self.mem_mode = mem_mode
@ -232,13 +227,19 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
if bare_metal:
# EOT character on UART will end the simulation
self.realview.uart.end_on_eot = True
self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')), zero = True)
else:
self.physmem = PhysicalMemory(range = AddrRange(Addr('128MB')), zero = True)
self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'),
file = disk('ael-arm.ext2'))
self.diskmem.port = self.membus.port
self.machine_type = machine_type
self.kernel = binary('vmlinux.arm')
self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0' + \
' lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000' + \
' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0'
self.physmem.port = self.membus.port
self.realview.attachOnChipIO(self.membus)
self.realview.attachIO(self.iobus)

6
src/arch/alpha/predecoder.hh
View file

@ -76,6 +76,12 @@ class Predecoder
emiIsReady = false;
}
void
reset(const ExtMachInst &old_emi)
{
reset();
}
// Use this to give data to the predecoder. This should be used
// when there is control flow.
void

1
src/arch/arm/insts/branch.hh
View file

@ -57,6 +57,7 @@ class BranchImm : public PredOp
int32_t _imm) :
PredOp(mnem, _machInst, __opClass), imm(_imm)
{}
};
// Conditionally Branch to a target computed with an immediate

74
src/arch/arm/insts/macromem.cc
View file

@ -58,8 +58,13 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
{
uint32_t regs = reglist;
uint32_t ones = number_of_ones(reglist);
// Remember that writeback adds a uop
numMicroops = ones + (writeback ? 1 : 0) + 1;
// Remember that writeback adds a uop or two and the temp register adds one
numMicroops = ones + (writeback ? (load ? 2 : 1) : 0) + 1;
// It's technically legal to do a lot of nothing
if (!ones)
numMicroops = 1;
microOps = new StaticInstPtr[numMicroops];
uint32_t addr = 0;
@ -70,28 +75,13 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
addr += 4;
StaticInstPtr *uop = microOps;
StaticInstPtr wbUop;
if (writeback) {
if (up) {
wbUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
} else {
wbUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
}
}
// Add 0 to Rn and stick it in ureg0.
// This is equivalent to a move.
*uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
// Write back at the start for loads. This covers the ldm exception return
// case where the base needs to be written in the old mode. Stores may need
// the original value of the base, but they don't change mode and can
// write back at the end like before.
if (load && writeback) {
*++uop = wbUop;
}
unsigned reg = 0;
unsigned regIdx = 0;
bool force_user = user & !bits(reglist, 15);
bool exception_ret = user & bits(reglist, 15);
@ -101,12 +91,20 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
reg++;
replaceBits(regs, reg, 0);
unsigned regIdx = reg;
regIdx = reg;
if (force_user) {
regIdx = intRegInMode(MODE_USER, regIdx);
}
if (load) {
if (writeback && i == ones - 1) {
// If it's a writeback and this is the last register
// do the load into a temporary register which we'll move
// into the final one later
*++uop = new MicroLdrUop(machInst, INTREG_UREG1, INTREG_UREG0,
up, addr);
} else {
// Otherwise just do it normally
if (reg == INTREG_PC && exception_ret) {
// This must be the exception return form of ldm.
*++uop = new MicroLdrRetUop(machInst, regIdx,
@ -115,6 +113,7 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
*++uop = new MicroLdrUop(machInst, regIdx,
INTREG_UREG0, up, addr);
}
}
} else {
*++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
}
@ -125,8 +124,32 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
addr -= 4;
}
if (!load && writeback) {
*++uop = wbUop;
if (writeback && ones) {
// put the register update after we're done all loading
if (up)
*++uop = new MicroAddiUop(machInst, rn, rn, ones * 4);
else
*++uop = new MicroSubiUop(machInst, rn, rn, ones * 4);
// If this was a load move the last temporary value into place
// this way we can't take an exception after we update the base
// register.
if (load && reg == INTREG_PC && exception_ret) {
*++uop = new MicroUopRegMovRet(machInst, 0, INTREG_UREG1);
warn("creating instruction with exception return at curTick:%d\n",
curTick());
} else if (load) {
*++uop = new MicroUopRegMov(machInst, regIdx, INTREG_UREG1);
if (reg == INTREG_PC) {
(*uop)->setFlag(StaticInstBase::IsControl);
(*uop)->setFlag(StaticInstBase::IsCondControl);
(*uop)->setFlag(StaticInstBase::IsIndirectControl);
// This is created as a RAS POP
if (rn == INTREG_SP)
(*uop)->setFlag(StaticInstBase::IsReturn);
}
}
}
(*uop)->setLastMicroop();
@ -895,6 +918,15 @@ MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
return ss.str();
}
std::string
MicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
ss << "[PC,CPSR]";
return ss.str();
}
std::string
MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{

21
src/arch/arm/insts/macromem.hh
View file

@ -134,6 +134,27 @@ class MicroNeonMixLaneOp : public MicroNeonMixOp
{
}
};
/**
* Microops of the form
* PC = IntRegA
* CPSR = IntRegB
*/
class MicroSetPCCPSR : public MicroOp
{
protected:
IntRegIndex ura, urb, urc;
MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
: MicroOp(mnem, machInst, __opClass),
ura(_ura), urb(_urb), urc(_urc)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
* Microops of the form IntRegA = IntRegB
*/

8
src/arch/arm/insts/mem.hh
View file

@ -97,14 +97,18 @@ class RfeOp : public MightBeMicro
IntRegIndex base;
AddrMode mode;
bool wb;
static const unsigned numMicroops = 2;
IntRegIndex ura, urb, urc;
static const unsigned numMicroops = 3;
StaticInstPtr *uops;
RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _base, AddrMode _mode, bool _wb)
: MightBeMicro(mnem, _machInst, __opClass),
base(_base), mode(_mode), wb(_wb), uops(NULL)
base(_base), mode(_mode), wb(_wb),
ura(INTREG_UREG0), urb(INTREG_UREG1),
urc(INTREG_UREG2),
uops(NULL)
{}
virtual

2
src/arch/arm/intregs.hh
View file

@ -110,6 +110,8 @@ enum IntRegIndex
INTREG_ZERO, // Dummy zero reg since there has to be one.
INTREG_UREG0,
INTREG_UREG1,
INTREG_UREG2,
INTREG_CONDCODES,
INTREG_FPCONDCODES,

10
src/arch/arm/isa.cc
View file

@ -143,6 +143,16 @@ ISA::clear()
miscRegs[MISCREG_CPACR] = 0;
miscRegs[MISCREG_FPSID] = 0x410430A0;
// See section B4.1.84 of ARM ARM
// All values are latest for ARMv7-A profile
miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
//XXX We need to initialize the rest of the state.
}

2
src/arch/arm/isa/formats/fp.isa
View file

@ -143,7 +143,7 @@ let {{
bits(machInst, 22) << 4);
const uint32_t type = bits(machInst, 11, 8);
uint32_t size = 0;
uint32_t align = 0;
uint32_t align = TLB::MustBeOne;
unsigned inc = 1;
unsigned regs = 1;
unsigned lane = 0;

35
src/arch/arm/isa/insts/branch.isa
View file

@ -48,6 +48,8 @@ let {{
bCode = '''
NPC = (uint32_t)(PC + imm);
'''
br_tgt_code = '''pcs.instNPC(branchPC.instPC() + imm);'''
instFlags = ["IsDirectControl"]
if (link):
bCode += '''
if (Thumb)
@ -55,12 +57,15 @@ let {{
else
LR = PC - 4;
'''
instFlags += ["IsCall"]
bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
{"code": bCode,
"predicate_test": predicateTest})
{"code": bCode, "predicate_test": predicateTest,
"brTgtCode" : br_tgt_code}, instFlags)
header_output += BranchImmCondDeclare.subst(bIop)
decoder_output += BranchImmCondConstructor.subst(bIop)
decoder_output += BranchImmCondConstructor.subst(bIop) + \
BranchTarget.subst(bIop)
exec_output += PredOpExecute.subst(bIop)
# BX, BLX
@ -81,15 +86,22 @@ let {{
# Since we're switching ISAs, the target ISA will be the opposite
# of the current ISA. Thumb is whether the target is ARM.
newPC = '(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
br_tgt_code = '''
pcs.instNPC((branchPC.thumb() ? (roundDown(branchPC.instPC(),4) + imm) :
(branchPC.instPC() + imm)));
'''
base = "BranchImmCond"
declare = BranchImmCondDeclare
constructor = BranchImmCondConstructor
instFlags = ["IsDirectControl"]
else:
Name += "Reg"
newPC = 'Op1'
br_tgt_code = ''
base = "BranchRegCond"
declare = BranchRegCondDeclare
constructor = BranchRegCondConstructor
instFlags = ["IsIndirectControl"]
if link and imm:
linkStr = '''
// The immediate version of the blx thumb instruction
@ -100,6 +112,7 @@ let {{
else
LR = PC - 4;
'''
instFlags += ["IsCall"]
elif link:
linkStr = '''
if (Thumb)
@ -107,14 +120,18 @@ let {{
else
LR = PC - 4;
'''
instFlags += ["IsCall"]
else:
linkStr = ""
instFlags += ["IsReturn"]
if imm and link: #blx with imm
branchStr = '''
NextThumb = !Thumb;
NPC = %(newPC)s;
'''
br_tgt_code = '''pcs.nextThumb(!branchPC.thumb());\n''' + \
br_tgt_code
else:
branchStr = "IWNPC = %(newPC)s;"
branchStr = branchStr % { "newPC" : newPC }
@ -123,11 +140,13 @@ let {{
"newPC": newPC,
"branch": branchStr}
blxIop = InstObjParams(mnem, Name, base,
{"code": code,
"predicate_test": predicateTest})
{"code": code, "brTgtCode" : br_tgt_code,
"predicate_test": predicateTest}, instFlags)
header_output += declare.subst(blxIop)
decoder_output += constructor.subst(blxIop)
exec_output += PredOpExecute.subst(blxIop)
if imm:
decoder_output += BranchTarget.subst(blxIop)
#Ignore BXJ for now
@ -136,7 +155,8 @@ let {{
code = 'NPC = (uint32_t)(PC + imm);\n'
predTest = "Op1 %(test)s 0" % {"test": test}
iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
{"code": code, "predicate_test": predTest})
{"code": code, "predicate_test": predTest},
["IsIndirectControl"])
header_output += BranchImmRegDeclare.subst(iop)
decoder_output += BranchImmRegConstructor.subst(iop)
exec_output += PredOpExecute.subst(iop)
@ -164,7 +184,8 @@ let {{
iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
{'ea_code': eaCode,
'memacc_code': accCode,
'predicate_test': predicateTest})
'predicate_test': predicateTest},
["IsIndirectControl"])
header_output += BranchTableDeclare.subst(iop)
decoder_output += BranchRegRegConstructor.subst(iop)
exec_output += LoadExecute.subst(iop) + \

25
src/arch/arm/isa/insts/ldr.isa
View file

@ -67,7 +67,7 @@ let {{
self.memFlags = ["ArmISA::TLB::MustBeOne"]
self.codeBlobs = {"postacc_code" : ""}
def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = []):
def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = [], pcDecl = None):
global header_output, decoder_output, exec_output
@ -76,7 +76,8 @@ let {{
(newHeader,
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
self.memFlags, instFlags, base, wbDecl)
self.memFlags, instFlags, base,
wbDecl, pcDecl)
header_output += newHeader
decoder_output += newDecoder
@ -104,26 +105,18 @@ let {{
wbDiff = 8
accCode = '''
CPSR cpsr = Cpsr;
SCTLR sctlr = Sctlr;
// Use the version of NPC that gets set before NextThumb
pNPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
uint32_t tempSpsr = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
uint32_t newCpsr =
cpsrWriteByInstr(cpsr | CondCodes, tempSpsr,
0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
NextThumb = ((CPSR)newCpsr).t;
NextJazelle = ((CPSR)newCpsr).j;
ForcedItState = ((((CPSR)tempSpsr).it2 << 2) & 0xFC)
| (((CPSR)tempSpsr).it1 & 0x3);
CondCodes = CondCodesMask & newCpsr;
URc = cpsr | CondCodes;
URa = cSwap<uint32_t>(Mem.ud, cpsr.e);
URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
'''
self.codeBlobs["memacc_code"] = accCode
wbDecl = None
pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);"
if self.writeback:
wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff
self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"])
self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"], pcDecl)
class LoadImmInst(LoadInst):
def __init__(self, *args, **kargs):

6
src/arch/arm/isa/insts/m5ops.isa
View file

@ -66,7 +66,7 @@ let {{
["IsNonSpeculative", "IsQuiesce"])
header_output += BasicDeclare.subst(quiesceIop)
decoder_output += BasicConstructor.subst(quiesceIop)
exec_output += PredOpExecute.subst(quiesceIop)
exec_output += QuiescePredOpExecute.subst(quiesceIop)
quiesceNsCode = '''
#if FULL_SYSTEM
@ -80,7 +80,7 @@ let {{
["IsNonSpeculative", "IsQuiesce"])
header_output += BasicDeclare.subst(quiesceNsIop)
decoder_output += BasicConstructor.subst(quiesceNsIop)
exec_output += PredOpExecute.subst(quiesceNsIop)
exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
quiesceCyclesCode = '''
#if FULL_SYSTEM
@ -94,7 +94,7 @@ let {{
["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
header_output += BasicDeclare.subst(quiesceCyclesIop)
decoder_output += BasicConstructor.subst(quiesceCyclesIop)
exec_output += PredOpExecute.subst(quiesceCyclesIop)
exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
quiesceTimeCode = '''
#if FULL_SYSTEM

84
src/arch/arm/isa/insts/macromem.isa
View file

@ -51,7 +51,7 @@ let {{
microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
'MicroMemOp',
{'memacc_code': microLdrUopCode,
'ea_code': 'EA = Rb + (up ? imm : -imm);',
'ea_code': 'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest},
['IsMicroop'])
@ -60,7 +60,7 @@ let {{
'MicroMemOp',
{'memacc_code': microLdrFpUopCode,
'ea_code': vfpEnabledCheckCode +
'EA = Rb + (up ? imm : -imm);',
'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest},
['IsMicroop'])
@ -69,7 +69,7 @@ let {{
'MicroMemOp',
{'memacc_code': microLdrFpUopCode,
'ea_code': vfpEnabledCheckCode + '''
EA = Rb + (up ? imm : -imm) +
EA = URb + (up ? imm : -imm) +
(((CPSR)Cpsr).e ? 4 : 0);
''',
'predicate_test': predicateTest},
@ -80,37 +80,40 @@ let {{
'MicroMemOp',
{'memacc_code': microLdrFpUopCode,
'ea_code': vfpEnabledCheckCode + '''
EA = Rb + (up ? imm : -imm) -
EA = URb + (up ? imm : -imm) -
(((CPSR)Cpsr).e ? 4 : 0);
''',
'predicate_test': predicateTest},
['IsMicroop'])
microLdrRetUopCode = '''
microRetUopCode = '''
CPSR cpsr = Cpsr;
SCTLR sctlr = Sctlr;
uint32_t newCpsr =
cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
CondCodes = CondCodesMask & newCpsr;
IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
| (((CPSR)Spsr).it1 & 0x3);
'''
microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
'MicroMemOp',
{'memacc_code': microLdrRetUopCode,
{'memacc_code':
microRetUopCode % 'Mem.uw',
'ea_code':
'EA = Rb + (up ? imm : -imm);',
'EA = URb + (up ? imm : -imm);',
'predicate_test': condPredicateTest},
['IsMicroop','IsNonSpeculative','IsSerializeAfter'])
['IsMicroop','IsNonSpeculative',
'IsSerializeAfter'])
microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);"
microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
'MicroMemOp',
{'memacc_code': microStrUopCode,
'postacc_code': "",
'ea_code': 'EA = Rb + (up ? imm : -imm);',
'ea_code': 'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest},
['IsMicroop'])
@ -120,7 +123,7 @@ let {{
{'memacc_code': microStrFpUopCode,
'postacc_code': "",
'ea_code': vfpEnabledCheckCode +
'EA = Rb + (up ? imm : -imm);',
'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest},
['IsMicroop'])
@ -130,7 +133,7 @@ let {{
{'memacc_code': microStrFpUopCode,
'postacc_code': "",
'ea_code': vfpEnabledCheckCode + '''
EA = Rb + (up ? imm : -imm) +
EA = URb + (up ? imm : -imm) +
(((CPSR)Cpsr).e ? 4 : 0);
''',
'predicate_test': predicateTest},
@ -142,7 +145,7 @@ let {{
{'memacc_code': microStrFpUopCode,
'postacc_code': "",
'ea_code': vfpEnabledCheckCode + '''
EA = Rb + (up ? imm : -imm) -
EA = URb + (up ? imm : -imm) -
(((CPSR)Cpsr).e ? 4 : 0);
''',
'predicate_test': predicateTest},
@ -170,7 +173,7 @@ let {{
let {{
exec_output = header_output = ''
eaCode = 'EA = Ra + imm;'
eaCode = 'EA = URa + imm;'
for size in (1, 2, 3, 4, 6, 8, 12, 16):
# Set up the memory access.
@ -572,14 +575,14 @@ let {{
let {{
microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
'MicroIntImmOp',
{'code': 'Ra = Rb + imm;',
{'code': 'URa = URb + imm;',
'predicate_test': predicateTest},
['IsMicroop'])
microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
'MicroIntRegOp',
{'code':
'''Ra = Rb + shift_rm_imm(Rc, shiftAmt,
'''URa = URb + shift_rm_imm(URc, shiftAmt,
shiftType,
CondCodes<29:>);
''',
@ -588,14 +591,14 @@ let {{
microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
'MicroIntImmOp',
{'code': 'Ra = Rb - imm;',
{'code': 'URa = URb - imm;',
'predicate_test': predicateTest},
['IsMicroop'])
microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
'MicroIntRegOp',
{'code':
'''Ra = Rb - shift_rm_imm(Rc, shiftAmt,
'''URa = URb - shift_rm_imm(URc, shiftAmt,
shiftType,
CondCodes<29:>);
''',
@ -604,7 +607,35 @@ let {{
microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
'MicroIntMov',
{'code': 'IWRa = Rb;',
{'code': 'IWRa = URb;',
'predicate_test': predicateTest},
['IsMicroop'])
microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet',
'MicroIntMov',
{'code': microRetUopCode % 'URb',
'predicate_test': predicateTest},
['IsMicroop', 'IsNonSpeculative',
'IsSerializeAfter'])
setPCCPSRDecl = '''
CPSR cpsrOrCondCodes = URc;
SCTLR sctlr = Sctlr;
pNPC = URa;
uint32_t newCpsr =
cpsrWriteByInstr(cpsrOrCondCodes, URb,
0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
NextThumb = ((CPSR)newCpsr).t;
NextJazelle = ((CPSR)newCpsr).j;
ForcedItState = ((((CPSR)URb).it2 << 2) & 0xFC)
| (((CPSR)URb).it1 & 0x3);
CondCodes = CondCodesMask & newCpsr;
'''
microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
'MicroSetPCCPSR',
{'code': setPCCPSRDecl,
'predicate_test': predicateTest},
['IsMicroop'])
@ -612,19 +643,26 @@ let {{
MicroIntImmDeclare.subst(microSubiUopIop) + \
MicroIntRegDeclare.subst(microAddUopIop) + \
MicroIntRegDeclare.subst(microSubUopIop) + \
MicroIntMovDeclare.subst(microUopRegMovIop)
MicroIntMovDeclare.subst(microUopRegMovIop) + \
MicroIntMovDeclare.subst(microUopRegMovRetIop) + \
MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop)
decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
MicroIntImmConstructor.subst(microSubiUopIop) + \
MicroIntRegConstructor.subst(microAddUopIop) + \
MicroIntRegConstructor.subst(microSubUopIop) + \
MicroIntMovConstructor.subst(microUopRegMovIop)
MicroIntMovConstructor.subst(microUopRegMovIop) + \
MicroIntMovConstructor.subst(microUopRegMovRetIop) + \
MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop)
exec_output = PredOpExecute.subst(microAddiUopIop) + \
PredOpExecute.subst(microSubiUopIop) + \
PredOpExecute.subst(microAddUopIop) + \
PredOpExecute.subst(microSubUopIop) + \
PredOpExecute.subst(microUopRegMovIop)
PredOpExecute.subst(microUopRegMovIop) + \
PredOpExecute.subst(microUopRegMovRetIop) + \
PredOpExecute.subst(microUopSetPCCPSRIop)
}};
let {{

25
src/arch/arm/isa/insts/mem.isa
View file

@ -48,7 +48,7 @@ let {{
self.constructTemplate = eval(self.decConstBase + 'Constructor')
def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags,
base = 'Memory', wbDecl = None):
base = 'Memory', wbDecl = None, pcDecl = None):
# Make sure flags are in lists (convert to lists if not).
memFlags = makeList(memFlags)
instFlags = makeList(instFlags)
@ -65,12 +65,26 @@ let {{
macroName = Name
instFlagsCopy = list(instFlags)
codeBlobsCopy = dict(codeBlobs)
if wbDecl is not None:
use_uops = 0
if wbDecl is not None or pcDecl is not None:
instFlagsCopy.append('IsMicroop')
Name = Name + 'Acc'
use_uops = 1
use_wb = 0
use_pc = 0
if wbDecl is not None:
use_wb = 1
if pcDecl is not None:
use_pc = 1
codeBlobsCopy['acc_name'] = Name
codeBlobsCopy['wb_decl'] = wbDecl
codeBlobsCopy['pc_decl'] = pcDecl
codeBlobsCopy['use_uops'] = 0
codeBlobsCopy['use_wb'] = 0
codeBlobsCopy['use_pc'] = 0
iop = InstObjParams(name, Name, base,
codeBlobsCopy, instFlagsCopy)
@ -81,11 +95,14 @@ let {{
self.initiateAccTemplate.subst(iop) + \
self.completeAccTemplate.subst(iop)
if wbDecl is not None:
if wbDecl is not None or pcDecl is not None:
iop = InstObjParams(name, macroName, base,
{ "wb_decl" : wbDecl,
"pc_decl" : pcDecl,
"acc_name" : Name,
"use_uops" : 1 },
"use_uops" : use_uops,
"use_pc" : use_pc,
"use_wb" : use_wb },
['IsMacroop'])
header_output += self.declareTemplate.subst(iop)
decoder_output += self.constructTemplate.subst(iop)

18
src/arch/arm/isa/insts/misc.isa
View file

@ -491,10 +491,13 @@ let {{
wfeCode = '''
#if FULL_SYSTEM
if (SevMailbox)
if (SevMailbox) {
SevMailbox = 0;
else
PseudoInst::quiesceSkip(xc->tcBase());
}
else {
PseudoInst::quiesce(xc->tcBase());
}
#endif
'''
wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
@ -502,7 +505,7 @@ let {{
["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
header_output += BasicDeclare.subst(wfeIop)
decoder_output += BasicConstructor.subst(wfeIop)
exec_output += PredOpExecute.subst(wfeIop)
exec_output += QuiescePredOpExecute.subst(wfeIop)
wfiCode = '''
#if FULL_SYSTEM
@ -511,22 +514,25 @@ let {{
'''
wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
{ "code" : wfiCode, "predicate_test" : predicateTest },
["IsNonSpeculative", "IsQuiesce"])
["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
header_output += BasicDeclare.subst(wfiIop)
decoder_output += BasicConstructor.subst(wfiIop)
exec_output += PredOpExecute.subst(wfiIop)
exec_output += QuiescePredOpExecute.subst(wfiIop)
sevCode = '''
// Need a way for O3 to not scoreboard these accesses as pipe flushes.
SevMailbox = 1;
System *sys = xc->tcBase()->getSystemPtr();
for (int x = 0; x < sys->numContexts(); x++) {
ThreadContext *oc = sys->getThreadContext(x);
if (oc != xc->tcBase()) {
oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
}
}
'''
sevIop = InstObjParams("sev", "SevInst", "PredOp", \
{ "code" : sevCode, "predicate_test" : predicateTest },
["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
["IsNonSpeculative", "IsSquashAfter"])
header_output += BasicDeclare.subst(sevIop)
decoder_output += BasicConstructor.subst(sevIop)
exec_output += PredOpExecute.subst(sevIop)

14
src/arch/arm/isa/insts/str.isa
View file

@ -222,7 +222,6 @@ let {{
decConstBase = 'StoreExImm'
basePrefix = 'MemoryExImm'
nameFunc = staticmethod(storeImmClassName)
instFlags = ['IsStoreConditional']
def __init__(self, *args, **kargs):
super(StoreImmEx, self).__init__(*args, **kargs)
@ -302,7 +301,6 @@ let {{
decConstBase = 'StoreExDImm'
basePrefix = 'MemoryExDImm'
nameFunc = staticmethod(storeDoubleImmClassName)
instFlags = ['IsStoreConditional']
def __init__(self, *args, **kargs):
super(StoreDoubleImmEx, self).__init__(*args, **kargs)
@ -370,10 +368,14 @@ let {{
buildDoubleStores("strd")
StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit()
StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit()
StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit()
StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit()
StoreImmEx("strex", False, True, False, size=4, flavor="exclusive",
instFlags = ['IsStoreConditional']).emit()
StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive",
instFlags = ['IsStoreConditional']).emit()
StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive",
instFlags = ['IsStoreConditional']).emit()
StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive",
instFlags = ['IsStoreConditional']).emit()
StoreImm("vstr", False, True, False, size=4, flavor="fp").emit()
StoreImm("vstr", False, False, False, size=4, flavor="fp").emit()

6
src/arch/arm/isa/operands.isa
View file

@ -228,11 +228,11 @@ def operands {{
'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
#Register fields for microops
'Ra' : intReg('ura'),
'URa' : intReg('ura'),
'IWRa' : intRegIWPC('ura'),
'Fa' : floatReg('ura'),
'Rb' : intReg('urb'),
'Rc' : intReg('urc'),
'URb' : intReg('urb'),
'URc' : intReg('urc'),
#Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),

37
src/arch/arm/isa/templates/branch.isa
View file

@ -57,7 +57,11 @@ def template BranchImmConstructor {{
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
flags[IsCondControl] = true;
} else {
flags[IsUncondControl] = true;
}
}
}};
@ -69,6 +73,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, int32_t _imm,
ConditionCode _condCode);
%(BasicExecDeclare)s
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
};
}};
@ -84,6 +89,9 @@ def template BranchImmCondConstructor {{
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
flags[IsCondControl] = true;
} else {
flags[IsUncondControl] = true;
}
}
}};
@ -108,6 +116,9 @@ def template BranchRegConstructor {{
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
flags[IsCondControl] = true;
} else {
flags[IsUncondControl] = true;
}
}
}};
@ -135,6 +146,9 @@ def template BranchRegCondConstructor {{
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
flags[IsCondControl] = true;
} else {
flags[IsUncondControl] = true;
}
}
}};
@ -176,6 +190,9 @@ def template BranchRegRegConstructor {{
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
flags[IsCondControl] = true;
} else {
flags[IsUncondControl] = true;
}
}
}};
@ -202,6 +219,26 @@ def template BranchImmRegConstructor {{
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
flags[IsCondControl] = true;
} else {
flags[IsUncondControl] = true;
}
}
}};
def template BranchTarget {{
ArmISA::PCState
%(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const
{
%(op_decl)s;
%(op_rd)s;
ArmISA::PCState pcs = branchPC;
%(brTgtCode)s
pcs.advance();
return pcs;
}
}};

35
src/arch/arm/isa/templates/macromem.isa
View file

@ -107,6 +107,41 @@ def template MicroNeonMemDeclare {{
};
}};
////////////////////////////////////////////////////////////////////
//
// PC = Integer(ura)
// CPSR = Integer(urb)
//
def template MicroSetPCCPSRDeclare {{
class %(class_name)s : public %(base_class)s
{
public:
%(class_name)s(ExtMachInst machInst,
IntRegIndex _ura,
IntRegIndex _urb,
IntRegIndex _urc);
%(BasicExecDeclare)s
};
}};
def template MicroSetPCCPSRConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _ura,
IntRegIndex _urb,
IntRegIndex _urc)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb, _urc)
{
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
}
}
}
}};
////////////////////////////////////////////////////////////////////
//
// Integer = Integer op Integer microops

18
src/arch/arm/isa/templates/mem.isa
View file

@ -928,12 +928,18 @@ def template RfeConstructor {{
}
}
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d];
int uopIdx = 0;
uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb);
uops[uopIdx]->setDelayedCommit();
#if %(use_wb)d
uops[++uopIdx] = new %(wb_decl)s;
uops[uopIdx]->setDelayedCommit();
#endif
#if %(use_pc)d
uops[++uopIdx] = new %(pc_decl)s;
#endif
uops[uopIdx]->setLastMicroop();
#endif
}
}};

32
src/arch/arm/isa/templates/pred.isa
View file

@ -170,6 +170,38 @@ def template PredOpExecute {{
}
}};
def template QuiescePredOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;
resTemp = resTemp;
%(op_decl)s;
%(op_rd)s;
if (%(predicate_test)s)
{
%(code)s;
if (fault == NoFault)
{
%(op_wb)s;
}
} else {
xc->setPredicate(false);
#if FULL_SYSTEM
PseudoInst::quiesceSkip(xc->tcBase());
#endif
}
if (fault == NoFault && machInst.itstateMask != 0&&
(!isMicroop() || isLastMicroop())) {
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
}
return fault;
}
}};
def template DataDecode {{
if (machInst.opcode4 == 0) {
if (machInst.sField == 0)

34
src/arch/arm/linux/process.cc
View file

@ -197,7 +197,7 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = {
/* 117 */ SyscallDesc("ipc", unimplementedFunc),
/* 118 */ SyscallDesc("fsync", unimplementedFunc),
/* 119 */ SyscallDesc("sigreturn", unimplementedFunc),
/* 120 */ SyscallDesc("clone", unimplementedFunc),
/* 120 */ SyscallDesc("clone", cloneFunc),
/* 121 */ SyscallDesc("setdomainname", unimplementedFunc),
/* 122 */ SyscallDesc("uname", unameFunc),
/* 123 */ SyscallDesc("unused#123", unimplementedFunc),
@ -239,7 +239,7 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = {
/* 159 */ SyscallDesc("sched_get_priority_max", unimplementedFunc),
/* 160 */ SyscallDesc("sched_get_priority_min", unimplementedFunc),
/* 161 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc),
/* 162 */ SyscallDesc("nanosleep", unimplementedFunc),
/* 162 */ SyscallDesc("nanosleep", ignoreWarnOnceFunc),
/* 163 */ SyscallDesc("mremap", mremapFunc<ArmLinux>), // ARM-specific
/* 164 */ SyscallDesc("setresuid", unimplementedFunc),
/* 165 */ SyscallDesc("getresuid", unimplementedFunc),
@ -251,8 +251,8 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = {
/* 171 */ SyscallDesc("getresgid", unimplementedFunc),
/* 172 */ SyscallDesc("prctl", unimplementedFunc),
/* 173 */ SyscallDesc("rt_sigreturn", unimplementedFunc),
/* 174 */ SyscallDesc("rt_sigaction", ignoreFunc),
/* 175 */ SyscallDesc("rt_sigprocmask", unimplementedFunc),
/* 174 */ SyscallDesc("rt_sigaction", ignoreWarnOnceFunc),
/* 175 */ SyscallDesc("rt_sigprocmask", ignoreWarnOnceFunc),
/* 176 */ SyscallDesc("rt_sigpending", unimplementedFunc),
/* 177 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc),
/* 178 */ SyscallDesc("rt_sigqueueinfo", ignoreFunc),
@ -317,7 +317,7 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = {
/* 237 */ SyscallDesc("fremovexattr", unimplementedFunc),
/* 238 */ SyscallDesc("tkill", unimplementedFunc),
/* 239 */ SyscallDesc("sendfile64", unimplementedFunc),
/* 240 */ SyscallDesc("futex", unimplementedFunc),
/* 240 */ SyscallDesc("futex", ignoreWarnOnceFunc),
/* 241 */ SyscallDesc("sched_setaffinity", unimplementedFunc),
/* 242 */ SyscallDesc("sched_getaffinity", unimplementedFunc),
/* 243 */ SyscallDesc("io_setup", unimplementedFunc),
@ -456,6 +456,7 @@ setTLSFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
tc->getMemPort()->writeBlob(ArmLinuxProcess::commPage + 0x0ff0,
(uint8_t *)&tlsPtr, sizeof(tlsPtr));
tc->setMiscReg(MISCREG_TPIDRURO,tlsPtr);
return 0;
}
@ -508,7 +509,7 @@ ArmLinuxProcess::startup()
ThreadContext *tc = system->getThreadContext(contextIds[0]);
uint8_t swiNeg1[] = {
0xff, 0xff, 0xff, 0xef //swi -1
0xff, 0xff, 0xff, 0xef // swi -1
};
// Fill this page with swi -1 so we'll no if we land in it somewhere.
@ -521,7 +522,8 @@ ArmLinuxProcess::startup()
// @todo Add a barrrier in this code
uint8_t memory_barrier[] =
{
0x0e, 0xf0, 0xa0, 0xe1 //usr_ret lr
0x5f, 0xf0, 0x7f, 0xf5, // dmb
0x0e, 0xf0, 0xa0, 0xe1 // return
};
tc->getMemPort()->writeBlob(commPage + 0x0fa0, memory_barrier,
sizeof(memory_barrier));
@ -531,18 +533,22 @@ ArmLinuxProcess::startup()
// @todo replace this with ldrex/strex and dmb
uint8_t cmpxchg[] =
{
0x00, 0x30, 0x92, 0xe5, //ldr r3, [r2]
0x00, 0x30, 0x53, 0xe0, //subs r3, r3, r0
0x00, 0x10, 0x82, 0x05, //streq r1, [r2]
0x03, 0x00, 0xa0, 0xe1, //mov r0, r3
0x0e, 0xf0, 0xa0, 0xe1 //usr_ret lr
0x9f, 0x3f, 0x92, 0xe1, // ldrex r3, [r2]
0x00, 0x30, 0x53, 0xe0, // subs r3, r3, r0
0x91, 0x3f, 0x82, 0x01, // strexeq r3, r1, [r2]
0x01, 0x00, 0x33, 0x03, // teqeq r3, #1
0xfa, 0xff, 0xff, 0x0a, // beq 1b
0x00, 0x00, 0x73, 0xe2, // rsbs r0, r3, #0
0x5f, 0xf0, 0x7f, 0xf5, // dmb
0x0e, 0xf0, 0xa0, 0xe1 // return
};
tc->getMemPort()->writeBlob(commPage + 0x0fc0, cmpxchg, sizeof(cmpxchg));
uint8_t get_tls[] =
{
0x08, 0x00, 0x9f, 0xe5, //ldr r0, [pc, #(16 - 8)]
0x0e, 0xf0, 0xa0, 0xe1 //usr_ret lr
// read user read-only thread id register
0x70, 0x0f, 0x1d, 0xee, // mrc p15, 0, r0, c13, c0, 3
0x0e, 0xf0, 0xa0, 0xe1 // return
};
tc->getMemPort()->writeBlob(commPage + 0x0fe0, get_tls, sizeof(get_tls));
}

24
src/arch/arm/linux/system.cc
View file

@ -47,9 +47,11 @@
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
#include "kern/linux/events.hh"
#include "mem/physical.hh"
using namespace ArmISA;
using namespace Linux;
LinuxArmSystem::LinuxArmSystem(Params *p)
: ArmSystem(p)
@ -96,6 +98,24 @@ LinuxArmSystem::LinuxArmSystem(Params *p)
if (!kernelPanicEvent)
panic("could not find kernel symbol \'panic\'");
#endif
// With ARM udelay() is #defined to __udelay
Addr addr = 0;
if (kernelSymtab->findAddress("__udelay", addr)) {
uDelaySkipEvent = new UDelayEvent(&pcEventQueue, "__udelay",
fixFuncEventAddr(addr), 1000, 0);
} else {
panic("couldn't find kernel symbol \'udelay\'");
}
// constant arguments to udelay() have some precomputation done ahead of
// time. Constant comes from code.
if (kernelSymtab->findAddress("__const_udelay", addr)) {
constUDelaySkipEvent = new UDelayEvent(&pcEventQueue, "__const_udelay",
fixFuncEventAddr(addr), 1000, 107374);
} else {
panic("couldn't find kernel symbol \'udelay\'");
}
}
void
@ -115,6 +135,10 @@ LinuxArmSystem::initState()
LinuxArmSystem::~LinuxArmSystem()
{
if (uDelaySkipEvent)
delete uDelaySkipEvent;
if (constUDelaySkipEvent)
delete constUDelaySkipEvent;
}
LinuxArmSystem *

13
src/arch/arm/linux/system.hh
View file

@ -74,6 +74,19 @@ class LinuxArmSystem : public ArmSystem
/** Event to halt the simulator if the kernel calls panic() */
BreakPCEvent *kernelPanicEvent;
#endif
/**
* PC based event to skip udelay(<time>) calls and quiesce the
* processor for the appropriate amount of time. This is not functionally
* required but does speed up simulation.
*/
Linux::UDelayEvent *uDelaySkipEvent;
/** Another PC based skip event for const_udelay(). Similar to the udelay
* skip, but this function precomputes the first multiply that is done
* in the generic case since the parameter is known at compile time.
* Thus we need to do some division to get back to us.
*/
Linux::UDelayEvent *constUDelaySkipEvent;
};
#endif // __ARCH_ARM_LINUX_SYSTEM_HH__

17
src/arch/arm/miscregs.hh
View file

@ -165,6 +165,12 @@ namespace ArmISA
MISCREG_PMUSERENR,
MISCREG_PMINTENSET,
MISCREG_PMINTENCLR,
MISCREG_ID_ISAR0,
MISCREG_ID_ISAR1,
MISCREG_ID_ISAR2,
MISCREG_ID_ISAR3,
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
MISCREG_ID_PFR1,
@ -173,12 +179,6 @@ namespace ArmISA
MISCREG_ID_MMFR1,
MISCREG_ID_MMFR2,
MISCREG_ID_MMFR3,
MISCREG_ID_ISAR0,
MISCREG_ID_ISAR1,
MISCREG_ID_ISAR2,
MISCREG_ID_ISAR3,
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
MISCREG_AIDR,
MISCREG_ADFSR,
MISCREG_AIFSR,
@ -233,13 +233,12 @@ namespace ArmISA
"pmswinc", "pmselr", "pmceid0",
"pmceid1", "pmc_other", "pmxevcntr",
"pmuserenr", "pmintenset", "pmintenclr",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
// Unimplemented below
"tcmtr",
"id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
"aidr",
"adfsr", "aifsr",
"aidr", "adfsr", "aifsr",
"dcimvac", "dcisw", "mccsw",
"dccmvau",
"nsacr",

13
src/arch/arm/predecoder.hh
View file

@ -83,6 +83,12 @@ namespace ArmISA
predAddrValid = false;
}
void reset(const ExtMachInst &old_emi)
{
reset();
itstate = old_emi.newItstate;
}
Predecoder(ThreadContext * _tc) :
tc(_tc), data(0)
{
@ -122,17 +128,17 @@ namespace ArmISA
outOfBytes = true;
}
bool needMoreBytes()
bool needMoreBytes() const
{
return outOfBytes;
}
bool extMachInstReady()
bool extMachInstReady() const
{
return emiReady;
}
int getInstSize()
int getInstSize() const
{
return (!emi.thumb || emi.bigThumb) ? 4 : 2;
}
@ -145,6 +151,7 @@ namespace ArmISA
pc.npc(pc.pc() + getInstSize());
predAddrValid = true;
predAddr = pc.pc() + getInstSize();
pc.size(getInstSize());
emi = 0;
emiReady = false;
return thisEmi;

13
src/arch/arm/types.hh
View file

@ -203,6 +203,7 @@ namespace ArmISA
uint8_t flags;
uint8_t nextFlags;
uint8_t forcedItStateValue;
uint8_t _size;
bool forcedItStateValid;
public:
PCState() : flags(0), nextFlags(0), forcedItStateValue(0), forcedItStateValid(false)
@ -248,6 +249,16 @@ namespace ArmISA
nextFlags &= ~ThumbBit;
}
void size(uint8_t s) { _size = s; }
uint8_t size() const { return _size; }
bool
branching() const
{
return ((this->pc() + this->size()) != this->npc());
}
bool
jazelle() const
{
@ -392,6 +403,7 @@ namespace ArmISA
{
Base::serialize(os);
SERIALIZE_SCALAR(flags);
SERIALIZE_SCALAR(_size);
SERIALIZE_SCALAR(nextFlags);
SERIALIZE_SCALAR(forcedItStateValue);
SERIALIZE_SCALAR(forcedItStateValid);
@ -402,6 +414,7 @@ namespace ArmISA
{
Base::unserialize(cp, section);
UNSERIALIZE_SCALAR(flags);
UNSERIALIZE_SCALAR(_size);
UNSERIALIZE_SCALAR(nextFlags);
UNSERIALIZE_SCALAR(forcedItStateValue);
UNSERIALIZE_SCALAR(forcedItStateValid);

6
src/arch/mips/predecoder.hh
View file

@ -75,6 +75,12 @@ class Predecoder
emiIsReady = false;
}
void
reset(const ExtMachInst &old_emi)
{
reset();
}
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void

6
src/arch/power/predecoder.hh
View file

@ -82,6 +82,12 @@ class Predecoder
emiIsReady = false;
}
void
reset(const ExtMachInst &old_emi)
{
reset();
}
// Use this to give data to the predecoder. This should be used
// when there is control flow.
void

7
src/arch/sparc/predecoder.hh
View file

@ -68,12 +68,19 @@ class Predecoder
}
void process() {}
void
reset()
{
emiIsReady = false;
}
void
reset(const ExtMachInst &old_emi)
{
reset();
}
// Use this to give data to the predecoder. This should be used
// when there is control flow.
void

6
src/arch/x86/predecoder.hh
View file

@ -174,6 +174,12 @@ namespace X86ISA
state = ResetState;
}
void
reset(const ExtMachInst &old_emi)
{
reset();
}
ThreadContext * getTC()
{
return tc;

57
src/cpu/o3/comm.hh
View file

@ -1,4 +1,16 @@
/*
* Copyright (c) 2011 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
@ -123,7 +135,6 @@ struct TimeBufStruct {
bool branchTaken;
Addr mispredPC;
TheISA::PCState nextPC;
unsigned branchCount;
};
@ -151,29 +162,45 @@ struct TimeBufStruct {
iewComm iewInfo[Impl::MaxThreads];
struct commitComm {
bool usedROB;
unsigned freeROBEntries;
bool emptyROB;
/////////////// For Decode, IEW, Rename, Fetch ///////////
bool squash;
bool robSquashing;
bool branchMispredict;
DynInstPtr mispredictInst;
bool branchTaken;
Addr mispredPC;
TheISA::PCState pc;
////////// For Fetch & IEW /////////////
// Represents the instruction that has either been retired or
// squashed. Similar to having a single bus that broadcasts the
// retired or squashed sequence number.
InstSeqNum doneSeqNum;
//Just in case we want to do a commit/squash on a cycle
//(necessary for multiple ROBs?)
bool commitInsts;
InstSeqNum squashSeqNum;
////////////// For Rename /////////////////
// Rename should re-read number of free rob entries
bool usedROB;
// Notify Rename that the ROB is empty
bool emptyROB;
// Tell Rename how many free entries it has in the ROB
unsigned freeROBEntries;
///////////// For Fetch //////////////////
// Provide fetch the instruction that mispredicted, if this
// pointer is not-null a misprediction occured
DynInstPtr mispredictInst;
// Was the branch taken or not
bool branchTaken;
// The pc of the next instruction to execute. This is the next
// instruction for a branch mispredict, but the same instruction for
// order violation and the like
TheISA::PCState pc;
// Instruction that caused the a non-mispredict squash
DynInstPtr squashInst;
// If an interrupt is pending and fetch should stall
bool interruptPending;
// If the interrupt ended up being cleared before being handled
bool clearInterrupt;
//////////// For IEW //////////////////
// Communication specifically to the IQ to tell the IQ that it can
// schedule a non-speculative instruction.
InstSeqNum nonSpecSeqNum;
@ -182,8 +209,6 @@ struct TimeBufStruct {
bool uncached;
DynInstPtr uncachedLoad;
bool interruptPending;
bool clearInterrupt;
};
commitComm commitInfo[Impl::MaxThreads];

3
src/cpu/o3/commit.hh
View file

@ -262,7 +262,8 @@ class DefaultCommit
* instructions instead of the current instruction and doesn't
* clean up various status bits about traps/tc writes pending.
*/
void squashAfter(ThreadID tid, uint64_t squash_after_seq_num);
void squashAfter(ThreadID tid, DynInstPtr &head_inst,
uint64_t squash_after_seq_num);
#if FULL_SYSTEM
/** Handles processing an interrupt. */

28
src/cpu/o3/commit_impl.hh
View file

@ -541,8 +541,8 @@ DefaultCommit<Impl>::squashAll(ThreadID tid)
// the ROB is in the process of squashing.
toIEW->commitInfo[tid].robSquashing = true;
toIEW->commitInfo[tid].branchMispredict = false;
toIEW->commitInfo[tid].mispredictInst = NULL;
toIEW->commitInfo[tid].squashInst = NULL;
toIEW->commitInfo[tid].pc = pc[tid];
}
@ -584,7 +584,8 @@ DefaultCommit<Impl>::squashFromTC(ThreadID tid)
template <class Impl>
void
DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
uint64_t squash_after_seq_num)
{
youngestSeqNum[tid] = squash_after_seq_num;
@ -594,6 +595,7 @@ DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
// Send back the sequence number of the squashed instruction.
toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
toIEW->commitInfo[tid].squashInst = head_inst;
// Send back the squash signal to tell stages that they should squash.
toIEW->commitInfo[tid].squash = true;
@ -601,7 +603,7 @@ DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
// the ROB is in the process of squashing.
toIEW->commitInfo[tid].robSquashing = true;
toIEW->commitInfo[tid].branchMispredict = false;
toIEW->commitInfo[tid].mispredictInst = NULL;
toIEW->commitInfo[tid].pc = pc[tid];
DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
@ -801,10 +803,17 @@ DefaultCommit<Impl>::commit()
commitStatus[tid] != TrapPending &&
fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
if (fromIEW->mispredictInst[tid]) {
DPRINTF(Commit,
"[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
tid,
fromIEW->mispredPC[tid],
fromIEW->mispredictInst[tid]->instAddr(),
fromIEW->squashedSeqNum[tid]);
} else {
DPRINTF(Commit,
"[tid:%i]: Squashing due to order violation [sn:%i]\n",
tid, fromIEW->squashedSeqNum[tid]);
}
DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
tid,
@ -835,18 +844,15 @@ DefaultCommit<Impl>::commit()
// the ROB is in the process of squashing.
toIEW->commitInfo[tid].robSquashing = true;
toIEW->commitInfo[tid].branchMispredict =
fromIEW->branchMispredict[tid];
toIEW->commitInfo[tid].mispredictInst =
fromIEW->mispredictInst[tid];
toIEW->commitInfo[tid].branchTaken =
fromIEW->branchTaken[tid];
toIEW->commitInfo[tid].squashInst = NULL;
toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
if (toIEW->commitInfo[tid].branchMispredict) {
if (toIEW->commitInfo[tid].mispredictInst) {
++branchMispredicts;
}
}
@ -988,7 +994,7 @@ DefaultCommit<Impl>::commitInsts()
// If this is an instruction that doesn't play nicely with
// others squash everything and restart fetch
if (head_inst->isSquashAfter())
squashAfter(tid, head_inst->seqNum);
squashAfter(tid, head_inst, head_inst->seqNum);
int count = 0;
Addr oldpc;

5
src/cpu/o3/cpu.cc
View file

@ -808,8 +808,9 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
}
// Squash Throughout Pipeline
InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
fetch.squash(0, squash_seq_num, tid);
DynInstPtr inst = commit.rob->readHeadInst(tid);
InstSeqNum squash_seq_num = inst->seqNum;
fetch.squash(0, squash_seq_num, inst, tid);
decode.squash(tid);
rename.squash(squash_seq_num, tid);
iew.squash(tid);

4
src/cpu/o3/fetch.hh
View file

@ -312,8 +312,8 @@ class DefaultFetch
* remove any instructions that are not in the ROB. The source of this
* squash should be the commit stage.
*/
void squash(const TheISA::PCState &newPC,
const InstSeqNum &seq_num, ThreadID tid);
void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
DynInstPtr &squashInst, ThreadID tid);
/** Ticks the fetch stage, processing all inputs signals and fetching
* as many instructions as possible.

15
src/cpu/o3/fetch_impl.hh
View file

@ -112,6 +112,9 @@ DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
{
DPRINTF(Fetch, "Received timing\n");
if (pkt->isResponse()) {
// We shouldn't ever get a block in ownership state
assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
fetch->processCacheCompletion(pkt);
}
//else Snooped a coherence request, just return
@ -812,11 +815,14 @@ DefaultFetch<Impl>::updateFetchStatus()
template <class Impl>
void
DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
const InstSeqNum &seq_num, ThreadID tid)
const InstSeqNum &seq_num, DynInstPtr &squashInst,
ThreadID tid)
{
DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
doSquash(newPC, tid);
if (squashInst)
predecoder.reset(squashInst->staticInst->machInst);
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid);
@ -931,15 +937,12 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
// In any case, squash.
squash(fromCommit->commitInfo[tid].pc,
fromCommit->commitInfo[tid].doneSeqNum,
tid);
fromCommit->commitInfo[tid].squashInst, tid);
// If it was a branch mispredict on a control instruction, update the
// branch predictor with that instruction, otherwise just kill the
// invalid state we generated in after sequence number
assert(!fromCommit->commitInfo[tid].branchMispredict ||
fromCommit->commitInfo[tid].mispredictInst);
if (fromCommit->commitInfo[tid].branchMispredict &&
if (fromCommit->commitInfo[tid].mispredictInst &&
fromCommit->commitInfo[tid].mispredictInst->isControl()) {
branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
fromCommit->commitInfo[tid].pc,

6
src/cpu/o3/iew_impl.hh
View file

@ -456,8 +456,6 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum;
toCommit->mispredPC[tid] = inst->instAddr();
toCommit->branchMispredict[tid] = true;
toCommit->branchTaken[tid] = inst->pcState().branching();
TheISA::PCState pc = inst->pcState();
@ -486,7 +484,7 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
TheISA::PCState pc = inst->pcState();
TheISA::advancePC(pc, inst->staticInst);
toCommit->pc[tid] = pc;
toCommit->branchMispredict[tid] = false;
toCommit->mispredictInst[tid] = NULL;
toCommit->includeSquashInst[tid] = false;
@ -506,7 +504,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
toCommit->squashedSeqNum[tid] = inst->seqNum;
toCommit->pc[tid] = inst->pcState();
toCommit->branchMispredict[tid] = false;
toCommit->mispredictInst[tid] = NULL;
// Must include the broadcasted SN in the squash.
toCommit->includeSquashInst[tid] = true;

4
src/cpu/o3/lsq_unit_impl.hh
View file

@ -1103,7 +1103,9 @@ LSQUnit<Impl>::recvRetry()
dynamic_cast<LSQSenderState *>(retryPkt->senderState);
// Don't finish the store unless this is the last packet.
if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) {
if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
state->pendingPacket == retryPkt) {
state->pktToSend = false;
storePostSend(retryPkt);
}
retryPkt = NULL;

3
src/cpu/simple/atomic.cc
View file

@ -641,6 +641,9 @@ AtomicSimpleCPU::tick()
checkForInterrupts();
checkPcEventQueue();
// We must have just got suspended by a PC event
if (_status == Idle)
return;
Fault fault = NoFault;

4
src/cpu/simple/timing.cc
View file

@ -714,6 +714,10 @@ TimingSimpleCPU::fetch()
checkPcEventQueue();
// We must have just got suspended by a PC event
if (_status == Idle)
return;
TheISA::PCState pcState = thread->pcState();
bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;

1
src/cpu/static_inst.hh
View file

@ -267,6 +267,7 @@ class StaticInstBase : public RefCounted
void setLastMicroop() { flags[IsLastMicroop] = true; }
void setDelayedCommit() { flags[IsDelayedCommit] = true; }
void setFlag(Flags f) { flags[f] = true; }
/// Operation class. Used to select appropriate function unit in issue.
OpClass opClass() const { return _opClass; }

3
src/dev/io_device.cc
View file

@ -139,6 +139,9 @@ DmaPort::recvTiming(PacketPtr pkt)
assert(pendingCount >= 0);
assert(state);
// We shouldn't ever get a block in ownership state
assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
state->numBytes += pkt->req->getSize();
assert(state->totBytes >= state->numBytes);
if (state->totBytes == state->numBytes) {

37
src/kern/linux/events.cc
View file

@ -1,4 +1,16 @@
/*
* Copyright (c) 2011 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
@ -32,11 +44,13 @@
#include <sstream>
#include "base/trace.hh"
#include "arch/utility.hh"
#include "cpu/thread_context.hh"
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"
#include "kern/system_events.hh"
#include "sim/arguments.hh"
#include "sim/pseudo_inst.hh"
#include "sim/system.hh"
namespace Linux {
@ -54,4 +68,27 @@ DebugPrintkEvent::process(ThreadContext *tc)
SkipFuncEvent::process(tc);
}
void
UDelayEvent::process(ThreadContext *tc)
{
int arg_num = 0;
// Get the time in native size
uint64_t time = TheISA::getArgument(tc, arg_num, (uint16_t)-1, false);
// convert parameter to ns
if (argDivToNs)
time /= argDivToNs;
time *= argMultToNs;
// Convert ns to ticks
time *= SimClock::Int::ns;
SkipFuncEvent::process(tc);
PseudoInst::quiesceNs(tc, time);
}
} // namespace linux

27
src/kern/linux/events.hh
View file

@ -44,6 +44,33 @@ class DebugPrintkEvent : public SkipFuncEvent
virtual void process(ThreadContext *xc);
};
/** A class to skip udelay() and related calls in the kernel.
* This class has two additional parameters that take the argument to udelay and
* manipulated it to come up with ns and eventually ticks to quiesce for.
* See descriptions of argDivToNs and argMultToNs below.
*/
class UDelayEvent : public SkipFuncEvent
{
private:
/** value to divide arg by to create ns. This is present beacues the linux
* kernel code sometime precomputes the first multiply that is done in
* udelay() if the parameter is a constant. We need to undo it so here is
* how. */
uint64_t argDivToNs;
/** value to multiple arg by to create ns. Nominally, this is 1000 to
* convert us to ns, but since linux can do some preprocessing of constant
* values something else might be required. */
uint64_t argMultToNs;
public:
UDelayEvent(PCEventQueue *q, const std::string &desc, Addr addr,
uint64_t mult, uint64_t div)
: SkipFuncEvent(q, desc, addr), argDivToNs(div), argMultToNs(mult) {}
virtual void process(ThreadContext *xc);
};
}
#endif

1
src/mem/cache/BaseCache.py vendored
View file

@ -48,6 +48,7 @@ class BaseCache(MemObject):
size = Param.MemorySize("capacity in bytes")
forward_snoops = Param.Bool(True,
"forward snoops from mem side to cpu side")
is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)")
subblock_size = Param.Int(0,
"Size of subblock in IIC used for compression")
tgts_per_mshr = Param.Int("max number of accesses per MSHR")

1
src/mem/cache/base.cc vendored
View file

@ -58,6 +58,7 @@ BaseCache::BaseCache(const Params *p)
hitLatency(p->latency),
numTarget(p->tgts_per_mshr),
forwardSnoops(p->forward_snoops),
isTopLevel(p->is_top_level),
blocked(0),
noTargetMSHR(NULL),
missCount(p->max_miss_count),

5
src/mem/cache/base.hh vendored
View file

@ -194,6 +194,11 @@ class BaseCache : public MemObject
/** Do we forward snoops from mem side port through to cpu side port? */
bool forwardSnoops;
/** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
* never try to forward ownership and similar optimizations to the cpu
* side */
bool isTopLevel;
/**
* Bit vector of the blocking reasons for the access path.
* @sa #BlockedCause

2
src/mem/cache/cache_impl.hh vendored
View file

@ -216,7 +216,7 @@ Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
if (blk->isDirty()) {
// special considerations if we're owner:
if (!deferred_response) {
if (!deferred_response && !isTopLevel) {
// if we are responding immediately and can
// signal that we're transferring ownership
// along with exclusivity, do so

34
src/sim/pseudo_inst.cc
View file

@ -1,4 +1,16 @@
/*
* Copyright (c) 2010 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
@ -85,6 +97,28 @@ quiesce(ThreadContext *tc)
tc->getKernelStats()->quiesce();
}
void
quiesceSkip(ThreadContext *tc)
{
BaseCPU *cpu = tc->getCpuPtr();
if (!cpu->params()->do_quiesce)
return;
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
Tick resume = curTick() + 1;
cpu->reschedule(quiesceEvent, resume, true);
DPRINTF(Quiesce, "%s: quiesceSkip() until %d\n",
cpu->name(), resume);
tc->suspend();
if (tc->getKernelStats())
tc->getKernelStats()->quiesce();
}
void
quiesceNs(ThreadContext *tc, uint64_t ns)
{

1
src/sim/pseudo_inst.hh
View file

@ -45,6 +45,7 @@ extern bool doQuiesce;
#if FULL_SYSTEM
void arm(ThreadContext *tc);
void quiesce(ThreadContext *tc);
void quiesceSkip(ThreadContext *tc);
void quiesceNs(ThreadContext *tc, uint64_t ns);
void quiesceCycles(ThreadContext *tc, uint64_t cycles);
uint64_t quiesceTime(ThreadContext *tc);

14
src/sim/syscall_emul.cc
View file

@ -97,6 +97,18 @@ ignoreFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
}
SyscallReturn
ignoreWarnOnceFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
ThreadContext *tc)
{
int index = 0;
warn_once("ignoring syscall %s(%d, %d, ...)", desc->name,
process->getSyscallArg(tc, index), process->getSyscallArg(tc, index));
return 0;
}
SyscallReturn
exitFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
ThreadContext *tc)
@ -802,6 +814,8 @@ cloneFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
for (int y = 8; y < 32; y++)
ctc->setIntReg(y, tc->readIntReg(y));
#elif THE_ISA == ARM_ISA
TheISA::copyRegs(tc, ctc);
#else
fatal("sys_clone is not implemented for this ISA\n");
#endif

2
src/sim/syscall_emul.hh
View file

@ -187,6 +187,8 @@ SyscallReturn unimplementedFunc(SyscallDesc *desc, int num,
/// trace flag is enabled. Return success to the target program.
SyscallReturn ignoreFunc(SyscallDesc *desc, int num,
LiveProcess *p, ThreadContext *tc);
SyscallReturn ignoreWarnOnceFunc(SyscallDesc *desc, int num,
LiveProcess *p, ThreadContext *tc);
/// Target exit() handler: terminate current context.
SyscallReturn exitFunc(SyscallDesc *desc, int num,

3
tests/SConscript
View file

@ -276,7 +276,8 @@ if env['FULL_SYSTEM']:
't1000-simple-timing']
if env['TARGET_ISA'] == 'arm':
configs += ['realview-simple-atomic',
'realview-simple-timing']
'realview-simple-timing',
'realview-o3']
if env['TARGET_ISA'] == 'x86':
configs += ['pc-simple-atomic',
'pc-simple-timing']

6
tests/configs/inorder-timing.py
View file

@ -37,8 +37,12 @@ class MyCache(BaseCache):
mshrs = 10
tgts_per_mshr = 5
class MyL1Cache(MyCache):
is_top_level = True
cpu = InOrderCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'),
MyCache(size = '2MB', latency='10ns'))
cpu.clock = '2GHz'

1
tests/configs/memtest.py
View file

@ -38,6 +38,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 12
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache

1
tests/configs/o3-timing-mp.py
View file

@ -39,6 +39,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache

6
tests/configs/o3-timing.py
View file

@ -37,8 +37,12 @@ class MyCache(BaseCache):
mshrs = 10
tgts_per_mshr = 5
class MyL1Cache(MyCache):
is_top_level = True
cpu = DerivO3CPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'),
MyCache(size = '2MB'))
cpu.clock = '2GHz'

3
tests/configs/pc-simple-atomic.py
View file

@ -43,6 +43,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache
@ -65,6 +66,7 @@ class PageTableWalkerCache(BaseCache):
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
is_top_level = True
# ---------------------
# I/O Cache
@ -78,6 +80,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range = AddrRange(0, size=mem_size)
forward_snoops = False
is_top_level = True
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)

1
tests/configs/pc-simple-timing.py
View file

@ -44,6 +44,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache

99
tests/configs/realview-o3.py Normal file
View file

@ -0,0 +1,99 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
# --------------------
# Base L1 Cache
# ====================
class L1(BaseCache):
latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache
# ----------------------
class L2(BaseCache):
block_size = 64
latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
# ---------------------
# I/O Cache
# ---------------------
class IOCache(BaseCache):
assoc = 8
block_size = 64
latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
addr_range=AddrRange(0, size='128MB')
forward_snoops = False
#cpu
cpu = DerivO3CPU(cpu_id=0)
#the system
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
system.cpu = cpu
#create the l1/l2 bus
system.toL2Bus = Bus()
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.port
system.l2c.mem_side = system.membus.port
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
root = Root(system=system)
m5.ticks.setGlobalFrequency('1THz')

1
tests/configs/realview-simple-atomic.py
View file

@ -40,6 +40,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache

1
tests/configs/realview-simple-timing.py
View file

@ -41,6 +41,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache

1
tests/configs/simple-atomic-mp.py
View file

@ -38,6 +38,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache

1
tests/configs/simple-timing-mp.py
View file

@ -38,6 +38,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache

6
tests/configs/simple-timing.py
View file

@ -36,8 +36,12 @@ class MyCache(BaseCache):
mshrs = 10
tgts_per_mshr = 5
class MyL1Cache(MyCache):
is_top_level = True
cpu = TimingSimpleCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
MyL1Cache(size = '256kB'),
MyCache(size = '2MB', latency='10ns'))
system = System(cpu = cpu,
physmem = PhysicalMemory(),

2
tests/configs/tsunami-o3-dual.py
View file

@ -41,6 +41,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache
@ -65,6 +66,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
is_top_level = True
#cpu
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]

2
tests/configs/tsunami-o3.py
View file

@ -41,6 +41,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache
@ -65,6 +66,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
is_top_level = True
#cpu
cpu = DerivO3CPU(cpu_id=0)

2
tests/configs/tsunami-simple-atomic-dual.py
View file

@ -40,6 +40,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache
@ -64,6 +65,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
is_top_level = True
#cpu
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]

2
tests/configs/tsunami-simple-atomic.py
View file

@ -40,6 +40,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache
@ -64,6 +65,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
is_top_level = True
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)

2
tests/configs/tsunami-simple-timing-dual.py
View file

@ -40,6 +40,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache
@ -64,6 +65,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
is_top_level = True
#cpu
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]

2
tests/configs/tsunami-simple-timing.py
View file

@ -41,6 +41,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
is_top_level = True
# ----------------------
# Base L2 Cache
@ -65,6 +66,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
is_top_level = True
#cpu
cpu = TimingSimpleCPU(cpu_id=0)

5
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
View file

@ -115,6 +115,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -413,6 +414,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -448,6 +450,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
@ -493,7 +496,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

10
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 21 2011 14:34:16
M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
M5 started Feb 21 2011 14:34:24
M5 compiled Mar 11 2011 20:10:09
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
M5 started Mar 11 2011 20:10:13
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -43,4 +43,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 216988269500 because target called exit()
Exiting @ tick 212151683000 because target called exit()

782
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,130 +1,142 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 84615 # Simulator instruction rate (inst/s)
host_mem_usage 256696 # Number of bytes of host memory used
host_seconds 7097.77 # Real time elapsed on the host
host_tick_rate 30571310 # Simulator tick rate (ticks/s)
host_inst_rate 130169 # Simulator instruction rate (inst/s)
host_mem_usage 255152 # Number of bytes of host memory used
host_seconds 4627.51 # Real time elapsed on the host
host_tick_rate 45845717 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 600581343 # Number of instructions simulated
sim_seconds 0.216988 # Number of seconds simulated
sim_ticks 216988269500 # Number of ticks simulated
sim_insts 602359950 # Number of instructions simulated
sim_seconds 0.212152 # Number of seconds simulated
sim_ticks 212151683000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 80605280 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 86769998 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 3926724 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 92457743 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 92457743 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 70067581 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 7237688 # number cycles where commit BW limit reached
system.cpu.BPredUnit.BTBHits 77353146 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 83702663 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 1593 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 3826409 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 84369915 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 91120892 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1482138 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 70826872 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 7259535 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 415627277 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.445000 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.803105 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 408127750 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.475910 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.811076 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 151327612 36.41% 36.41% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 131463127 31.63% 68.04% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 59591085 14.34% 82.38% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 19300079 4.64% 87.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 16801337 4.04% 91.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 14774918 3.55% 94.62% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 12865599 3.10% 97.71% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 2265832 0.55% 98.26% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 7237688 1.74% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 143768271 35.23% 35.23% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 130628056 32.01% 67.23% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 60243177 14.76% 81.99% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 18962619 4.65% 86.64% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 17622510 4.32% 90.96% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 14296756 3.50% 94.46% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 13120148 3.21% 97.68% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 2226678 0.55% 98.22% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 7259535 1.78% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 415627277 # Number of insts commited each cycle
system.cpu.commit.COM:count 600581394 # Number of instructions committed
system.cpu.commit.COM:committed_per_cycle::total 408127750 # Number of insts commited each cycle
system.cpu.commit.COM:count 602360001 # Number of instructions committed
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 531746837 # Number of committed integer instructions.
system.cpu.commit.COM:loads 148953025 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 219174038 # Number of memory references committed
system.cpu.commit.COM:function_calls 997573 # Number of function calls committed.
system.cpu.commit.COM:int_insts 533522759 # Number of committed integer instructions.
system.cpu.commit.COM:loads 148952624 # Number of loads committed
system.cpu.commit.COM:membars 1328 # Number of memory barriers committed
system.cpu.commit.COM:refs 219173667 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 4754311 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 600581394 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 3642 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 121349980 # The number of squashed insts skipped by commit
system.cpu.committedInsts 600581343 # Number of Instructions Simulated
system.cpu.committedInsts_total 600581343 # Number of Instructions Simulated
system.cpu.cpi 0.722594 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.722594 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 140357692 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13126.895414 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7797.393105 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 140121332 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3102673000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001684 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 236360 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 40725 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1525443000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001394 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 195635 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 17787.364223 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10360.276216 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 67933393 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 26422506996 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.021399 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1485465 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1237601 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2567939504 # number of WriteReq MSHR miss cycles
system.cpu.commit.branchMispredicts 3887306 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 602360001 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 6327 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 105586113 # The number of squashed insts skipped by commit
system.cpu.committedInsts 602359950 # Number of Instructions Simulated
system.cpu.committedInsts_total 602359950 # Number of Instructions Simulated
system.cpu.cpi 0.704402 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.704402 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 1392 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 10807.692308 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_hits 1379 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 140500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.009339 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 13 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 13 # number of LoadLockedReq MSHR hits
system.cpu.dcache.ReadReq_accesses 139573989 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13187.861272 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7875.361074 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 139338017 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3111966000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001691 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 235972 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 40375 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1540397000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 195597 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses 1357 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 1357 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 19453.548688 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10358.949737 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 68088613 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 25852171016 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.019144 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1328918 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1081042 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2567735025 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 247864 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4386.427788 # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_mshr_misses 247876 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4395.291476 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 469.123191 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 2188 # number of cycles access was blocked
system.cpu.dcache.avg_refs 467.742670 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 2182 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 9597504 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 9590526 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 209776550 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 17147.607914 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9229.744608 # average overall mshr miss latency
system.cpu.dcache.demand_hits 208054725 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 29525179996 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.008208 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1721825 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 1278326 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4093382504 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 443499 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 208991520 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 18508.736727 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9263.544849 # average overall mshr miss latency
system.cpu.dcache.demand_hits 207426630 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 28964137016 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.007488 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1564890 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 1121417 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4108132025 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002122 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 443473 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999739 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.932523 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 209776550 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 17147.607914 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9229.744608 # average overall mshr miss latency
system.cpu.dcache.occ_blocks::0 4094.932917 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 208991520 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18508.736727 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9263.544849 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 208054725 # number of overall hits
system.cpu.dcache.overall_miss_latency 29525179996 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.008208 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1721825 # number of overall misses
system.cpu.dcache.overall_mshr_hits 1278326 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4093382504 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 443499 # number of overall MSHR misses
system.cpu.dcache.overall_hits 207426630 # number of overall hits
system.cpu.dcache.overall_miss_latency 28964137016 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.007488 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1564890 # number of overall misses
system.cpu.dcache.overall_mshr_hits 1121417 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4108132025 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002122 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 443473 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 439401 # number of replacements
system.cpu.dcache.sampled_refs 443497 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 439373 # number of replacements
system.cpu.dcache.sampled_refs 443469 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.932523 # Cycle average of tags in use
system.cpu.dcache.total_refs 208054728 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 90723000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 394050 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 84141897 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 763381678 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 172755507 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 145178933 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 17467706 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 13550939 # Number of cycles decode is unblocking
system.cpu.dcache.tagsinuse 4094.932917 # Cycle average of tags in use
system.cpu.dcache.total_refs 207429374 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 89412000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 394062 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 84592597 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 1269 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 6208796 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 740088879 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 168706146 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 141255851 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 15304229 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 4703 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 13573155 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -146,242 +158,242 @@ system.cpu.dtb.read_misses 0 # DT
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 92457743 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 75163466 # Number of cache lines fetched
system.cpu.fetch.Cycles 161721841 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 803288 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 727645114 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 2139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 5447051 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.213048 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 75163466 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 80605280 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.676692 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 433094982 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.793896 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.871529 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.Branches 91120892 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 73409824 # Number of cache lines fetched
system.cpu.fetch.Cycles 157341177 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 853332 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 706778220 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 2056 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 4584124 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.214754 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 73409824 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 78835284 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.665738 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 423431978 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.775923 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.853239 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 271374463 62.66% 62.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 26620223 6.15% 68.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 18536414 4.28% 73.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 23464508 5.42% 78.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 11465886 2.65% 81.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 12676535 2.93% 84.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5122176 1.18% 85.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7816549 1.80% 87.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 56018228 12.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 266090925 62.84% 62.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25382675 5.99% 68.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 18707202 4.42% 73.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 23120734 5.46% 78.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 11518747 2.72% 81.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 12813304 3.03% 84.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4581816 1.08% 85.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7541689 1.78% 87.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 53674886 12.68% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 433094982 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 423431978 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 75163466 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35392.896175 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34027.443106 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 75162551 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 32384500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 915 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 168 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 25418500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_accesses 73409824 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35098.824786 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34224.447514 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 73408888 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 32852500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 936 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 212 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 24778500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 747 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 724 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 100889.330201 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 101956.788889 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 75163466 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35392.896175 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34027.443106 # average overall mshr miss latency
system.cpu.icache.demand_hits 75162551 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 32384500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000012 # miss rate for demand accesses
system.cpu.icache.demand_misses 915 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 168 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 25418500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_accesses 73409824 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35098.824786 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34224.447514 # average overall mshr miss latency
system.cpu.icache.demand_hits 73408888 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 32852500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
system.cpu.icache.demand_misses 936 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 212 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 24778500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 747 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 724 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.323287 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 662.091546 # Average occupied blocks per context
system.cpu.icache.overall_accesses 75163466 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35392.896175 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34027.443106 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.307623 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 630.012478 # Average occupied blocks per context
system.cpu.icache.overall_accesses 73409824 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35098.824786 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34224.447514 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 75162551 # number of overall hits
system.cpu.icache.overall_miss_latency 32384500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000012 # miss rate for overall accesses
system.cpu.icache.overall_misses 915 # number of overall misses
system.cpu.icache.overall_mshr_hits 168 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 25418500 # number of overall MSHR miss cycles
system.cpu.icache.overall_hits 73408888 # number of overall hits
system.cpu.icache.overall_miss_latency 32852500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
system.cpu.icache.overall_misses 936 # number of overall misses
system.cpu.icache.overall_mshr_hits 212 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 24778500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 747 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 724 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 23 # number of replacements
system.cpu.icache.sampled_refs 745 # Sample count of references to valid blocks.
system.cpu.icache.replacements 33 # number of replacements
system.cpu.icache.sampled_refs 720 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 662.091546 # Cycle average of tags in use
system.cpu.icache.total_refs 75162551 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 630.012478 # Cycle average of tags in use
system.cpu.icache.total_refs 73408888 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 881558 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 74261585 # Number of branches executed
system.cpu.iew.EXEC:nop 62913 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.487680 # Inst execution rate
system.cpu.iew.EXEC:refs 240772759 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 74373435 # Number of stores executed
system.cpu.idleCycles 871389 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 73892971 # Number of branches executed
system.cpu.iew.EXEC:nop 61798 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.506493 # Inst execution rate
system.cpu.iew.EXEC:refs 238982736 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 73900874 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 747728792 # num instructions consuming a value
system.cpu.iew.WB:count 638494059 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.593986 # average fanout of values written-back
system.cpu.iew.WB:consumers 738975685 # num instructions consuming a value
system.cpu.iew.WB:count 633750064 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.595052 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 444140095 # num instructions producing a value
system.cpu.iew.WB:rate 1.471264 # insts written-back per cycle
system.cpu.iew.WB:sent 640207091 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 5262481 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 938808 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 184696679 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 3886 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 3056896 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 88578804 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 721929028 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 166399324 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 7744349 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 645618045 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 15544 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 439728869 # num instructions producing a value
system.cpu.iew.WB:rate 1.493625 # insts written-back per cycle
system.cpu.iew.WB:sent 634774515 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 4294677 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 946102 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 181732576 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 5902 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 2934920 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 84682953 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 707943366 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 165081862 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6085968 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 639209952 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 15519 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 10568 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 17467706 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 68840 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 2353 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 15304229 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 50818 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 8986 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 24659910 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 40290 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 8944 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 24296735 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 57403 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 927620 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 15164 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 35743653 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 18357791 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 927620 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1455468 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3807013 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 1741672216 # number of integer regfile reads
system.cpu.int_regfile_writes 500762058 # number of integer regfile writes
system.cpu.ipc 1.383903 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.383903 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 930118 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 15159 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 32779951 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 14461910 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 930118 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 636408 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3658269 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 1727320002 # number of integer regfile reads
system.cpu.int_regfile_writes 496802288 # number of integer regfile writes
system.cpu.ipc 1.419645 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.419645 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 408522313 62.53% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 6689 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 168909835 25.85% 88.38% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 75923554 11.62% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 402470959 62.37% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 6564 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 167645097 25.98% 88.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 75173297 11.65% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 653362394 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 7689776 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011770 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 645295920 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 7755028 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.012018 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 110224 1.43% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 7362915 95.75% 97.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 216637 2.82% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 198697 2.56% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 7348141 94.75% 97.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 208190 2.68% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 433094982 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.508589 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.485286 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 423431978 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.523966 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.473546 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 131707315 30.41% 30.41% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 125173244 28.90% 59.31% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 78416793 18.11% 77.42% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 46415103 10.72% 88.14% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 32898080 7.60% 95.73% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 12956560 2.99% 98.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 3885385 0.90% 99.62% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 717191 0.17% 99.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 925311 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 124767045 29.47% 29.47% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 123576315 29.18% 58.65% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 78343969 18.50% 77.15% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 46750040 11.04% 88.19% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 32770284 7.74% 95.93% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 12193598 2.88% 98.81% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 3344839 0.79% 99.60% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 823717 0.19% 99.80% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 862171 0.20% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 433094982 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.505525 # Inst issue rate
system.cpu.iq.ISSUE:issued_per_cycle::total 423431978 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.520836 # Inst issue rate
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 661052150 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 1748135502 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 638494043 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 843674084 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 721862229 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 653362394 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 3886 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 120901183 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 625992 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 244 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 239953447 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.int_alu_accesses 653050928 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 1722505687 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 633750048 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 814020305 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 707874308 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 645295920 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 7260 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 105229644 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 726877 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 933 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 212022368 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -403,114 +415,114 @@ system.cpu.itb.read_misses 0 # DT
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 247865 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34472.344792 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.636053 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 189395 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2015598000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.235895 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 58470 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828569500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235895 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 58470 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 196377 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34258.354481 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31117.674945 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 163670 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1120488000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.166552 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32707 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency 1017423500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166496 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32696 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_accesses 247874 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.539920 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31261.130694 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 189432 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2008274000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.235773 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 58442 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1826963000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235773 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 58442 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 196316 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34255.152982 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31104.089447 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 163665 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1118465000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.166319 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32651 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency 1015393000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166288 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32645 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_miss_rate 0.333333 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.333333 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 394050 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 394050 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6190.332326 # average number of cycles each access was blocked
system.cpu.l2cache.Writeback_accesses 394062 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 394062 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5824.362606 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.731748 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 331 # number of cycles access was blocked
system.cpu.l2cache.avg_refs 4.737794 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 353 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 2049000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 2056000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 444242 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34395.582219 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.701775 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 353065 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3136086000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.205242 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 91177 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2845993000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.205217 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 91166 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_accesses 444190 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34324.690152 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.848112 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 353097 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3126739000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.205077 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 91093 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2842356000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.205063 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 91087 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.056947 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.488639 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1866.034580 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16011.711774 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 444242 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34395.582219 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.701775 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.056232 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.489259 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1842.604757 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16032.025879 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 444190 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34324.690152 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.848112 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 353065 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3136086000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.205242 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 91177 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2845993000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.205217 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 91166 # number of overall MSHR misses
system.cpu.l2cache.overall_hits 353097 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3126739000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.205077 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 91093 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2842356000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.205063 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 91087 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 72987 # number of replacements
system.cpu.l2cache.sampled_refs 88484 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 72891 # number of replacements
system.cpu.l2cache.sampled_refs 88396 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17877.746353 # Cycle average of tags in use
system.cpu.l2cache.total_refs 418684 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 17874.630636 # Cycle average of tags in use
system.cpu.l2cache.total_refs 418802 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 58152 # number of writebacks
system.cpu.memDep0.conflictingLoads 56143840 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 33466009 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 184696679 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 88578804 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 960863165 # number of misc regfile reads
system.cpu.misc_regfile_writes 9367 # number of misc regfile writes
system.cpu.numCycles 433976540 # number of cpu cycles simulated
system.cpu.l2cache.writebacks 58120 # number of writebacks
system.cpu.memDep0.conflictingLoads 59394757 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 28028248 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 181732576 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 84682953 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 939363465 # number of misc regfile reads
system.cpu.misc_regfile_writes 9368 # number of misc regfile writes
system.cpu.numCycles 424303367 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 12394449 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 469246940 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 63310870 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 190431449 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 3181742 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 2146129409 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 749361548 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 579635255 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 140764920 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 17467706 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 71980154 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 110388312 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:BlockCycles 12681660 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 471025546 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 63633162 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 186161185 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2954668 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 2083466922 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 728669573 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 566468470 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 137330990 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 15304229 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 71846492 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 95442921 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 2146129313 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 56304 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 3959 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 128598458 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 3953 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 1130320351 # The number of ROB reads
system.cpu.rob.rob_writes 1461345715 # The number of ROB writes
system.cpu.timesIdled 36569 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:int_rename_lookups 2083466826 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 107422 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 6263 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 128424972 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 6268 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 1108813717 # The number of ROB reads
system.cpu.rob.rob_writes 1431196844 # The number of ROB writes
system.cpu.timesIdled 36620 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
View file

@ -66,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

10
tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 01:56:16
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:00:03
M5 executing on burrito
M5 compiled Mar 11 2011 20:10:09
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
M5 started Mar 11 2011 20:23:27
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -43,4 +43,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 300302141500 because target called exit()
Exiting @ tick 301191370000 because target called exit()

36
tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1026292 # Simulator instruction rate (inst/s)
host_mem_usage 229344 # Number of bytes of host memory used
host_seconds 585.20 # Real time elapsed on the host
host_tick_rate 513165203 # Simulator tick rate (ticks/s)
host_inst_rate 1838558 # Simulator instruction rate (inst/s)
host_mem_usage 246240 # Number of bytes of host memory used
host_seconds 327.63 # Real time elapsed on the host
host_tick_rate 919312999 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 600581394 # Number of instructions simulated
sim_seconds 0.300302 # Number of seconds simulated
sim_ticks 300302141500 # Number of ticks simulated
sim_insts 602359851 # Number of instructions simulated
sim_seconds 0.301191 # Number of seconds simulated
sim_ticks 301191370000 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -52,24 +52,24 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 600604284 # number of cpu cycles simulated
system.cpu.numCycles 602382741 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 600604284 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_busy_cycles 602382741 # Number of busy cycles
system.cpu.num_conditional_control_insts 67016068 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_func_calls 1993596 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 600581394 # Number of instructions executed
system.cpu.num_int_alu_accesses 531746837 # Number of integer alu accesses
system.cpu.num_int_insts 531746837 # number of integer instructions
system.cpu.num_int_register_reads 1690709529 # number of times the integer registers were read
system.cpu.num_int_register_writes 456307392 # number of times the integer registers were written
system.cpu.num_load_insts 148953025 # Number of load instructions
system.cpu.num_mem_refs 219174038 # number of memory refs
system.cpu.num_insts 602359851 # Number of instructions executed
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
system.cpu.num_int_insts 533522639 # number of integer instructions
system.cpu.num_int_register_reads 1694262461 # number of times the integer registers were read
system.cpu.num_int_register_writes 458085654 # number of times the integer registers were written
system.cpu.num_load_insts 148952594 # Number of load instructions
system.cpu.num_mem_refs 219173607 # number of memory refs
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls

5
tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
View file

@ -51,6 +51,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -86,6 +87,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -121,6 +123,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
@ -166,7 +169,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

10
tests/long/00.gzip/ref/arm/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 01:56:16
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 01:56:25
M5 executing on burrito
M5 compiled Mar 11 2011 20:10:09
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
M5 started Mar 11 2011 20:13:11
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -43,4 +43,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 796759936000 because target called exit()
Exiting @ tick 796762926000 because target called exit()

210
tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,27 +1,31 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 452045 # Simulator instruction rate (inst/s)
host_mem_usage 237056 # Number of bytes of host memory used
host_seconds 1324.25 # Real time elapsed on the host
host_tick_rate 601669731 # Simulator tick rate (ticks/s)
host_inst_rate 732997 # Simulator instruction rate (inst/s)
host_mem_usage 253960 # Number of bytes of host memory used
host_seconds 819.10 # Real time elapsed on the host
host_tick_rate 972728993 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 598619824 # Number of instructions simulated
sim_seconds 0.796760 # Number of seconds simulated
sim_ticks 796759936000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 20842.812219 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.812219 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3956862000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3387333000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses)
sim_insts 600398281 # Number of instructions simulated
sim_seconds 0.796763 # Number of seconds simulated
sim_ticks 796762926000 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 1327 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 147602036 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 189816 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 1327 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 69171110 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits 69169783 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses
@ -30,49 +34,49 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # m
system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 22578.791611 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency
system.cpu.dcache.demand_hits 216774877 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 9880276000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002015 # miss rate for demand accesses
system.cpu.dcache.demand_misses 437591 # number of demand (read+write) misses
system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
system.cpu.dcache.demand_hits 216771819 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 9879688000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses
system.cpu.dcache.demand_misses 437564 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 8567503000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002015 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 437591 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999566 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.223177 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22578.791611 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency
system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 216774877 # number of overall hits
system.cpu.dcache.overall_miss_latency 9880276000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002015 # miss rate for overall accesses
system.cpu.dcache.overall_misses 437591 # number of overall misses
system.cpu.dcache.overall_hits 216771819 # number of overall hits
system.cpu.dcache.overall_miss_latency 9879688000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses
system.cpu.dcache.overall_misses 437564 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 8567503000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002015 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 437591 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 433495 # number of replacements
system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 433468 # number of replacements
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.223177 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 392389 # number of writebacks
system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 392392 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -94,10 +98,10 @@ system.cpu.dtb.read_misses 0 # DT
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses 570070553 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 570069910 # number of ReadReq hits
system.cpu.icache.ReadReq_hits 570073892 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses
@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # ms
system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 886578.398134 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 570070553 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
system.cpu.icache.demand_hits 570069910 # number of demand (read+write) hits
system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 643 # number of demand (read+write) misses
@ -127,12 +131,12 @@ system.cpu.icache.fast_writes 0 # nu
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.282094 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 577.728453 # Average occupied blocks per context
system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context
system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 570069910 # number of overall hits
system.cpu.icache.overall_hits 570073892 # number of overall hits
system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 643 # number of overall misses
@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 12 # number of replacements
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 577.728453 # Cycle average of tags in use
system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use
system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses 58451 # nu
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 158940 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1640392000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.165608 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 31546 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1261840000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165608 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 31546 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 392389 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 392389 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1640132000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 392392 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.718118 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 348237 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4679844000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.205363 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 89997 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 3599880000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.205363 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 89997 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 3599680000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.205364 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.053819 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.492601 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1763.554655 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16141.554862 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses
system.cpu.l2cache.occ_%::0 0.053777 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.492610 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 348237 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4679844000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.205363 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 89997 # number of overall misses
system.cpu.l2cache.overall_hits 348215 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 89992 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 3599880000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.205363 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 89997 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 71809 # number of replacements
system.cpu.l2cache.sampled_refs 87292 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 71804 # number of replacements
system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17905.109517 # Cycle average of tags in use
system.cpu.l2cache.total_refs 411854 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 57886 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1593519872 # number of cpu cycles simulated
system.cpu.numCycles 1593525852 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 1593519872 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_busy_cycles 1593525852 # Number of busy cycles
system.cpu.num_conditional_control_insts 67016068 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_func_calls 1993596 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 598619824 # Number of instructions executed
system.cpu.num_int_alu_accesses 531746837 # Number of integer alu accesses
system.cpu.num_int_insts 531746837 # number of integer instructions
system.cpu.num_int_register_reads 1837343724 # number of times the integer registers were read
system.cpu.num_int_register_writes 456308029 # number of times the integer registers were written
system.cpu.num_load_insts 148953025 # Number of load instructions
system.cpu.num_mem_refs 219174038 # number of memory refs
system.cpu.num_insts 600398281 # Number of instructions executed
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
system.cpu.num_int_insts 533522639 # number of integer instructions
system.cpu.num_int_register_reads 1840897552 # number of times the integer registers were read
system.cpu.num_int_register_writes 458086291 # number of times the integer registers were written
system.cpu.num_load_insts 148952594 # Number of load instructions
system.cpu.num_mem_refs 219173607 # number of memory refs
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls

18
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -10,12 +10,12 @@ type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
console=/chips/pd/randd/dist/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
kernel=/chips/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
pal=/dist/m5/system/binaries/ts_osfpal
pal=/chips/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -142,6 +142,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@ -440,6 +441,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@ -573,6 +575,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@ -871,6 +874,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@ -922,7 +926,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -942,7 +946,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -967,6 +971,7 @@ assoc=8
block_size=64
forward_snoops=false
hash_delay=1
is_top_level=true
latency=50000
max_miss_count=0
mshrs=20
@ -998,6 +1003,7 @@ assoc=8
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
@ -1068,7 +1074,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]

12
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 01:46:17
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 01:46:32
M5 executing on burrito
M5 compiled Mar 15 2011 18:10:57
M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip
M5 started Mar 15 2011 18:10:59
M5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 118370500
Exiting @ tick 1900831034500 because m5_exit instruction encountered
Exiting @ tick 1900831106500 because m5_exit instruction encountered

1732
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

16
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -10,12 +10,12 @@ type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
console=/chips/pd/randd/dist/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
kernel=/chips/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
pal=/dist/m5/system/binaries/ts_osfpal
pal=/chips/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -142,6 +142,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@ -440,6 +441,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@ -491,7 +493,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -511,7 +513,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -536,6 +538,7 @@ assoc=8
block_size=64
forward_snoops=false
hash_delay=1
is_top_level=true
latency=50000
max_miss_count=0
mshrs=20
@ -567,6 +570,7 @@ assoc=8
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
@ -637,7 +641,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]

12
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 01:46:17
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 01:46:32
M5 executing on burrito
M5 compiled Mar 15 2011 18:10:57
M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip
M5 started Mar 15 2011 18:10:59
M5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1866702838500 because m5_exit instruction encountered
Exiting @ tick 1865724648500 because m5_exit instruction encountered

934
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

950
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini Normal file
View file

@ -0,0 +1,950 @@
[root]
type=Root
children=system
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
init_param=0
kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.bridge]
type=Bridge
delay=50000
filter_ranges_a=0:18446744073709551615
filter_ranges_b=0:134217727
nack_delay=4000
req_size_a=16
req_size_b=16
resp_size_a=16
resp_size_b=16
write_ack=false
side_a=system.iobus.port[0]
side_b=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.toL2Bus.port[2]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.toL2Bus.port[4]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.toL2Bus.port[1]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.toL2Bus.port[3]
[system.cpu.tracer]
type=ExeTracer
[system.diskmem]
type=PhysicalMemory
file=/chips/pd/randd/dist/disks/ael-arm.ext2
latency=30000
latency_var=0
null=false
range=134217728:268435455
zero=false
port=system.membus.port[1]
[system.intrctrl]
type=IntrControl
sys=system
[system.iobus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma
[system.iocache]
type=BaseCache
addr_range=0:134217727
assoc=8
block_size=64
forward_snoops=false
hash_delay=1
is_top_level=false
latency=50000
max_miss_count=0
mshrs=20
num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[25]
mem_side=system.membus.port[5]
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
tgts_per_mshr=16
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
mem_side=system.membus.port[6]
[system.membus]
type=Bus
children=badaddr_responder
block_size=64
bus_id=1
clock=1000
header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
pio_addr=0
pio_latency=1000
pio_size=8
platform=system.realview
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=warn
pio=system.membus.default
[system.physmem]
type=PhysicalMemory
file=
latency=30000
latency_var=0
null=false
range=0:134217727
zero=true
port=system.membus.port[2]
[system.realview]
type=RealView
children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
system=system
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268451840
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[20]
[system.realview.cf0_fake]
type=IsaFake
pio_addr=402653184
pio_latency=1000
pio_size=4095
platform=system.realview
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[24]
[system.realview.clcd]
type=Pl111
amba_id=1315089
clock=41667
gic=system.realview.gic
int_num=55
max_backoff_delay=10000000
min_backoff_delay=4000
pio_addr=268566528
pio_latency=10000
platform=system.realview
system=system
vnc=system.vncserver
dma=system.iobus.port[26]
pio=system.iobus.port[5]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268632064
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[8]
[system.realview.flash_fake]
type=IsaFake
pio_addr=1073741824
pio_latency=1000
pio_size=67108864
platform=system.realview
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[23]
[system.realview.gic]
type=Gic
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
dist_pio_delay=10000
it_lines=128
platform=system.realview
system=system
pio=system.membus.port[3]
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268513280
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[15]
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268517376
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[16]
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268521472
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[17]
[system.realview.kmi0]
type=Pl050
amba_id=1314896
gic=system.realview.gic
int_delay=1000000
int_num=52
is_mouse=false
pio_addr=268460032
pio_latency=1000
platform=system.realview
system=system
vnc=system.vncserver
pio=system.iobus.port[6]
[system.realview.kmi1]
type=Pl050
amba_id=1314896
gic=system.realview.gic
int_delay=1000000
int_num=53
is_mouse=true
pio_addr=268464128
pio_latency=1000
platform=system.realview
system=system
vnc=system.vncserver
pio=system.iobus.port[7]
[system.realview.l2x0_fake]
type=IsaFake
pio_addr=520101888
pio_latency=1000
pio_size=4095
platform=system.realview
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.membus.port[4]
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268455936
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[21]
[system.realview.realview_io]
type=RealViewCtrl
pio_addr=268435456
pio_latency=1000
platform=system.realview
proc_id=201326592
system=system
pio=system.iobus.port[2]
[system.realview.rtc_fake]
type=AmbaFake
amba_id=266289
ignore_access=false
pio_addr=268529664
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[22]
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268492800
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[19]
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=269357056
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[12]
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
ignore_access=true
pio_addr=268439552
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[13]
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268488704
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[18]
[system.realview.timer0]
type=Sp804
amba_id=1316868
clock0=1000000
clock1=1000000
gic=system.realview.gic
int_num0=36
int_num1=36
pio_addr=268505088
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[3]
[system.realview.timer1]
type=Sp804
amba_id=1316868
clock0=1000000
clock1=1000000
gic=system.realview.gic
int_num0=37
int_num1=37
pio_addr=268509184
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[4]
[system.realview.uart]
type=Pl011
end_on_eot=false
gic=system.realview.gic
int_delay=100000
int_num=44
pio_addr=268472320
pio_latency=1000
platform=system.realview
system=system
terminal=system.terminal
pio=system.iobus.port[1]
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268476416
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[9]
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268480512
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[10]
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268484608
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[11]
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268500992
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[14]
[system.terminal]
type=Terminal
intr_control=system.intrctrl
number=0
output=true
port=3456
[system.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.vncserver]
type=VncServer
number=0
port=5900

43
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr Executable file
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@ -0,0 +1,43 @@
warn: Sockets disabled, not accepting vnc client connections
For more information see: http://www.m5sim.org/warn/af6a84f6
warn: Sockets disabled, not accepting terminal connections
For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: The clidr register always reports 0 caches.
For more information see: http://www.m5sim.org/warn/23a3c326
warn: The csselr register isn't implemented.
For more information see: http://www.m5sim.org/warn/c0c486b8
warn: Need to flush all TLBs in MP
For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: The ccsidr register isn't implemented and always reads as 0.
For more information see: http://www.m5sim.org/warn/2c4acb9c
warn: instruction 'mcr dccimvac' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: Need to flush all TLBs in MP
For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr dccmvau' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr icimvau' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
For more information see: http://www.m5sim.org/warn/7998f2ea
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
For more information see: http://www.m5sim.org/warn/7998f2ea
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: Need to flush all TLBs in MP
For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
hack: be nice to actually delete the event here

16
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout Executable file
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@ -0,0 +1,16 @@
M5 Simulator System
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 11 2011 20:10:37
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
M5 started Mar 11 2011 20:12:00
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 84388283500 because m5_exit instruction encountered

750
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt Normal file
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@ -0,0 +1,750 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 136897 # Simulator instruction rate (inst/s)
host_mem_usage 384172 # Number of bytes of host memory used
host_seconds 379.57 # Real time elapsed on the host
host_tick_rate 222327398 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 51961461 # Number of instructions simulated
sim_seconds 0.084388 # Number of seconds simulated
sim_ticks 84388283500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 9710586 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 12489985 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 157419 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 644152 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 11960647 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 14006556 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 818238 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 8358835 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 766788 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 96225527 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.541277 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.325518 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 74314309 77.23% 77.23% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 10868177 11.29% 88.52% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 3539344 3.68% 92.20% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 1575243 1.64% 93.84% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 3605097 3.75% 97.59% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 765856 0.80% 98.38% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 506916 0.53% 98.91% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 283797 0.29% 99.20% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 766788 0.80% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 96225527 # Number of insts commited each cycle
system.cpu.commit.COM:count 52084641 # Number of instructions committed
system.cpu.commit.COM:fp_insts 6017 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 529465 # Number of function calls committed.
system.cpu.commit.COM:int_insts 42494142 # Number of committed integer instructions.
system.cpu.commit.COM:loads 9208604 # Number of loads committed
system.cpu.commit.COM:membars 3 # Number of memory barriers committed
system.cpu.commit.COM:refs 16292498 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 712712 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 52084641 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2962577 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 21317023 # The number of squashed insts skipped by commit
system.cpu.committedInsts 51961461 # Number of Instructions Simulated
system.cpu.committedInsts_total 51961461 # Number of Instructions Simulated
system.cpu.cpi 3.248111 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.248111 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses::0 110709 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 110709 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15013.262803 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11890.992284 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
system.cpu.dcache.LoadLockedReq_hits::0 104187 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 104187 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 97916500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058911 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::0 6522 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 6522 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 949 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66268500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050339 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 5573 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 312424000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_accesses::0 10044139 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 10044139 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency::0 14270.972361 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13253.335400 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_hits::0 9552480 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 9552480 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 7016452000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate::0 0.048950 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::0 491659 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 491659 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 243263 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 3292075500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.024730 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 248396 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191881500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.StoreCondReq_accesses::0 104612 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 104612 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::0 104612 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 104612 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses::0 6670215 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6670215 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency::0 39957.308282 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38553.884427 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_hits::0 4625539 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4625539 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 81699749268 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate::0 0.306538 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::0 2044676 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2044676 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1874256 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 6570352984 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025549 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 170420 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 939854183 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7310.688742 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 21687.500000 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 34.045188 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 906 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 24 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 6623484 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 520500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses::0 16714354 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 16714354 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::0 34978.108676 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23548.356519 # average overall mshr miss latency
system.cpu.dcache.demand_hits::0 14178019 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 14178019 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 88716201268 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate::0 0.151746 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.dcache.demand_misses::0 2536335 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2536335 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2117519 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 9862428484 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0.025057 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 418816 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999523 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 511.755643 # Average occupied blocks per context
system.cpu.dcache.overall_accesses::0 16714354 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 16714354 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::0 34978.108676 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23548.356519 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits::0 14178019 # number of overall hits
system.cpu.dcache.overall_hits::1 0 # number of overall hits
system.cpu.dcache.overall_hits::total 14178019 # number of overall hits
system.cpu.dcache.overall_miss_latency 88716201268 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate::0 0.151746 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.dcache.overall_misses::0 2536335 # number of overall misses
system.cpu.dcache.overall_misses::1 0 # number of overall misses
system.cpu.dcache.overall_misses::total 2536335 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2117519 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 9862428484 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::0 0.025057 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 418816 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 39131735683 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 422122 # number of replacements
system.cpu.dcache.sampled_refs 422634 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 511.755643 # Cycle average of tags in use
system.cpu.dcache.total_refs 14388654 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 48260000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 390579 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 54500037 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 71855 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 1270879 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 84249767 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 24736930 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 15841745 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 3334409 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 234983 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1146787 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 36041317 # DTB accesses
system.cpu.dtb.align_faults 1606 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 2757 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 35961278 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 80039 # DTB misses
system.cpu.dtb.perms_faults 987 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 1022 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 28355137 # DTB read accesses
system.cpu.dtb.read_hits 28285868 # DTB read hits
system.cpu.dtb.read_misses 69269 # DTB read misses
system.cpu.dtb.write_accesses 7686180 # DTB write accesses
system.cpu.dtb.write_hits 7675410 # DTB write hits
system.cpu.dtb.write_misses 10770 # DTB write misses
system.cpu.fetch.Branches 14006556 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 6998275 # Number of cache lines fetched
system.cpu.fetch.Cycles 17468426 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 310113 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 71954338 # Number of instructions fetch has processed
system.cpu.fetch.ItlbSquashes 4839 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.MiscStallCycles 24771 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 1293063 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 7917 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.branchRate 0.082989 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 6996896 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 10528824 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.426329 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 99559908 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.876249 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.150340 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 82110011 82.47% 82.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1333573 1.34% 83.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1775516 1.78% 85.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1526454 1.53% 87.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4859277 4.88% 92.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 919627 0.92% 92.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 887823 0.89% 93.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 767860 0.77% 94.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 5379767 5.40% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 99559908 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 5295 # number of floating regfile reads
system.cpu.fp_regfile_writes 1908 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses::0 6998182 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6998182 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency::0 14604.698564 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12005.361734 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_hits::0 6432138 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6432138 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 8266901994 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate::0 0.080884 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::0 566044 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 566044 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 56788 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 6113802495 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.072770 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 509256 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable_latency 4968000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.avg_blocked_cycles::no_mshrs 6198.435115 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 12.630486 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 131 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 811995 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses::0 6998182 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6998182 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::0 14604.698564 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12005.361734 # average overall mshr miss latency
system.cpu.icache.demand_hits::0 6432138 # number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6432138 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 8266901994 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::0 0.080884 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.icache.demand_misses::0 566044 # number of demand (read+write) misses
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 566044 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 56788 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 6113802495 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::0 0.072770 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 509256 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.968631 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 495.939326 # Average occupied blocks per context
system.cpu.icache.overall_accesses::0 6998182 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6998182 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::0 14604.698564 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12005.361734 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.icache.overall_hits::0 6432138 # number of overall hits
system.cpu.icache.overall_hits::1 0 # number of overall hits
system.cpu.icache.overall_hits::total 6432138 # number of overall hits
system.cpu.icache.overall_miss_latency 8266901994 # number of overall miss cycles
system.cpu.icache.overall_miss_rate::0 0.080884 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.icache.overall_misses::0 566044 # number of overall misses
system.cpu.icache.overall_misses::1 0 # number of overall misses
system.cpu.icache.overall_misses::total 566044 # number of overall misses
system.cpu.icache.overall_mshr_hits 56788 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 6113802495 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::0 0.072770 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 509256 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 4968000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 508743 # number of replacements
system.cpu.icache.sampled_refs 509255 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 495.939326 # Cycle average of tags in use
system.cpu.icache.total_refs 6432138 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 6683845000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 41856 # number of writebacks
system.cpu.idleCycles 69216660 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 10300528 # Number of branches executed
system.cpu.iew.EXEC:nop 233998 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.477549 # Inst execution rate
system.cpu.iew.EXEC:refs 36776263 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7992235 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 64109547 # num instructions consuming a value
system.cpu.iew.WB:count 62439853 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.508921 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 32626666 # num instructions producing a value
system.cpu.iew.WB:rate 0.369956 # insts written-back per cycle
system.cpu.iew.WB:sent 79765366 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 803947 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 21361717 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 14069931 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 4021819 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 473480 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 9383175 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 75615816 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 28784028 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1481918 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 80599112 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 30204 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 45946 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 3334409 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 259259 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 8096 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 314225 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 20180 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 524894 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 17006252 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 4861327 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 2299281 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 524894 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 291334 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 512613 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 187216676 # number of integer regfile reads
system.cpu.int_regfile_writes 45171594 # number of integer regfile writes
system.cpu.ipc 0.307871 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.307871 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2392951 2.92% 2.92% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 42044414 51.22% 54.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 91848 0.11% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 12 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 7 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 869 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 29326853 35.73% 89.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 8224069 10.02% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 82081030 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 4843845 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.059013 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 4773 0.10% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 1 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 4516251 93.24% 93.34% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 322820 6.66% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 99559908 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.824439 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384503 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 62623940 62.90% 62.90% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 16850481 16.92% 79.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 7354837 7.39% 87.21% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 4227768 4.25% 91.46% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 6061654 6.09% 97.55% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 1452072 1.46% 99.01% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 668981 0.67% 99.68% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 244691 0.25% 99.92% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 75484 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 99559908 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.486330 # Inst issue rate
system.cpu.iq.fp_alu_accesses 8335 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 15849 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 6220 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 8867 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 84523589 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 268809983 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 62433633 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 98520423 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 71330415 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 82081030 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 4051403 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 22670381 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 180259 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 1088826 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 31630143 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 7013299 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 1597 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 7005382 # DTB hits
system.cpu.itb.inst_accesses 7013299 # ITB inst accesses
system.cpu.itb.inst_hits 7005382 # ITB inst hits
system.cpu.itb.inst_misses 7917 # ITB inst misses
system.cpu.itb.misses 7917 # DTB misses
system.cpu.itb.perms_faults 6664 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.memDep0.conflictingLoads 10842 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 21645 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 14069931 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 9383175 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 92602547 # number of misc regfile reads
system.cpu.misc_regfile_writes 661893 # number of misc regfile writes
system.cpu.numCycles 168776568 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 32961979 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 36893255 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 568385 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 26505270 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2459966 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 448573 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 208179443 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 80158855 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 58599384 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 14253451 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 3334409 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 5274094 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 21706128 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 46818 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 208132625 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 17230705 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 870043 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 14712923 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 727497 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 167920116 # The number of ROB reads
system.cpu.rob.rob_writes 150187680 # The number of ROB writes
system.cpu.timesIdled 1086772 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
system.iocache.overall_miss_latency 0 # number of overall miss cycles
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.overall_misses::0 0 # number of overall misses
system.iocache.overall_misses::1 0 # number of overall misses
system.iocache.overall_misses::total 0 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.replacements 0 # number of replacements
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 0 # number of writebacks
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_mshr_uncacheable_latency 234163500 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.ReadExReq_accesses::0 168750 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 168750 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 52449.907829 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40012.010079 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_hits::0 60799 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 60799 # number of ReadExReq hits
system.l2c.ReadExReq_miss_latency 5662020000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0 0.639710 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0 107951 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 107951 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 4319336500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0 0.639710 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 107951 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0 760723 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 115478 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 876201 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0 52673.934298 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 6776716.981132 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 6829390.915430 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40041.287971 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits::0 740267 # number of ReadReq hits
system.l2c.ReadReq_hits::1 115319 # number of ReadReq hits
system.l2c.ReadReq_hits::total 855586 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 1077498000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0 0.026890 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.001377 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.028267 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0 20456 # number of ReadReq misses
system.l2c.ReadReq_misses::1 159 # number of ReadReq misses
system.l2c.ReadReq_misses::total 20615 # number of ReadReq misses
system.l2c.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency 823849500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0 0.027047 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 0.178172 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.205219 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 20575 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 28940574500 # number of ReadReq MSHR uncacheable cycles
system.l2c.UpgradeReq_accesses::0 1755 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1755 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0 785.423926 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.580720 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_hits::0 33 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_latency 1352500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0 0.981197 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0 1722 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1722 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 68881000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0 0.981197 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 1722 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 746022447 # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses::0 432435 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 432435 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 432435 # number of Writeback hits
system.l2c.Writeback_hits::total 432435 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 8.330108 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses::0 929473 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 115478 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1044951 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 52485.596580 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 42386905.660377 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 42439391.256957 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40016.697011 # average overall mshr miss latency
system.l2c.demand_hits::0 801066 # number of demand (read+write) hits
system.l2c.demand_hits::1 115319 # number of demand (read+write) hits
system.l2c.demand_hits::total 916385 # number of demand (read+write) hits
system.l2c.demand_miss_latency 6739518000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0 0.138150 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.001377 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.139527 # miss rate for demand accesses
system.l2c.demand_misses::0 128407 # number of demand (read+write) misses
system.l2c.demand_misses::1 159 # number of demand (read+write) misses
system.l2c.demand_misses::total 128566 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 40 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 5143186000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0.138278 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 1.112991 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 1.251270 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 128526 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.occ_%::0 0.099103 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.480856 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 6494.821877 # Average occupied blocks per context
system.l2c.occ_blocks::1 31513.354871 # Average occupied blocks per context
system.l2c.overall_accesses::0 929473 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 115478 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1044951 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 52485.596580 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 42386905.660377 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 42439391.256957 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40016.697011 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.l2c.overall_hits::0 801066 # number of overall hits
system.l2c.overall_hits::1 115319 # number of overall hits
system.l2c.overall_hits::total 916385 # number of overall hits
system.l2c.overall_miss_latency 6739518000 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.138150 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.001377 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.139527 # miss rate for overall accesses
system.l2c.overall_misses::0 128407 # number of overall misses
system.l2c.overall_misses::1 159 # number of overall misses
system.l2c.overall_misses::total 128566 # number of overall misses
system.l2c.overall_mshr_hits 40 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 5143186000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0.138278 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 1.112991 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 1.251270 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 128526 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 29686596947 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 94872 # number of replacements
system.l2c.sampled_refs 127034 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 38008.176748 # Cycle average of tags in use
system.l2c.total_refs 1058207 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 87774 # number of writebacks
---------- End Simulation Statistics ----------

1
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status Normal file
View file

@ -0,0 +1 @@
build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 passed.

BIN
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal Normal file
View file

Binary file not shown.

7
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -115,6 +115,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -413,6 +414,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -448,6 +450,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
@ -493,9 +496,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

10
tests/long/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 21 2011 14:34:16
M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
M5 started Feb 21 2011 15:32:42
M5 compiled Mar 11 2011 20:10:09
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
M5 started Mar 11 2011 21:03:35
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -28,4 +28,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 56054651500 because target called exit()
Exiting @ tick 45750115000 because target called exit()

787
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,130 +1,142 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 61070 # Simulator instruction rate (inst/s)
host_mem_usage 389424 # Number of bytes of host memory used
host_seconds 1493.21 # Real time elapsed on the host
host_tick_rate 37539692 # Simulator tick rate (ticks/s)
host_inst_rate 113142 # Simulator instruction rate (inst/s)
host_mem_usage 388016 # Number of bytes of host memory used
host_seconds 806.51 # Real time elapsed on the host
host_tick_rate 56726347 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91190126 # Number of instructions simulated
sim_seconds 0.056055 # Number of seconds simulated
sim_ticks 56054651500 # Number of ticks simulated
sim_insts 91249480 # Number of instructions simulated
sim_seconds 0.045750 # Number of seconds simulated
sim_ticks 45750115000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 20717897 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 22133091 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 1885129 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 22369140 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 22369140 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 18672384 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 365813 # number cycles where commit BW limit reached
system.cpu.BPredUnit.BTBHits 25060777 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 26802034 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 13379 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 1583014 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 23911601 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 29845348 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 62467 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 18706972 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 599512 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 109380669 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.833810 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.220279 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 85858585 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.062935 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.459577 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 55493600 50.73% 50.73% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 34988153 31.99% 82.72% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 8951302 8.18% 90.91% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 6346851 5.80% 96.71% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 1763725 1.61% 98.32% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 198423 0.18% 98.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 611708 0.56% 99.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 661094 0.60% 99.67% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 365813 0.33% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 40879742 47.61% 47.61% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 22675219 26.41% 74.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 9677073 11.27% 85.29% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 7600715 8.85% 94.15% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 2662481 3.10% 97.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 219814 0.26% 97.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 922714 1.07% 98.58% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 621315 0.72% 99.30% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 599512 0.70% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 109380669 # Number of insts commited each cycle
system.cpu.commit.COM:count 91202735 # Number of instructions committed
system.cpu.commit.COM:committed_per_cycle::total 85858585 # Number of insts commited each cycle
system.cpu.commit.COM:count 91262089 # Number of instructions committed
system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 72483223 # Number of committed integer instructions.
system.cpu.commit.COM:loads 22585492 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 27330336 # Number of memory references committed
system.cpu.commit.COM:function_calls 56148 # Number of function calls committed.
system.cpu.commit.COM:int_insts 72532978 # Number of committed integer instructions.
system.cpu.commit.COM:loads 22575791 # Number of loads committed
system.cpu.commit.COM:membars 3888 # Number of memory barriers committed
system.cpu.commit.COM:refs 27322459 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 1941617 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91202735 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 544722 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 11836562 # The number of squashed insts skipped by commit
system.cpu.committedInsts 91190126 # Number of Instructions Simulated
system.cpu.committedInsts_total 91190126 # Number of Instructions Simulated
system.cpu.cpi 1.229402 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.229402 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 23356359 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5257.244166 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2204.745551 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 22405801 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4997315500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.040698 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 950558 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 47017 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1992078000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.038685 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 903541 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 4738868 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 21505.165872 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20098.081505 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 4602377 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2935261595 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.028802 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 136491 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 89917 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 936048048 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009828 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 46574 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2906.794309 # average number of cycles each access was blocked
system.cpu.commit.branchMispredicts 1602069 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91262089 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 554321 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 39090054 # The number of squashed insts skipped by commit
system.cpu.committedInsts 91249480 # Number of Instructions Simulated
system.cpu.committedInsts_total 91249480 # Number of Instructions Simulated
system.cpu.cpi 1.002748 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.002748 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 6707 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17642.857143 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_hits 6700 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 123500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.001044 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits
system.cpu.dcache.ReadReq_accesses 24501880 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5328.400499 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2255.904510 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 23546851 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 5088777000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.038978 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 955029 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 51059 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2039270000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.036894 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 903970 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses 5711 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 5711 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 24088.951664 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22495.719344 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 4561444 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 4180324405 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.036650 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 173537 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 127274 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 1040719464 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009770 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 46263 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2889.691936 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 28.426220 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 6009 # number of cycles access was blocked
system.cpu.dcache.avg_refs 29.593485 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 7453 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 17466927 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 21536874 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 28095227 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 7297.350069 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3081.864877 # average overall mshr miss latency
system.cpu.dcache.demand_hits 27008178 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 7932577095 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.038692 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1087049 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 136934 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 2928126048 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.033818 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 950115 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 29236861 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 8213.167334 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3241.299201 # average overall mshr miss latency
system.cpu.dcache.demand_hits 28108295 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 9269101405 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.038601 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1128566 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 178333 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3079989464 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.032501 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 950233 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.851200 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3486.513459 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 28095227 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 7297.350069 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3081.864877 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.852939 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3493.638101 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 29236861 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 8213.167334 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3241.299201 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 27008178 # number of overall hits
system.cpu.dcache.overall_miss_latency 7932577095 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.038692 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1087049 # number of overall misses
system.cpu.dcache.overall_mshr_hits 136934 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 2928126048 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.033818 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 950115 # number of overall MSHR misses
system.cpu.dcache.overall_hits 28108295 # number of overall hits
system.cpu.dcache.overall_miss_latency 9269101405 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.038601 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1128566 # number of overall misses
system.cpu.dcache.overall_mshr_hits 178333 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3079989464 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.032501 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 950233 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 946019 # number of replacements
system.cpu.dcache.sampled_refs 950115 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 946137 # number of replacements
system.cpu.dcache.sampled_refs 950233 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3486.513459 # Cycle average of tags in use
system.cpu.dcache.total_refs 27008178 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 23888324000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 943195 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 6646243 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 108354440 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 27877036 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 74250519 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 2697135 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 606870 # Number of cycles decode is unblocking
system.cpu.dcache.tagsinuse 3493.638101 # Cycle average of tags in use
system.cpu.dcache.total_refs 28120706 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 19296981000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 943150 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 18515611 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 9136 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 4758893 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 141080898 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 33469255 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 33017602 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 5612232 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 30592 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 856116 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -146,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 22369140 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 12683528 # Number of cache lines fetched
system.cpu.fetch.Cycles 76804780 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 214312 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 109645002 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 18268 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 1945739 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.199530 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 12683528 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 20717897 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.978019 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 112077803 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.986563 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.108841 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.Branches 29845348 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 15520576 # Number of cache lines fetched
system.cpu.fetch.Cycles 34753915 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 276813 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 143294690 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 20423 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 1615761 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.326178 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 15520576 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 25123244 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.566058 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 91470816 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.578120 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.573721 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 35656347 31.81% 31.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 60887079 54.33% 86.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 7618220 6.80% 92.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 828250 0.74% 93.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4141725 3.70% 97.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2560072 2.28% 99.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 241812 0.22% 99.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 9014 0.01% 99.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 135284 0.12% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 56780865 62.08% 62.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 6426529 7.03% 69.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 6459161 7.06% 76.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4449430 4.86% 81.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3594685 3.93% 84.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1897731 2.07% 87.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1934782 2.12% 89.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3238407 3.54% 92.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6689226 7.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 112077803 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 75 # number of floating regfile reads
system.cpu.fp_regfile_writes 47 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 12683528 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36327.096774 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34505.200594 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 12682753 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 28153500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 775 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 102 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 23222000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 673 # number of ReadReq MSHR misses
system.cpu.fetch.rateDist::total 91470816 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 87 # number of floating regfile reads
system.cpu.fp_regfile_writes 78 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 15520576 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35610.047847 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34405.604720 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 15519740 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 29770000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000054 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 836 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 158 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 23327000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000044 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 678 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 18845.101040 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 22890.471976 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 12683528 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 36327.096774 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34505.200594 # average overall mshr miss latency
system.cpu.icache.demand_hits 12682753 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 28153500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses
system.cpu.icache.demand_misses 775 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 102 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 23222000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 673 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 15520576 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35610.047847 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34405.604720 # average overall mshr miss latency
system.cpu.icache.demand_hits 15519740 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 29770000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000054 # miss rate for demand accesses
system.cpu.icache.demand_misses 836 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 158 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 23327000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000044 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 678 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.278329 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 570.018353 # Average occupied blocks per context
system.cpu.icache.overall_accesses 12683528 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36327.096774 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34505.200594 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.276985 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 567.265894 # Average occupied blocks per context
system.cpu.icache.overall_accesses 15520576 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35610.047847 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34405.604720 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 12682753 # number of overall hits
system.cpu.icache.overall_miss_latency 28153500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses
system.cpu.icache.overall_misses 775 # number of overall misses
system.cpu.icache.overall_mshr_hits 102 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 23222000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 673 # number of overall MSHR misses
system.cpu.icache.overall_hits 15519740 # number of overall hits
system.cpu.icache.overall_miss_latency 29770000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000054 # miss rate for overall accesses
system.cpu.icache.overall_misses 836 # number of overall misses
system.cpu.icache.overall_mshr_hits 158 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 23327000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000044 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 678 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 3 # number of replacements
system.cpu.icache.sampled_refs 673 # Sample count of references to valid blocks.
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.sampled_refs 678 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 570.018353 # Cycle average of tags in use
system.cpu.icache.total_refs 12682753 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 567.265894 # Cycle average of tags in use
system.cpu.icache.total_refs 15519740 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 31501 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 19532471 # Number of branches executed
system.cpu.iew.EXEC:nop 62748 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.868101 # Inst execution rate
system.cpu.iew.EXEC:refs 28649527 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 5007239 # Number of stores executed
system.cpu.idleCycles 29415 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 20970115 # Number of branches executed
system.cpu.iew.EXEC:nop 54598 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.133641 # Inst execution rate
system.cpu.iew.EXEC:refs 30199659 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 5140774 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 90073370 # num instructions consuming a value
system.cpu.iew.WB:count 96561407 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.596775 # average fanout of values written-back
system.cpu.iew.WB:consumers 127211016 # num instructions consuming a value
system.cpu.iew.WB:count 102056385 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.487951 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 53753580 # num instructions producing a value
system.cpu.iew.WB:rate 0.861315 # insts written-back per cycle
system.cpu.iew.WB:sent 96831306 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2055858 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 89156 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 24681129 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 553822 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 1090186 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 5533282 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 103041042 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 23642288 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2270342 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 97322249 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 1607 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 62072763 # num instructions producing a value
system.cpu.iew.WB:rate 1.115368 # insts written-back per cycle
system.cpu.iew.WB:sent 102572716 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 1825852 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 421320 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 32016564 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 690308 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 299404 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 6585994 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 130352707 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 25058885 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2046100 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 103728443 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 170905 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 2697135 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 23177 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 1567 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 5612232 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 206705 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 17440 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 113868 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 30334 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 21484 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 353411 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 19757 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 1330 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 2095636 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 788438 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 1330 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 76110 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1979748 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 246243554 # number of integer regfile reads
system.cpu.int_regfile_writes 76222698 # number of integer regfile writes
system.cpu.ipc 0.813404 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.813404 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 3168 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 9440772 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1839326 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 3168 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 298332 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1527520 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 259522598 # number of integer regfile reads
system.cpu.int_regfile_writes 80481877 # number of integer regfile writes
system.cpu.ipc 0.997260 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.997260 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 70280458 70.57% 70.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 10479 0.01% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 2 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 11 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 27 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 3 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 24261777 24.36% 94.94% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 5039834 5.06% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 74292294 70.24% 70.24% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 10639 0.01% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 21 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 38 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 4 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 26262906 24.83% 95.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 5208640 4.92% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 99592591 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 491330 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.004933 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 105774543 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 160185 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.001514 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 430175 87.55% 87.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 27 0.01% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 26408 5.37% 92.93% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 34720 7.07% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 52262 32.63% 32.63% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 27 0.02% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 32.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 62957 39.30% 71.95% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 44939 28.05% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 112077803 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.888602 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.089642 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 91470816 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.156375 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.444584 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 47855391 42.70% 42.70% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 42755359 38.15% 80.85% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 14035968 12.52% 93.37% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 4551717 4.06% 97.43% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 786660 0.70% 98.13% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 736099 0.66% 98.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1220793 1.09% 99.88% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 128276 0.11% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 7540 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 39774696 43.48% 43.48% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 24298391 26.56% 70.05% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 14242553 15.57% 85.62% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 6365982 6.96% 92.58% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 2257550 2.47% 95.05% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2688100 2.94% 97.98% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1607594 1.76% 99.74% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 110764 0.12% 99.86% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 125186 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 112077803 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.888353 # Inst issue rate
system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 144 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 100083847 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 311754559 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 96561341 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 112732108 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 102424472 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 99592591 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 553822 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 9752691 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 388 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 9100 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 13565681 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::total 91470816 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.156003 # Inst issue rate
system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 190 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 87 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 166 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 105934631 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 303205662 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 102056298 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 169015166 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 129602907 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 105774543 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 695202 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 38714982 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 25765 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 140881 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 72800988 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -404,106 +416,107 @@ system.cpu.itb.read_misses 0 # DT
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 46574 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34284.629133 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31026.465938 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 32027 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 498738500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.312342 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 14547 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451342000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312342 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 14547 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 904214 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34295.295295 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.850051 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 903215 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 34261000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.001105 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 999 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency 30699500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001092 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 987 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 943195 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 943195 # number of Writeback hits
system.cpu.l2cache.ReadExReq_accesses 46263 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34215.214251 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31037.691726 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 31724 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 497455000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.314268 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 14539 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451257000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.314268 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 14539 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 904648 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34281.219272 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31102.589641 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 903631 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 34864000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.001124 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1017 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 13 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency 31227000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001110 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1004 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 943150 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 943150 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 103.008184 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 102.932573 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 950788 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34285.314550 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31031.382773 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 935242 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 532999500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.016351 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 15546 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 482041500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.016338 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 15534 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_accesses 950911 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34219.529442 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31041.883806 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 935355 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 532319000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.016359 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 15556 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 13 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 482484000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.016345 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 15543 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.012324 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.246682 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 403.843587 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8083.268197 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 950788 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34285.314550 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31031.382773 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.012326 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.249116 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 403.905799 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8163.029985 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 950911 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34219.529442 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31041.883806 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 935242 # number of overall hits
system.cpu.l2cache.overall_miss_latency 532999500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.016351 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 15546 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 482041500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.016338 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 15534 # number of overall MSHR misses
system.cpu.l2cache.overall_hits 935355 # number of overall hits
system.cpu.l2cache.overall_miss_latency 532319000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.016359 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 15556 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 13 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 482484000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.016345 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 15543 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 709 # number of replacements
system.cpu.l2cache.sampled_refs 15518 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 704 # number of replacements
system.cpu.l2cache.sampled_refs 15528 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8487.111783 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1598481 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 8566.935784 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1598337 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 32 # number of writebacks
system.cpu.memDep0.conflictingLoads 436025 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 249497 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 24681129 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5533282 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 157552597 # number of misc regfile reads
system.cpu.misc_regfile_writes 1603309 # number of misc regfile writes
system.cpu.numCycles 112109304 # number of cpu cycles simulated
system.cpu.memDep0.conflictingLoads 1440720 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1005315 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 32016564 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 6585994 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 198555291 # number of misc regfile reads
system.cpu.misc_regfile_writes 1603310 # number of misc regfile writes
system.cpu.numCycles 91500231 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 294826 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 72061910 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 4906 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 29931132 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 31548 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 277443671 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 106593764 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 83924752 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 72730204 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 2697135 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 723329 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 11862839 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 474 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 277443197 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 5701177 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 592742 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 1065555 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 576556 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 212048419 # The number of ROB reads
system.cpu.rob.rob_writes 208775892 # The number of ROB writes
system.cpu.timesIdled 1292 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:BlockCycles 3003526 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 72121263 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2932731 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 36158864 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2288265 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 58 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 352780022 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 136654080 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 107391797 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 31135789 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 5612232 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 6274602 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 35270531 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 655 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 352779367 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 9285803 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 702152 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 13506306 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 702838 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 215605482 # The number of ROB reads
system.cpu.rob.rob_writes 266316908 # The number of ROB writes
system.cpu.timesIdled 1399 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
View file

@ -66,9 +66,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

10
tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 01:56:16
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 01:56:24
M5 executing on burrito
M5 compiled Mar 11 2011 20:10:09
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
M5 started Mar 11 2011 20:10:13
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -28,4 +28,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 54215549000 because target called exit()
Exiting @ tick 54240666000 because target called exit()

36
tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 937948 # Simulator instruction rate (inst/s)
host_mem_usage 362060 # Number of bytes of host memory used
host_seconds 97.24 # Real time elapsed on the host
host_tick_rate 557562760 # Simulator tick rate (ticks/s)
host_inst_rate 1915165 # Simulator instruction rate (inst/s)
host_mem_usage 378952 # Number of bytes of host memory used
host_seconds 47.65 # Real time elapsed on the host
host_tick_rate 1138365446 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91202735 # Number of instructions simulated
sim_seconds 0.054216 # Number of seconds simulated
sim_ticks 54215549000 # Number of ticks simulated
sim_insts 91252969 # Number of instructions simulated
sim_seconds 0.054241 # Number of seconds simulated
sim_ticks 54240666000 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -52,24 +52,24 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 108431099 # number of cpu cycles simulated
system.cpu.numCycles 108481333 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 108431099 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_busy_cycles 108481333 # Number of busy cycles
system.cpu.num_conditional_control_insts 15112201 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_func_calls 97900 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 91202735 # Number of instructions executed
system.cpu.num_int_alu_accesses 72483223 # Number of integer alu accesses
system.cpu.num_int_insts 72483223 # number of integer instructions
system.cpu.num_int_register_reads 234567931 # number of times the integer registers were read
system.cpu.num_int_register_writes 72546720 # number of times the integer registers were written
system.cpu.num_load_insts 22585492 # Number of load instructions
system.cpu.num_mem_refs 27330336 # number of memory refs
system.cpu.num_insts 91252969 # Number of instructions executed
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
system.cpu.num_int_insts 72525682 # number of integer instructions
system.cpu.num_int_register_reads 234656737 # number of times the integer registers were read
system.cpu.num_int_register_writes 72596953 # number of times the integer registers were written
system.cpu.num_load_insts 22573967 # Number of load instructions
system.cpu.num_mem_refs 27318811 # number of memory refs
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls

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