diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 3adc7e5c9..ffcd63c49 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -34,6 +34,7 @@ class L1Cache(BaseCache):
     latency = '1ns'
     mshrs = 10
     tgts_per_mshr = 5
+    is_top_level = True
 
 class L2Cache(BaseCache):
     assoc = 8
@@ -49,6 +50,7 @@ class PageTableWalkerCache(BaseCache):
     mshrs = 10
     size = '1kB'
     tgts_per_mshr = 12
+    is_top_level = True
 
 class IOCache(BaseCache):
     assoc = 8
@@ -58,3 +60,4 @@ class IOCache(BaseCache):
     size = '1kB'
     tgts_per_mshr = 12
     forward_snoops = False
+    is_top_level = True
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 2c6696ea7..48ece0db4 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -201,13 +201,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
     self.membus = MemBus(bus_id=1)
     self.membus.badaddr_responder.warn_access = "warn"
     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
-    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
-    self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'),
-                                  file = disk('ael-arm.ext2'))
     self.bridge.side_a = self.iobus.port
     self.bridge.side_b = self.membus.port
-    self.physmem.port = self.membus.port
-    self.diskmem.port = self.membus.port
 
     self.mem_mode = mem_mode
 
@@ -232,13 +227,19 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
     if bare_metal:
         # EOT character on UART will end the simulation
         self.realview.uart.end_on_eot = True
+        self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')), zero = True)
     else:
+        self.physmem = PhysicalMemory(range = AddrRange(Addr('128MB')), zero = True)
+        self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'),
+                                  file = disk('ael-arm.ext2'))
+        self.diskmem.port = self.membus.port
         self.machine_type = machine_type
         self.kernel = binary('vmlinux.arm')
         self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0' +          \
                 ' lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000' + \
                 ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0'
 
+    self.physmem.port = self.membus.port
     self.realview.attachOnChipIO(self.membus)
     self.realview.attachIO(self.iobus)
 
diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
index a8788051f..2f8c4c2ef 100644
--- a/src/arch/alpha/predecoder.hh
+++ b/src/arch/alpha/predecoder.hh
@@ -76,6 +76,12 @@ class Predecoder
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void
diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh
index fbdd10d68..0e33a9214 100644
--- a/src/arch/arm/insts/branch.hh
+++ b/src/arch/arm/insts/branch.hh
@@ -57,6 +57,7 @@ class BranchImm : public PredOp
               int32_t _imm) :
         PredOp(mnem, _machInst, __opClass), imm(_imm)
     {}
+
 };
 
 // Conditionally Branch to a target computed with an immediate
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 2a45cf2e6..8a82bd319 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -58,8 +58,13 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
 {
     uint32_t regs = reglist;
     uint32_t ones = number_of_ones(reglist);
-    // Remember that writeback adds a uop
-    numMicroops = ones + (writeback ? 1 : 0) + 1;
+    // Remember that writeback adds a uop or two and the temp register adds one
+    numMicroops = ones + (writeback ? (load ? 2 : 1) : 0) + 1;
+
+    // It's technically legal to do a lot of nothing
+    if (!ones)
+        numMicroops = 1;
+
     microOps = new StaticInstPtr[numMicroops];
     uint32_t addr = 0;
 
@@ -70,28 +75,13 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
         addr += 4;
 
     StaticInstPtr *uop = microOps;
-    StaticInstPtr wbUop;
-    if (writeback) {
-        if (up) {
-            wbUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
-        } else {
-            wbUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
-        }
-    }
 
     // Add 0 to Rn and stick it in ureg0.
     // This is equivalent to a move.
     *uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
 
-    // Write back at the start for loads. This covers the ldm exception return
-    // case where the base needs to be written in the old mode. Stores may need
-    // the original value of the base, but they don't change mode and can
-    // write back at the end like before.
-    if (load && writeback) {
-        *++uop = wbUop;
-    }
-
     unsigned reg = 0;
+    unsigned regIdx = 0;
     bool force_user = user & !bits(reglist, 15);
     bool exception_ret = user & bits(reglist, 15);
 
@@ -101,19 +91,28 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
             reg++;
         replaceBits(regs, reg, 0);
 
-        unsigned regIdx = reg;
+        regIdx = reg;
         if (force_user) {
             regIdx = intRegInMode(MODE_USER, regIdx);
         }
 
         if (load) {
-            if (reg == INTREG_PC && exception_ret) {
-                // This must be the exception return form of ldm.
-                *++uop = new MicroLdrRetUop(machInst, regIdx,
-                                           INTREG_UREG0, up, addr);
+            if (writeback && i == ones - 1) {
+                // If it's a writeback and this is the last register
+                // do the load into a temporary register which we'll move
+                // into the final one later
+                *++uop = new MicroLdrUop(machInst, INTREG_UREG1, INTREG_UREG0,
+                        up, addr);
             } else {
-                *++uop = new MicroLdrUop(machInst, regIdx,
-                                        INTREG_UREG0, up, addr);
+                // Otherwise just do it normally
+                if (reg == INTREG_PC && exception_ret) {
+                    // This must be the exception return form of ldm.
+                    *++uop = new MicroLdrRetUop(machInst, regIdx,
+                                               INTREG_UREG0, up, addr);
+                } else {
+                    *++uop = new MicroLdrUop(machInst, regIdx,
+                                            INTREG_UREG0, up, addr);
+                }
             }
         } else {
             *++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
@@ -125,8 +124,32 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
             addr -= 4;
     }
 
-    if (!load && writeback) {
-        *++uop = wbUop;
+    if (writeback && ones) {
+        // put the register update after we're done all loading
+        if (up)
+            *++uop = new MicroAddiUop(machInst, rn, rn, ones * 4);
+        else
+            *++uop = new MicroSubiUop(machInst, rn, rn, ones * 4);
+
+        // If this was a load move the last temporary value into place
+        // this way we can't take an exception after we update the base
+        // register.
+        if (load && reg == INTREG_PC && exception_ret) {
+            *++uop = new MicroUopRegMovRet(machInst, 0, INTREG_UREG1);
+            warn("creating instruction with exception return at curTick:%d\n",
+                    curTick());
+        } else if (load) {
+            *++uop = new MicroUopRegMov(machInst, regIdx, INTREG_UREG1);
+            if (reg == INTREG_PC) {
+                (*uop)->setFlag(StaticInstBase::IsControl);
+                (*uop)->setFlag(StaticInstBase::IsCondControl);
+                (*uop)->setFlag(StaticInstBase::IsIndirectControl);
+                // This is created as a RAS POP
+                if (rn == INTREG_SP)
+                    (*uop)->setFlag(StaticInstBase::IsReturn);
+
+            }
+        }
     }
 
     (*uop)->setLastMicroop();
@@ -895,6 +918,15 @@ MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     return ss.str();
 }
 
+std::string
+MicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    ss << "[PC,CPSR]";
+    return ss.str();
+}
+
 std::string
 MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index 1a2db8b9a..4933a1e7c 100644
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -134,6 +134,27 @@ class MicroNeonMixLaneOp : public MicroNeonMixOp
     {
     }
 };
+
+/**
+ * Microops of the form
+ * PC   = IntRegA
+ * CPSR = IntRegB
+ */
+class MicroSetPCCPSR : public MicroOp
+{
+    protected:
+    IntRegIndex ura, urb, urc;
+
+    MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+                   IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
+        : MicroOp(mnem, machInst, __opClass),
+          ura(_ura), urb(_urb), urc(_urc)
+    {
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 /**
  * Microops of the form IntRegA = IntRegB
  */
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index a4fc62603..324d86fed 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -97,14 +97,18 @@ class RfeOp : public MightBeMicro
     IntRegIndex base;
     AddrMode mode;
     bool wb;
-    static const unsigned numMicroops = 2;
+    IntRegIndex ura, urb, urc;
+    static const unsigned numMicroops = 3;
 
     StaticInstPtr *uops;
 
     RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
           IntRegIndex _base, AddrMode _mode, bool _wb)
         : MightBeMicro(mnem, _machInst, __opClass),
-          base(_base), mode(_mode), wb(_wb), uops(NULL)
+          base(_base), mode(_mode), wb(_wb),
+          ura(INTREG_UREG0), urb(INTREG_UREG1),
+          urc(INTREG_UREG2),
+          uops(NULL)
     {}
 
     virtual
diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh
index 4b2cc560d..2cbed6c59 100644
--- a/src/arch/arm/intregs.hh
+++ b/src/arch/arm/intregs.hh
@@ -110,6 +110,8 @@ enum IntRegIndex
 
     INTREG_ZERO, // Dummy zero reg since there has to be one.
     INTREG_UREG0,
+    INTREG_UREG1,
+    INTREG_UREG2,
     INTREG_CONDCODES,
     INTREG_FPCONDCODES,
 
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 4bdbe77ce..d720becba 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -143,6 +143,16 @@ ISA::clear()
 
     miscRegs[MISCREG_CPACR] = 0;
     miscRegs[MISCREG_FPSID] = 0x410430A0;
+
+    // See section B4.1.84 of ARM ARM
+    // All values are latest for ARMv7-A profile
+    miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
+    miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
+    miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
+    miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
+    miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
+    miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
+
     //XXX We need to initialize the rest of the state.
 }
 
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 3a0cad1c5..2267ee34f 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -143,7 +143,7 @@ let {{
                                                  bits(machInst, 22) << 4);
         const uint32_t type = bits(machInst, 11, 8);
         uint32_t size = 0;
-        uint32_t align = 0;
+        uint32_t align = TLB::MustBeOne;
         unsigned inc = 1;
         unsigned regs = 1;
         unsigned lane = 0;
diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa
index d8ea2118e..84b9bb720 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -48,6 +48,8 @@ let {{
         bCode = '''
         NPC = (uint32_t)(PC + imm);
         '''
+        br_tgt_code = '''pcs.instNPC(branchPC.instPC() + imm);'''
+        instFlags = ["IsDirectControl"]
         if (link):
             bCode += '''
                 if (Thumb)
@@ -55,12 +57,15 @@ let {{
                 else
                     LR = PC - 4;
             '''
+            instFlags += ["IsCall"]
+
 
         bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
-                             {"code": bCode,
-                              "predicate_test": predicateTest})
+                             {"code": bCode, "predicate_test": predicateTest,
+                             "brTgtCode" : br_tgt_code}, instFlags)
         header_output += BranchImmCondDeclare.subst(bIop)
-        decoder_output += BranchImmCondConstructor.subst(bIop)
+        decoder_output += BranchImmCondConstructor.subst(bIop) + \
+                       BranchTarget.subst(bIop)
         exec_output += PredOpExecute.subst(bIop)
 
     # BX, BLX
@@ -81,15 +86,22 @@ let {{
             # Since we're switching ISAs, the target ISA will be the opposite
             # of the current ISA. Thumb is whether the target is ARM.
             newPC = '(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
+            br_tgt_code = '''
+            pcs.instNPC((branchPC.thumb() ? (roundDown(branchPC.instPC(),4) + imm) :
+                                (branchPC.instPC() + imm)));
+            '''
             base = "BranchImmCond"
             declare = BranchImmCondDeclare
             constructor = BranchImmCondConstructor
+            instFlags = ["IsDirectControl"]
         else:
             Name += "Reg"
             newPC = 'Op1'
+            br_tgt_code = ''
             base = "BranchRegCond"
             declare = BranchRegCondDeclare
             constructor = BranchRegCondConstructor
+            instFlags = ["IsIndirectControl"]
         if link and imm:
             linkStr = '''
                 // The immediate version of the blx thumb instruction
@@ -100,6 +112,7 @@ let {{
                 else
                     LR = PC - 4;
             '''
+            instFlags += ["IsCall"]
         elif link:
             linkStr = '''
                 if (Thumb)
@@ -107,14 +120,18 @@ let {{
                 else
                     LR = PC - 4;
             '''
+            instFlags += ["IsCall"]
         else:
             linkStr = ""
+            instFlags += ["IsReturn"]
 
         if imm and link: #blx with imm
             branchStr = '''
                 NextThumb = !Thumb;
                 NPC = %(newPC)s;
             '''
+            br_tgt_code = '''pcs.nextThumb(!branchPC.thumb());\n''' + \
+                          br_tgt_code
         else:
             branchStr = "IWNPC = %(newPC)s;"
         branchStr = branchStr % { "newPC" : newPC }
@@ -123,11 +140,13 @@ let {{
                           "newPC": newPC,
                           "branch": branchStr}
         blxIop = InstObjParams(mnem, Name, base,
-                               {"code": code,
-                                "predicate_test": predicateTest})
+                               {"code": code, "brTgtCode" : br_tgt_code,
+                                "predicate_test": predicateTest}, instFlags)
         header_output += declare.subst(blxIop)
         decoder_output += constructor.subst(blxIop)
         exec_output += PredOpExecute.subst(blxIop)
+        if imm:
+            decoder_output += BranchTarget.subst(blxIop)
 
     #Ignore BXJ for now
 
@@ -136,7 +155,8 @@ let {{
         code = 'NPC = (uint32_t)(PC + imm);\n'
         predTest = "Op1 %(test)s 0" % {"test": test}
         iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
-                            {"code": code, "predicate_test": predTest})
+                            {"code": code, "predicate_test": predTest},
+                            ["IsIndirectControl"])
         header_output += BranchImmRegDeclare.subst(iop)
         decoder_output += BranchImmRegConstructor.subst(iop)
         exec_output += PredOpExecute.subst(iop)
@@ -164,7 +184,8 @@ let {{
         iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
                             {'ea_code': eaCode,
                              'memacc_code': accCode,
-                             'predicate_test': predicateTest})
+                             'predicate_test': predicateTest},
+                             ["IsIndirectControl"])
         header_output += BranchTableDeclare.subst(iop)
         decoder_output += BranchRegRegConstructor.subst(iop)
         exec_output += LoadExecute.subst(iop) + \
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index c60a91a50..2e45f2875 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -67,7 +67,7 @@ let {{
             self.memFlags = ["ArmISA::TLB::MustBeOne"]
             self.codeBlobs = {"postacc_code" : ""}
 
-        def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = []):
+        def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = [], pcDecl = None):
 
             global header_output, decoder_output, exec_output
 
@@ -76,7 +76,8 @@ let {{
             (newHeader,
              newDecoder,
              newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
-                                           self.memFlags, instFlags, base, wbDecl)
+                                           self.memFlags, instFlags, base,
+                                           wbDecl, pcDecl)
 
             header_output += newHeader
             decoder_output += newDecoder
@@ -104,26 +105,18 @@ let {{
                 wbDiff = 8
             accCode = '''
             CPSR cpsr = Cpsr;
-            SCTLR sctlr = Sctlr;
-            // Use the version of NPC that gets set before NextThumb
-            pNPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
-            uint32_t tempSpsr = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
-            uint32_t newCpsr =
-                cpsrWriteByInstr(cpsr | CondCodes, tempSpsr,
-                                 0xF, true, sctlr.nmfi);
-            Cpsr = ~CondCodesMask & newCpsr;
-            NextThumb = ((CPSR)newCpsr).t;
-            NextJazelle = ((CPSR)newCpsr).j;
-            ForcedItState = ((((CPSR)tempSpsr).it2 << 2) & 0xFC)
-                | (((CPSR)tempSpsr).it1 & 0x3);
-            CondCodes = CondCodesMask & newCpsr;
+            URc = cpsr | CondCodes;
+            URa = cSwap<uint32_t>(Mem.ud, cpsr.e);
+            URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
             '''
             self.codeBlobs["memacc_code"] = accCode
 
             wbDecl = None
+            pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);"
+
             if self.writeback:
                 wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff
-            self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"])
+            self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"], pcDecl)
 
     class LoadImmInst(LoadInst):
         def __init__(self, *args, **kargs):
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index da3609bbc..8521cbc97 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -66,7 +66,7 @@ let {{
                              ["IsNonSpeculative", "IsQuiesce"])
     header_output += BasicDeclare.subst(quiesceIop)
     decoder_output += BasicConstructor.subst(quiesceIop)
-    exec_output += PredOpExecute.subst(quiesceIop)
+    exec_output += QuiescePredOpExecute.subst(quiesceIop)
 
     quiesceNsCode = '''
 #if FULL_SYSTEM
@@ -80,7 +80,7 @@ let {{
                              ["IsNonSpeculative", "IsQuiesce"])
     header_output += BasicDeclare.subst(quiesceNsIop)
     decoder_output += BasicConstructor.subst(quiesceNsIop)
-    exec_output += PredOpExecute.subst(quiesceNsIop)
+    exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
 
     quiesceCyclesCode = '''
 #if FULL_SYSTEM
@@ -94,7 +94,7 @@ let {{
                              ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
     header_output += BasicDeclare.subst(quiesceCyclesIop)
     decoder_output += BasicConstructor.subst(quiesceCyclesIop)
-    exec_output += PredOpExecute.subst(quiesceCyclesIop)
+    exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
 
     quiesceTimeCode = '''
 #if FULL_SYSTEM
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 33d57a60b..15879e0e3 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -51,7 +51,7 @@ let {{
     microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
                                    'MicroMemOp',
                                    {'memacc_code': microLdrUopCode,
-                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
+                                    'ea_code': 'EA = URb + (up ? imm : -imm);',
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])
 
@@ -60,7 +60,7 @@ let {{
                                       'MicroMemOp',
                                       {'memacc_code': microLdrFpUopCode,
                                        'ea_code': vfpEnabledCheckCode +
-                                           'EA = Rb + (up ? imm : -imm);',
+                                           'EA = URb + (up ? imm : -imm);',
                                        'predicate_test': predicateTest},
                                       ['IsMicroop'])
 
@@ -69,7 +69,7 @@ let {{
                                       'MicroMemOp',
                                       {'memacc_code': microLdrFpUopCode,
                                        'ea_code': vfpEnabledCheckCode + '''
-                                        EA = Rb + (up ? imm : -imm) +
+                                        EA = URb + (up ? imm : -imm) +
                                              (((CPSR)Cpsr).e ? 4 : 0);
                                         ''',
                                        'predicate_test': predicateTest},
@@ -80,37 +80,40 @@ let {{
                                       'MicroMemOp',
                                       {'memacc_code': microLdrFpUopCode,
                                        'ea_code': vfpEnabledCheckCode + '''
-                                        EA = Rb + (up ? imm : -imm) -
+                                        EA = URb + (up ? imm : -imm) -
                                              (((CPSR)Cpsr).e ? 4 : 0);
                                         ''',
                                        'predicate_test': predicateTest},
                                       ['IsMicroop'])
 
-    microLdrRetUopCode = '''
+    microRetUopCode = '''
         CPSR cpsr = Cpsr;
         SCTLR sctlr = Sctlr;
         uint32_t newCpsr =
             cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
         CondCodes = CondCodesMask & newCpsr;
-        IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
+        IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
         ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
                 | (((CPSR)Spsr).it1 & 0x3);
     '''
+
     microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
                                       'MicroMemOp',
-                                      {'memacc_code': microLdrRetUopCode,
+                                      {'memacc_code':
+                                          microRetUopCode % 'Mem.uw',
                                        'ea_code':
-                                          'EA = Rb + (up ? imm : -imm);',
+                                          'EA = URb + (up ? imm : -imm);',
                                        'predicate_test': condPredicateTest},
-                                      ['IsMicroop','IsNonSpeculative','IsSerializeAfter'])
+                                      ['IsMicroop','IsNonSpeculative',
+                                       'IsSerializeAfter'])
 
-    microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);"
+    microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
     microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
                                    'MicroMemOp',
                                    {'memacc_code': microStrUopCode,
                                     'postacc_code': "",
-                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
+                                    'ea_code': 'EA = URb + (up ? imm : -imm);',
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])
 
@@ -120,7 +123,7 @@ let {{
                                      {'memacc_code': microStrFpUopCode,
                                       'postacc_code': "",
                                       'ea_code': vfpEnabledCheckCode +
-                                           'EA = Rb + (up ? imm : -imm);',
+                                           'EA = URb + (up ? imm : -imm);',
                                       'predicate_test': predicateTest},
                                      ['IsMicroop'])
 
@@ -130,7 +133,7 @@ let {{
                                        {'memacc_code': microStrFpUopCode,
                                         'postacc_code': "",
                                         'ea_code': vfpEnabledCheckCode + '''
-                                         EA = Rb + (up ? imm : -imm) +
+                                         EA = URb + (up ? imm : -imm) +
                                               (((CPSR)Cpsr).e ? 4 : 0);
                                          ''',
                                         'predicate_test': predicateTest},
@@ -142,7 +145,7 @@ let {{
                                        {'memacc_code': microStrFpUopCode,
                                         'postacc_code': "",
                                         'ea_code': vfpEnabledCheckCode + '''
-                                         EA = Rb + (up ? imm : -imm) -
+                                         EA = URb + (up ? imm : -imm) -
                                               (((CPSR)Cpsr).e ? 4 : 0);
                                          ''',
                                         'predicate_test': predicateTest},
@@ -170,7 +173,7 @@ let {{
 let {{
     exec_output = header_output = ''
 
-    eaCode = 'EA = Ra + imm;'
+    eaCode = 'EA = URa + imm;'
 
     for size in (1, 2, 3, 4, 6, 8, 12, 16):
         # Set up the memory access.
@@ -572,14 +575,14 @@ let {{
 let {{
     microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
                                     'MicroIntImmOp',
-                                    {'code': 'Ra = Rb + imm;',
+                                    {'code': 'URa = URb + imm;',
                                      'predicate_test': predicateTest},
                                     ['IsMicroop'])
 
     microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
                                    'MicroIntRegOp',
                                    {'code':
-                                    '''Ra = Rb + shift_rm_imm(Rc, shiftAmt,
+                                    '''URa = URb + shift_rm_imm(URc, shiftAmt,
                                                               shiftType,
                                                               CondCodes<29:>);
                                     ''',
@@ -588,14 +591,14 @@ let {{
 
     microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
                                     'MicroIntImmOp',
-                                    {'code': 'Ra = Rb - imm;',
+                                    {'code': 'URa = URb - imm;',
                                      'predicate_test': predicateTest},
                                     ['IsMicroop'])
 
     microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
                                    'MicroIntRegOp',
                                    {'code':
-                                    '''Ra = Rb - shift_rm_imm(Rc, shiftAmt,
+                                    '''URa = URb - shift_rm_imm(URc, shiftAmt,
                                                               shiftType,
                                                               CondCodes<29:>);
                                     ''',
@@ -604,27 +607,62 @@ let {{
 
     microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
                                    'MicroIntMov',
-                                   {'code': 'IWRa = Rb;',
+                                   {'code': 'IWRa = URb;',
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])
 
+    microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet',
+                                      'MicroIntMov',
+                                     {'code': microRetUopCode % 'URb',
+                                      'predicate_test': predicateTest},
+                                     ['IsMicroop', 'IsNonSpeculative',
+                                      'IsSerializeAfter'])
+
+    setPCCPSRDecl = '''
+                    CPSR cpsrOrCondCodes = URc;
+                    SCTLR sctlr = Sctlr;
+                    pNPC = URa;
+                    uint32_t newCpsr =
+                    cpsrWriteByInstr(cpsrOrCondCodes, URb,
+                                     0xF, true, sctlr.nmfi);
+                    Cpsr = ~CondCodesMask & newCpsr;
+                    NextThumb = ((CPSR)newCpsr).t;
+                    NextJazelle = ((CPSR)newCpsr).j;
+                    ForcedItState = ((((CPSR)URb).it2 << 2) & 0xFC)
+                                    | (((CPSR)URb).it1 & 0x3);
+                    CondCodes = CondCodesMask & newCpsr;
+                    '''
+
+    microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
+                                         'MicroSetPCCPSR',
+                                         {'code': setPCCPSRDecl,
+                                          'predicate_test': predicateTest},
+                                         ['IsMicroop'])
+
     header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
                     MicroIntImmDeclare.subst(microSubiUopIop) + \
                     MicroIntRegDeclare.subst(microAddUopIop) + \
                     MicroIntRegDeclare.subst(microSubUopIop) + \
-                    MicroIntMovDeclare.subst(microUopRegMovIop)
+                    MicroIntMovDeclare.subst(microUopRegMovIop) + \
+                    MicroIntMovDeclare.subst(microUopRegMovRetIop) + \
+                    MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop)
 
     decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
                      MicroIntImmConstructor.subst(microSubiUopIop) + \
                      MicroIntRegConstructor.subst(microAddUopIop) + \
                      MicroIntRegConstructor.subst(microSubUopIop) + \
-                     MicroIntMovConstructor.subst(microUopRegMovIop)
+                     MicroIntMovConstructor.subst(microUopRegMovIop) + \
+                     MicroIntMovConstructor.subst(microUopRegMovRetIop) + \
+                     MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop)
 
     exec_output = PredOpExecute.subst(microAddiUopIop) + \
                   PredOpExecute.subst(microSubiUopIop) + \
                   PredOpExecute.subst(microAddUopIop) + \
                   PredOpExecute.subst(microSubUopIop) + \
-                  PredOpExecute.subst(microUopRegMovIop)
+                  PredOpExecute.subst(microUopRegMovIop) + \
+                  PredOpExecute.subst(microUopRegMovRetIop) + \
+                  PredOpExecute.subst(microUopSetPCCPSRIop)
+
 }};
 
 let {{
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa
index 507f8cd4b..d0c0f0710 100644
--- a/src/arch/arm/isa/insts/mem.isa
+++ b/src/arch/arm/isa/insts/mem.isa
@@ -48,7 +48,7 @@ let {{
             self.constructTemplate = eval(self.decConstBase + 'Constructor')
 
         def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags,
-                          base = 'Memory', wbDecl = None):
+                          base = 'Memory', wbDecl = None, pcDecl = None):
             # Make sure flags are in lists (convert to lists if not).
             memFlags = makeList(memFlags)
             instFlags = makeList(instFlags)
@@ -65,12 +65,26 @@ let {{
             macroName = Name
             instFlagsCopy = list(instFlags)
             codeBlobsCopy = dict(codeBlobs)
-            if wbDecl is not None:
+
+            use_uops = 0
+            if wbDecl is not None or pcDecl is not None:
                 instFlagsCopy.append('IsMicroop')
                 Name = Name + 'Acc'
+                use_uops = 1
+
+            use_wb = 0
+            use_pc = 0
+            if wbDecl is not None:
+                use_wb = 1
+            if pcDecl is not None:
+                use_pc = 1
+
             codeBlobsCopy['acc_name'] = Name
             codeBlobsCopy['wb_decl'] = wbDecl
+            codeBlobsCopy['pc_decl'] = pcDecl
             codeBlobsCopy['use_uops'] = 0
+            codeBlobsCopy['use_wb'] = 0
+            codeBlobsCopy['use_pc'] = 0
 
             iop = InstObjParams(name, Name, base,
                                 codeBlobsCopy, instFlagsCopy)
@@ -81,11 +95,14 @@ let {{
                           self.initiateAccTemplate.subst(iop) + \
                           self.completeAccTemplate.subst(iop)
 
-            if wbDecl is not None:
+            if wbDecl is not None or pcDecl is not None:
                 iop = InstObjParams(name, macroName, base,
                                     { "wb_decl" : wbDecl,
+                                      "pc_decl" : pcDecl,
                                       "acc_name" : Name,
-                                      "use_uops" : 1 },
+                                      "use_uops" : use_uops,
+                                      "use_pc" : use_pc,
+                                      "use_wb" : use_wb },
                                     ['IsMacroop'])
                 header_output += self.declareTemplate.subst(iop)
                 decoder_output += self.constructTemplate.subst(iop)
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index be51d927d..cf5c7b47a 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -491,10 +491,13 @@ let {{
 
     wfeCode = '''
 #if FULL_SYSTEM
-    if (SevMailbox)
+    if (SevMailbox) {
         SevMailbox = 0;
-    else
+        PseudoInst::quiesceSkip(xc->tcBase());
+    }
+    else {
         PseudoInst::quiesce(xc->tcBase());
+    }
 #endif
     '''
     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
@@ -502,7 +505,7 @@ let {{
             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
     header_output += BasicDeclare.subst(wfeIop)
     decoder_output += BasicConstructor.subst(wfeIop)
-    exec_output += PredOpExecute.subst(wfeIop)
+    exec_output += QuiescePredOpExecute.subst(wfeIop)
 
     wfiCode = '''
 #if FULL_SYSTEM
@@ -511,22 +514,25 @@ let {{
     '''
     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
             { "code" : wfiCode, "predicate_test" : predicateTest },
-            ["IsNonSpeculative", "IsQuiesce"])
+            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
     header_output += BasicDeclare.subst(wfiIop)
     decoder_output += BasicConstructor.subst(wfiIop)
-    exec_output += PredOpExecute.subst(wfiIop)
+    exec_output += QuiescePredOpExecute.subst(wfiIop)
 
     sevCode = '''
     // Need a way for O3 to not scoreboard these accesses as pipe flushes.
+    SevMailbox = 1;
     System *sys = xc->tcBase()->getSystemPtr();
     for (int x = 0; x < sys->numContexts(); x++) {
         ThreadContext *oc = sys->getThreadContext(x);
-        oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+        if (oc != xc->tcBase()) {
+            oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+        }
     }
     '''
     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
             { "code" : sevCode, "predicate_test" : predicateTest },
-            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
+            ["IsNonSpeculative", "IsSquashAfter"])
     header_output += BasicDeclare.subst(sevIop)
     decoder_output += BasicConstructor.subst(sevIop)
     exec_output += PredOpExecute.subst(sevIop)
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index f661961f7..e5d47c28f 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -222,7 +222,6 @@ let {{
         decConstBase = 'StoreExImm'
         basePrefix = 'MemoryExImm'
         nameFunc = staticmethod(storeImmClassName)
-        instFlags = ['IsStoreConditional']
 
         def __init__(self, *args, **kargs):
             super(StoreImmEx, self).__init__(*args, **kargs)
@@ -302,7 +301,6 @@ let {{
         decConstBase = 'StoreExDImm'
         basePrefix = 'MemoryExDImm'
         nameFunc = staticmethod(storeDoubleImmClassName)
-        instFlags = ['IsStoreConditional']
 
         def __init__(self, *args, **kargs):
             super(StoreDoubleImmEx, self).__init__(*args, **kargs)
@@ -370,10 +368,14 @@ let {{
 
     buildDoubleStores("strd")
 
-    StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit()
-    StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit()
-    StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit()
-    StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit()
+    StoreImmEx("strex", False, True, False, size=4, flavor="exclusive",
+               instFlags = ['IsStoreConditional']).emit()
+    StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive",
+               instFlags = ['IsStoreConditional']).emit()
+    StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive",
+               instFlags = ['IsStoreConditional']).emit()
+    StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive",
+               instFlags = ['IsStoreConditional']).emit()
 
     StoreImm("vstr", False, True, False, size=4, flavor="fp").emit()
     StoreImm("vstr", False, False, False, size=4, flavor="fp").emit()
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index f403f9372..7b014acd0 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -228,11 +228,11 @@ def operands {{
     'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
 
     #Register fields for microops
-    'Ra' : intReg('ura'),
+    'URa' : intReg('ura'),
     'IWRa' : intRegIWPC('ura'),
     'Fa' : floatReg('ura'),
-    'Rb' : intReg('urb'),
-    'Rc' : intReg('urc'),
+    'URb' : intReg('urb'),
+    'URc' : intReg('urc'),
 
     #Memory Operand
     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index d1f581f51..6abf76963 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -57,7 +57,11 @@ def template BranchImmConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
+
     }
 }};
 
@@ -69,6 +73,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst, int32_t _imm,
                        ConditionCode _condCode);
         %(BasicExecDeclare)s
+        ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
 };
 }};
 
@@ -84,6 +89,9 @@ def template BranchImmCondConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -108,6 +116,9 @@ def template BranchRegConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -135,6 +146,9 @@ def template BranchRegCondConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -176,6 +190,9 @@ def template BranchRegRegConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -202,6 +219,26 @@ def template BranchImmRegConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
+
+def template BranchTarget {{
+
+    ArmISA::PCState
+    %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const
+    {
+        %(op_decl)s;
+        %(op_rd)s;
+
+        ArmISA::PCState pcs = branchPC;
+        %(brTgtCode)s
+        pcs.advance();
+        return pcs;
+    }
+}};
+
+
diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa
index b7ca7fa48..a7f7f0da8 100644
--- a/src/arch/arm/isa/templates/macromem.isa
+++ b/src/arch/arm/isa/templates/macromem.isa
@@ -107,6 +107,41 @@ def template MicroNeonMemDeclare {{
     };
 }};
 
+////////////////////////////////////////////////////////////////////
+//
+// PC   = Integer(ura)
+// CPSR = Integer(urb)
+//
+
+def template MicroSetPCCPSRDeclare {{
+    class %(class_name)s : public %(base_class)s
+    {
+      public:
+        %(class_name)s(ExtMachInst machInst,
+                       IntRegIndex _ura,
+                       IntRegIndex _urb,
+                       IntRegIndex _urc);
+        %(BasicExecDeclare)s
+    };
+}};
+
+def template MicroSetPCCPSRConstructor {{
+    %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                   IntRegIndex _ura,
+                                   IntRegIndex _urb,
+                                   IntRegIndex _urc)
+          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+                           _ura, _urb, _urc)
+    {
+        %(constructor)s;
+        if (!(condCode == COND_AL || condCode == COND_UC)) {
+            for (int x = 0; x < _numDestRegs; x++) {
+                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+            }
+        }
+    }
+}};
+
 ////////////////////////////////////////////////////////////////////
 //
 // Integer = Integer op Integer microops
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 3d073b322..dcfd47ace 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -917,9 +917,9 @@ def template CompleteAccDeclare {{
 
 def template RfeConstructor {{
     inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
-            uint32_t _base, int _mode, bool _wb)
-         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
-                 (IntRegIndex)_base, (AddrMode)_mode, _wb)
+                                          uint32_t _base, int _mode, bool _wb)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+                         (IntRegIndex)_base, (AddrMode)_mode, _wb)
     {
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
@@ -928,12 +928,18 @@ def template RfeConstructor {{
             }
         }
 #if %(use_uops)d
-        assert(numMicroops >= 2);
-        uops = new StaticInstPtr[numMicroops];
-        uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
-        uops[0]->setDelayedCommit();
-        uops[1] = new %(wb_decl)s;
-        uops[1]->setLastMicroop();
+        uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d];
+        int uopIdx = 0;
+        uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb);
+        uops[uopIdx]->setDelayedCommit();
+#if %(use_wb)d
+        uops[++uopIdx] = new %(wb_decl)s;
+        uops[uopIdx]->setDelayedCommit();
+#endif
+#if %(use_pc)d
+        uops[++uopIdx] = new %(pc_decl)s;
+#endif
+        uops[uopIdx]->setLastMicroop();
 #endif
     }
 }};
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index c9e7b1803..2a4bd9dab 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -170,6 +170,38 @@ def template PredOpExecute {{
     }
 }};
 
+def template QuiescePredOpExecute {{
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+    {
+        Fault fault = NoFault;
+        uint64_t resTemp = 0;
+        resTemp = resTemp;
+        %(op_decl)s;
+        %(op_rd)s;
+
+        if (%(predicate_test)s)
+        {
+            %(code)s;
+            if (fault == NoFault)
+            {
+                %(op_wb)s;
+            }
+        } else {
+            xc->setPredicate(false);
+#if FULL_SYSTEM
+            PseudoInst::quiesceSkip(xc->tcBase());
+#endif
+        }
+
+        if (fault == NoFault && machInst.itstateMask != 0&&
+                (!isMicroop() || isLastMicroop())) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
+        return fault;
+    }
+}};
+
 def template DataDecode {{
     if (machInst.opcode4 == 0) {
         if (machInst.sField == 0)
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index e3455d211..fc48ec12d 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -197,7 +197,7 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = {
     /* 117 */ SyscallDesc("ipc", unimplementedFunc),
     /* 118 */ SyscallDesc("fsync", unimplementedFunc),
     /* 119 */ SyscallDesc("sigreturn", unimplementedFunc),
-    /* 120 */ SyscallDesc("clone", unimplementedFunc),
+    /* 120 */ SyscallDesc("clone", cloneFunc),
     /* 121 */ SyscallDesc("setdomainname", unimplementedFunc),
     /* 122 */ SyscallDesc("uname", unameFunc),
     /* 123 */ SyscallDesc("unused#123", unimplementedFunc),
@@ -239,7 +239,7 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = {
     /* 159 */ SyscallDesc("sched_get_priority_max", unimplementedFunc),
     /* 160 */ SyscallDesc("sched_get_priority_min", unimplementedFunc),
     /* 161 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc),
-    /* 162 */ SyscallDesc("nanosleep", unimplementedFunc),
+    /* 162 */ SyscallDesc("nanosleep", ignoreWarnOnceFunc),
     /* 163 */ SyscallDesc("mremap", mremapFunc<ArmLinux>), // ARM-specific
     /* 164 */ SyscallDesc("setresuid", unimplementedFunc),
     /* 165 */ SyscallDesc("getresuid", unimplementedFunc),
@@ -251,8 +251,8 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = {
     /* 171 */ SyscallDesc("getresgid", unimplementedFunc),
     /* 172 */ SyscallDesc("prctl", unimplementedFunc),
     /* 173 */ SyscallDesc("rt_sigreturn", unimplementedFunc),
-    /* 174 */ SyscallDesc("rt_sigaction", ignoreFunc),
-    /* 175 */ SyscallDesc("rt_sigprocmask", unimplementedFunc),
+    /* 174 */ SyscallDesc("rt_sigaction", ignoreWarnOnceFunc),
+    /* 175 */ SyscallDesc("rt_sigprocmask", ignoreWarnOnceFunc),
     /* 176 */ SyscallDesc("rt_sigpending", unimplementedFunc),
     /* 177 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc),
     /* 178 */ SyscallDesc("rt_sigqueueinfo", ignoreFunc),
@@ -317,7 +317,7 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = {
     /* 237 */ SyscallDesc("fremovexattr", unimplementedFunc),
     /* 238 */ SyscallDesc("tkill", unimplementedFunc),
     /* 239 */ SyscallDesc("sendfile64", unimplementedFunc),
-    /* 240 */ SyscallDesc("futex", unimplementedFunc),
+    /* 240 */ SyscallDesc("futex", ignoreWarnOnceFunc),
     /* 241 */ SyscallDesc("sched_setaffinity", unimplementedFunc),
     /* 242 */ SyscallDesc("sched_getaffinity", unimplementedFunc),
     /* 243 */ SyscallDesc("io_setup", unimplementedFunc),
@@ -456,6 +456,7 @@ setTLSFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
 
     tc->getMemPort()->writeBlob(ArmLinuxProcess::commPage + 0x0ff0,
                                 (uint8_t *)&tlsPtr, sizeof(tlsPtr));
+    tc->setMiscReg(MISCREG_TPIDRURO,tlsPtr);
     return 0;
 }
 
@@ -508,7 +509,7 @@ ArmLinuxProcess::startup()
     ThreadContext *tc = system->getThreadContext(contextIds[0]);
 
     uint8_t swiNeg1[] = {
-        0xff, 0xff, 0xff, 0xef  //swi -1
+        0xff, 0xff, 0xff, 0xef  // swi -1
     };
 
     // Fill this page with swi -1 so we'll no if we land in it somewhere.
@@ -521,7 +522,8 @@ ArmLinuxProcess::startup()
     // @todo Add a barrrier in this code
     uint8_t memory_barrier[] =
     {
-        0x0e, 0xf0, 0xa0, 0xe1  //usr_ret lr
+        0x5f, 0xf0, 0x7f, 0xf5, // dmb
+        0x0e, 0xf0, 0xa0, 0xe1  // return
     };
     tc->getMemPort()->writeBlob(commPage + 0x0fa0, memory_barrier,
                                 sizeof(memory_barrier));
@@ -531,18 +533,22 @@ ArmLinuxProcess::startup()
     // @todo replace this with ldrex/strex and dmb
     uint8_t cmpxchg[] =
     {
-        0x00, 0x30, 0x92, 0xe5, //ldr r3, [r2]
-        0x00, 0x30, 0x53, 0xe0, //subs r3, r3, r0
-        0x00, 0x10, 0x82, 0x05, //streq r1, [r2]
-        0x03, 0x00, 0xa0, 0xe1, //mov r0, r3
-        0x0e, 0xf0, 0xa0, 0xe1  //usr_ret lr
+        0x9f, 0x3f, 0x92, 0xe1,  // ldrex    r3, [r2]
+        0x00, 0x30, 0x53, 0xe0,  // subs     r3, r3, r0
+        0x91, 0x3f, 0x82, 0x01,  // strexeq  r3, r1, [r2]
+        0x01, 0x00, 0x33, 0x03,  // teqeq    r3, #1
+        0xfa, 0xff, 0xff, 0x0a,  // beq 1b
+        0x00, 0x00, 0x73, 0xe2,  // rsbs r0, r3, #0
+        0x5f, 0xf0, 0x7f, 0xf5,  // dmb
+        0x0e, 0xf0, 0xa0, 0xe1   // return
     };
     tc->getMemPort()->writeBlob(commPage + 0x0fc0, cmpxchg, sizeof(cmpxchg));
 
     uint8_t get_tls[] =
     {
-        0x08, 0x00, 0x9f, 0xe5, //ldr r0, [pc, #(16 - 8)]
-        0x0e, 0xf0, 0xa0, 0xe1  //usr_ret lr
+                                // read user read-only thread id register
+        0x70, 0x0f, 0x1d, 0xee, // mrc p15, 0, r0, c13, c0, 3
+        0x0e, 0xf0, 0xa0, 0xe1  // return
     };
     tc->getMemPort()->writeBlob(commPage + 0x0fe0, get_tls, sizeof(get_tls));
 }
diff --git a/src/arch/arm/linux/system.cc b/src/arch/arm/linux/system.cc
index 38024c058..7aff2b6ef 100644
--- a/src/arch/arm/linux/system.cc
+++ b/src/arch/arm/linux/system.cc
@@ -47,9 +47,11 @@
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"
+#include "kern/linux/events.hh"
 #include "mem/physical.hh"
 
 using namespace ArmISA;
+using namespace Linux;
 
 LinuxArmSystem::LinuxArmSystem(Params *p)
     : ArmSystem(p)
@@ -96,6 +98,24 @@ LinuxArmSystem::LinuxArmSystem(Params *p)
     if (!kernelPanicEvent)
         panic("could not find kernel symbol \'panic\'");
 #endif
+
+    // With ARM udelay() is #defined to __udelay
+    Addr addr = 0;
+    if (kernelSymtab->findAddress("__udelay", addr)) {
+        uDelaySkipEvent = new UDelayEvent(&pcEventQueue, "__udelay",
+                fixFuncEventAddr(addr), 1000, 0);
+    } else {
+        panic("couldn't find kernel symbol \'udelay\'");
+    }
+
+    // constant arguments to udelay() have some precomputation done ahead of
+    // time. Constant comes from code.
+    if (kernelSymtab->findAddress("__const_udelay", addr)) {
+        constUDelaySkipEvent = new UDelayEvent(&pcEventQueue, "__const_udelay",
+                fixFuncEventAddr(addr), 1000, 107374);
+    } else {
+        panic("couldn't find kernel symbol \'udelay\'");
+    }
 }
 
 void
@@ -115,6 +135,10 @@ LinuxArmSystem::initState()
 
 LinuxArmSystem::~LinuxArmSystem()
 {
+    if (uDelaySkipEvent)
+        delete uDelaySkipEvent;
+    if (constUDelaySkipEvent)
+        delete constUDelaySkipEvent;
 }
 
 LinuxArmSystem *
diff --git a/src/arch/arm/linux/system.hh b/src/arch/arm/linux/system.hh
index 4e5ebcd73..2ef65fea2 100644
--- a/src/arch/arm/linux/system.hh
+++ b/src/arch/arm/linux/system.hh
@@ -74,6 +74,19 @@ class LinuxArmSystem : public ArmSystem
     /** Event to halt the simulator if the kernel calls panic()  */
     BreakPCEvent *kernelPanicEvent;
 #endif
+    /**
+     * PC based event to skip udelay(<time>) calls and quiesce the
+     * processor for the appropriate amount of time. This is not functionally
+     * required but does speed up simulation.
+     */
+    Linux::UDelayEvent *uDelaySkipEvent;
+
+    /** Another PC based skip event for const_udelay(). Similar to the udelay
+     * skip, but this function precomputes the first multiply that is done
+     * in the generic case since the parameter is known at compile time.
+     * Thus we need to do some division to get back to us.
+     */
+    Linux::UDelayEvent *constUDelaySkipEvent;
 };
 
 #endif // __ARCH_ARM_LINUX_SYSTEM_HH__
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 90b4fd999..47495a4e7 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -165,6 +165,12 @@ namespace ArmISA
         MISCREG_PMUSERENR,
         MISCREG_PMINTENSET,
         MISCREG_PMINTENCLR,
+        MISCREG_ID_ISAR0,
+        MISCREG_ID_ISAR1,
+        MISCREG_ID_ISAR2,
+        MISCREG_ID_ISAR3,
+        MISCREG_ID_ISAR4,
+        MISCREG_ID_ISAR5,
         MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
         MISCREG_ID_PFR1,
@@ -173,12 +179,6 @@ namespace ArmISA
         MISCREG_ID_MMFR1,
         MISCREG_ID_MMFR2,
         MISCREG_ID_MMFR3,
-        MISCREG_ID_ISAR0,
-        MISCREG_ID_ISAR1,
-        MISCREG_ID_ISAR2,
-        MISCREG_ID_ISAR3,
-        MISCREG_ID_ISAR4,
-        MISCREG_ID_ISAR5,
         MISCREG_AIDR,
         MISCREG_ADFSR,
         MISCREG_AIFSR,
@@ -233,13 +233,12 @@ namespace ArmISA
         "pmswinc", "pmselr", "pmceid0",
         "pmceid1", "pmc_other", "pmxevcntr",
         "pmuserenr", "pmintenset", "pmintenclr",
+        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
          // Unimplemented below
         "tcmtr",
         "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr1", "id_mmfr2", "id_mmfr3",
-        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
-        "aidr",
-        "adfsr", "aifsr",
+        "aidr", "adfsr", "aifsr",
         "dcimvac", "dcisw", "mccsw",
         "dccmvau",
         "nsacr",
diff --git a/src/arch/arm/predecoder.hh b/src/arch/arm/predecoder.hh
index a99e38ce7..08e1676c0 100644
--- a/src/arch/arm/predecoder.hh
+++ b/src/arch/arm/predecoder.hh
@@ -83,6 +83,12 @@ namespace ArmISA
             predAddrValid = false;
         }
 
+        void reset(const ExtMachInst &old_emi)
+        {
+            reset();
+            itstate = old_emi.newItstate;
+        }
+
         Predecoder(ThreadContext * _tc) :
             tc(_tc), data(0)
         {
@@ -122,17 +128,17 @@ namespace ArmISA
                 outOfBytes = true;
         }
 
-        bool needMoreBytes()
+        bool needMoreBytes() const
         {
             return outOfBytes;
         }
 
-        bool extMachInstReady()
+        bool extMachInstReady() const
         {
             return emiReady;
         }
 
-        int getInstSize()
+        int getInstSize() const
         {
             return (!emi.thumb || emi.bigThumb) ? 4 : 2;
         }
@@ -145,6 +151,7 @@ namespace ArmISA
             pc.npc(pc.pc() + getInstSize());
             predAddrValid = true;
             predAddr = pc.pc() + getInstSize();
+            pc.size(getInstSize());
             emi = 0;
             emiReady = false;
             return thisEmi;
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index e6865e280..b4ef07d8a 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -203,6 +203,7 @@ namespace ArmISA
         uint8_t flags;
         uint8_t nextFlags;
         uint8_t forcedItStateValue;
+        uint8_t _size;
         bool forcedItStateValid;
       public:
         PCState() : flags(0), nextFlags(0), forcedItStateValue(0), forcedItStateValid(false)
@@ -248,6 +249,16 @@ namespace ArmISA
                 nextFlags &= ~ThumbBit;
         }
 
+        void size(uint8_t s) { _size = s; }
+        uint8_t size() const { return _size; }
+
+        bool
+        branching() const
+        {
+            return ((this->pc() + this->size()) != this->npc());
+        }
+
+
         bool
         jazelle() const
         {
@@ -392,6 +403,7 @@ namespace ArmISA
         {
             Base::serialize(os);
             SERIALIZE_SCALAR(flags);
+            SERIALIZE_SCALAR(_size);
             SERIALIZE_SCALAR(nextFlags);
             SERIALIZE_SCALAR(forcedItStateValue);
             SERIALIZE_SCALAR(forcedItStateValid);
@@ -402,6 +414,7 @@ namespace ArmISA
         {
             Base::unserialize(cp, section);
             UNSERIALIZE_SCALAR(flags);
+            UNSERIALIZE_SCALAR(_size);
             UNSERIALIZE_SCALAR(nextFlags);
             UNSERIALIZE_SCALAR(forcedItStateValue);
             UNSERIALIZE_SCALAR(forcedItStateValid);
diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh
index 4220b768c..110493cc5 100644
--- a/src/arch/mips/predecoder.hh
+++ b/src/arch/mips/predecoder.hh
@@ -75,6 +75,12 @@ class Predecoder
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     //Use this to give data to the predecoder. This should be used
     //when there is control flow.
     void
diff --git a/src/arch/power/predecoder.hh b/src/arch/power/predecoder.hh
index 8b1089095..c10bc51bf 100644
--- a/src/arch/power/predecoder.hh
+++ b/src/arch/power/predecoder.hh
@@ -82,6 +82,12 @@ class Predecoder
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void
diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh
index 670c547d0..082adeb72 100644
--- a/src/arch/sparc/predecoder.hh
+++ b/src/arch/sparc/predecoder.hh
@@ -68,12 +68,19 @@ class Predecoder
     }
 
     void process() {}
+
     void
     reset()
     {
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void
diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh
index 5c67e28e1..790453b98 100644
--- a/src/arch/x86/predecoder.hh
+++ b/src/arch/x86/predecoder.hh
@@ -174,6 +174,12 @@ namespace X86ISA
             state = ResetState;
         }
 
+        void
+        reset(const ExtMachInst &old_emi)
+        {
+            reset();
+        }
+
         ThreadContext * getTC()
         {
             return tc;
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index 897807fdb..840dde9ea 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -123,7 +135,6 @@ struct TimeBufStruct {
         bool branchTaken;
         Addr mispredPC;
         TheISA::PCState nextPC;
-
         unsigned branchCount;
     };
 
@@ -151,29 +162,45 @@ struct TimeBufStruct {
     iewComm iewInfo[Impl::MaxThreads];
 
     struct commitComm {
-        bool usedROB;
-        unsigned freeROBEntries;
-        bool emptyROB;
 
+        /////////////// For Decode, IEW, Rename, Fetch ///////////
         bool squash;
         bool robSquashing;
 
-        bool branchMispredict;
-        DynInstPtr mispredictInst;
-        bool branchTaken;
-        Addr mispredPC;
-        TheISA::PCState pc;
-
+        ////////// For Fetch & IEW /////////////
         // Represents the instruction that has either been retired or
         // squashed.  Similar to having a single bus that broadcasts the
         // retired or squashed sequence number.
         InstSeqNum doneSeqNum;
 
-        //Just in case we want to do a commit/squash on a cycle
-        //(necessary for multiple ROBs?)
-        bool commitInsts;
-        InstSeqNum squashSeqNum;
+        ////////////// For Rename /////////////////
+        // Rename should re-read number of free rob entries
+        bool usedROB;
+        // Notify Rename that the ROB is empty
+        bool emptyROB;
+        // Tell Rename how many free entries it has in the ROB
+        unsigned freeROBEntries;
 
+
+        ///////////// For Fetch //////////////////
+        // Provide fetch the instruction that mispredicted, if this
+        // pointer is not-null a misprediction occured
+        DynInstPtr mispredictInst;
+        // Was the branch taken or not
+        bool branchTaken;
+        // The pc of the next instruction to execute. This is the next
+        // instruction for a branch mispredict, but the same instruction for
+        // order violation and the like
+        TheISA::PCState pc;
+
+        // Instruction that caused the a non-mispredict squash
+        DynInstPtr squashInst;
+        // If an interrupt is pending and fetch should stall
+        bool interruptPending;
+        // If the interrupt ended up being cleared before being handled
+        bool clearInterrupt;
+
+        //////////// For IEW //////////////////
         // Communication specifically to the IQ to tell the IQ that it can
         // schedule a non-speculative instruction.
         InstSeqNum nonSpecSeqNum;
@@ -182,8 +209,6 @@ struct TimeBufStruct {
         bool uncached;
         DynInstPtr uncachedLoad;
 
-        bool interruptPending;
-        bool clearInterrupt;
     };
 
     commitComm commitInfo[Impl::MaxThreads];
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 047e29f5d..ff7b53440 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -262,7 +262,8 @@ class DefaultCommit
      * instructions instead of the current instruction and doesn't
      * clean up various status bits about traps/tc writes pending.
      */
-    void squashAfter(ThreadID tid, uint64_t squash_after_seq_num);
+    void squashAfter(ThreadID tid, DynInstPtr &head_inst,
+            uint64_t squash_after_seq_num);
 
 #if FULL_SYSTEM
     /** Handles processing an interrupt. */
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 104e7fb58..8c651e203 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -541,8 +541,8 @@ DefaultCommit<Impl>::squashAll(ThreadID tid)
     // the ROB is in the process of squashing.
     toIEW->commitInfo[tid].robSquashing = true;
 
-    toIEW->commitInfo[tid].branchMispredict = false;
     toIEW->commitInfo[tid].mispredictInst = NULL;
+    toIEW->commitInfo[tid].squashInst = NULL;
 
     toIEW->commitInfo[tid].pc = pc[tid];
 }
@@ -584,7 +584,8 @@ DefaultCommit<Impl>::squashFromTC(ThreadID tid)
 
 template <class Impl>
 void
-DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
+DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
+        uint64_t squash_after_seq_num)
 {
     youngestSeqNum[tid] = squash_after_seq_num;
 
@@ -594,6 +595,7 @@ DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
     // Send back the sequence number of the squashed instruction.
     toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
 
+    toIEW->commitInfo[tid].squashInst = head_inst;
     // Send back the squash signal to tell stages that they should squash.
     toIEW->commitInfo[tid].squash = true;
 
@@ -601,7 +603,7 @@ DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
     // the ROB is in the process of squashing.
     toIEW->commitInfo[tid].robSquashing = true;
 
-    toIEW->commitInfo[tid].branchMispredict = false;
+    toIEW->commitInfo[tid].mispredictInst = NULL;
 
     toIEW->commitInfo[tid].pc = pc[tid];
     DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
@@ -801,10 +803,17 @@ DefaultCommit<Impl>::commit()
             commitStatus[tid] != TrapPending &&
             fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
 
-            DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
+            if (fromIEW->mispredictInst[tid]) {
+                DPRINTF(Commit,
+                    "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
                     tid,
-                    fromIEW->mispredPC[tid],
+                    fromIEW->mispredictInst[tid]->instAddr(),
                     fromIEW->squashedSeqNum[tid]);
+            } else {
+                DPRINTF(Commit,
+                    "[tid:%i]: Squashing due to order violation [sn:%i]\n",
+                    tid, fromIEW->squashedSeqNum[tid]);
+            }
 
             DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
                     tid,
@@ -835,18 +844,15 @@ DefaultCommit<Impl>::commit()
             // the ROB is in the process of squashing.
             toIEW->commitInfo[tid].robSquashing = true;
 
-            toIEW->commitInfo[tid].branchMispredict =
-                fromIEW->branchMispredict[tid];
             toIEW->commitInfo[tid].mispredictInst =
                 fromIEW->mispredictInst[tid];
             toIEW->commitInfo[tid].branchTaken =
                 fromIEW->branchTaken[tid];
+            toIEW->commitInfo[tid].squashInst = NULL;
 
             toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
 
-            toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
-
-            if (toIEW->commitInfo[tid].branchMispredict) {
+            if (toIEW->commitInfo[tid].mispredictInst) {
                 ++branchMispredicts;
             }
         }
@@ -988,7 +994,7 @@ DefaultCommit<Impl>::commitInsts()
                 // If this is an instruction that doesn't play nicely with
                 // others squash everything and restart fetch
                 if (head_inst->isSquashAfter())
-                    squashAfter(tid, head_inst->seqNum);
+                    squashAfter(tid, head_inst, head_inst->seqNum);
 
                 int count = 0;
                 Addr oldpc;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2d3bc3f72..4088f2399 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -808,8 +808,9 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
     }
 
     // Squash Throughout Pipeline
-    InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
-    fetch.squash(0, squash_seq_num, tid);
+    DynInstPtr inst = commit.rob->readHeadInst(tid);
+    InstSeqNum squash_seq_num = inst->seqNum;
+    fetch.squash(0, squash_seq_num, inst, tid);
     decode.squash(tid);
     rename.squash(squash_seq_num, tid);
     iew.squash(tid);
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index c51658104..4a4ac0902 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -312,8 +312,8 @@ class DefaultFetch
      * remove any instructions that are not in the ROB. The source of this
      * squash should be the commit stage.
      */
-    void squash(const TheISA::PCState &newPC,
-                const InstSeqNum &seq_num, ThreadID tid);
+    void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
+                DynInstPtr &squashInst, ThreadID tid);
 
     /** Ticks the fetch stage, processing all inputs signals and fetching
      * as many instructions as possible.
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index a2f2b4f8a..6c1ac456d 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -112,6 +112,9 @@ DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
 {
     DPRINTF(Fetch, "Received timing\n");
     if (pkt->isResponse()) {
+        // We shouldn't ever get a block in ownership state
+        assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
+
         fetch->processCacheCompletion(pkt);
     }
     //else Snooped a coherence request, just return
@@ -812,11 +815,14 @@ DefaultFetch<Impl>::updateFetchStatus()
 template <class Impl>
 void
 DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
-                           const InstSeqNum &seq_num, ThreadID tid)
+                           const InstSeqNum &seq_num, DynInstPtr &squashInst,
+                           ThreadID tid)
 {
     DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
 
     doSquash(newPC, tid);
+    if (squashInst)
+        predecoder.reset(squashInst->staticInst->machInst);
 
     // Tell the CPU to remove any instructions that are not in the ROB.
     cpu->removeInstsNotInROB(tid);
@@ -931,15 +937,12 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
         // In any case, squash.
         squash(fromCommit->commitInfo[tid].pc,
                fromCommit->commitInfo[tid].doneSeqNum,
-               tid);
+               fromCommit->commitInfo[tid].squashInst, tid);
 
         // If it was a branch mispredict on a control instruction, update the
         // branch predictor with that instruction, otherwise just kill the
         // invalid state we generated in after sequence number
-        assert(!fromCommit->commitInfo[tid].branchMispredict ||
-                fromCommit->commitInfo[tid].mispredictInst);
-
-        if (fromCommit->commitInfo[tid].branchMispredict &&
+        if (fromCommit->commitInfo[tid].mispredictInst &&
             fromCommit->commitInfo[tid].mispredictInst->isControl()) {
             branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
                               fromCommit->commitInfo[tid].pc,
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index dff287ff5..8bf3c56f4 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -456,8 +456,6 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
             inst->seqNum < toCommit->squashedSeqNum[tid]) {
         toCommit->squash[tid] = true;
         toCommit->squashedSeqNum[tid] = inst->seqNum;
-        toCommit->mispredPC[tid] = inst->instAddr();
-        toCommit->branchMispredict[tid] = true;
         toCommit->branchTaken[tid] = inst->pcState().branching();
 
         TheISA::PCState pc = inst->pcState();
@@ -486,7 +484,7 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
         TheISA::PCState pc = inst->pcState();
         TheISA::advancePC(pc, inst->staticInst);
         toCommit->pc[tid] = pc;
-        toCommit->branchMispredict[tid] = false;
+        toCommit->mispredictInst[tid] = NULL;
 
         toCommit->includeSquashInst[tid] = false;
 
@@ -506,7 +504,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
 
         toCommit->squashedSeqNum[tid] = inst->seqNum;
         toCommit->pc[tid] = inst->pcState();
-        toCommit->branchMispredict[tid] = false;
+        toCommit->mispredictInst[tid] = NULL;
 
         // Must include the broadcasted SN in the squash.
         toCommit->includeSquashInst[tid] = true;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index b5d337935..1a4e686a3 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1103,7 +1103,9 @@ LSQUnit<Impl>::recvRetry()
                 dynamic_cast<LSQSenderState *>(retryPkt->senderState);
 
             // Don't finish the store unless this is the last packet.
-            if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) {
+            if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
+                    state->pendingPacket == retryPkt) {
+                state->pktToSend = false;
                 storePostSend(retryPkt);
             }
             retryPkt = NULL;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 27635d3ce..6aa0eb64e 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -641,6 +641,9 @@ AtomicSimpleCPU::tick()
             checkForInterrupts();
 
         checkPcEventQueue();
+        // We must have just got suspended by a PC event
+        if (_status == Idle)
+            return;
 
         Fault fault = NoFault;
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 632e83356..aca48e5d4 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -714,6 +714,10 @@ TimingSimpleCPU::fetch()
 
     checkPcEventQueue();
 
+    // We must have just got suspended by a PC event
+    if (_status == Idle)
+        return;
+
     TheISA::PCState pcState = thread->pcState();
     bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
 
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 933496864..d07b322df 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -267,6 +267,7 @@ class StaticInstBase : public RefCounted
 
     void setLastMicroop() { flags[IsLastMicroop] = true; }
     void setDelayedCommit() { flags[IsDelayedCommit] = true; }
+    void setFlag(Flags f) { flags[f] = true; }
 
     /// Operation class.  Used to select appropriate function unit in issue.
     OpClass opClass()     const { return _opClass; }
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index be97bc4ad..ffe8fdf06 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -139,6 +139,9 @@ DmaPort::recvTiming(PacketPtr pkt)
         assert(pendingCount >= 0);
         assert(state);
 
+        // We shouldn't ever get a block in ownership state
+        assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
+
         state->numBytes += pkt->req->getSize();
         assert(state->totBytes >= state->numBytes);
         if (state->totBytes == state->numBytes) {
diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc
index f619dd11b..75c2b6f7f 100644
--- a/src/kern/linux/events.cc
+++ b/src/kern/linux/events.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -32,11 +44,13 @@
 #include <sstream>
 
 #include "base/trace.hh"
+#include "arch/utility.hh"
 #include "cpu/thread_context.hh"
 #include "kern/linux/events.hh"
 #include "kern/linux/printk.hh"
 #include "kern/system_events.hh"
 #include "sim/arguments.hh"
+#include "sim/pseudo_inst.hh"
 #include "sim/system.hh"
 
 namespace Linux {
@@ -54,4 +68,27 @@ DebugPrintkEvent::process(ThreadContext *tc)
     SkipFuncEvent::process(tc);
 }
 
+void
+UDelayEvent::process(ThreadContext *tc)
+{
+    int arg_num  = 0;
+
+    // Get the time in native size
+    uint64_t time = TheISA::getArgument(tc, arg_num,  (uint16_t)-1, false);
+
+    // convert parameter to ns
+    if (argDivToNs)
+        time /= argDivToNs;
+
+    time *= argMultToNs;
+
+    // Convert ns to ticks
+    time *= SimClock::Int::ns;
+
+    SkipFuncEvent::process(tc);
+
+    PseudoInst::quiesceNs(tc, time);
+}
+
+
 } // namespace linux
diff --git a/src/kern/linux/events.hh b/src/kern/linux/events.hh
index e36a72dde..3f5f2526f 100644
--- a/src/kern/linux/events.hh
+++ b/src/kern/linux/events.hh
@@ -44,6 +44,33 @@ class DebugPrintkEvent : public SkipFuncEvent
     virtual void process(ThreadContext *xc);
 };
 
+/** A class to skip udelay() and related calls in the kernel.
+ * This class has two additional parameters that take the argument to udelay and
+ * manipulated it to come up with ns and eventually ticks to quiesce for.
+ * See descriptions of argDivToNs and argMultToNs below.
+ */
+class UDelayEvent : public SkipFuncEvent
+{
+  private:
+    /** value to divide arg by to create ns. This is present beacues the linux
+     * kernel code sometime precomputes the first multiply that is done in
+     * udelay() if the parameter is a constant. We need to undo it so here is
+     * how. */
+    uint64_t argDivToNs;
+
+    /** value to multiple arg by to create ns. Nominally, this is 1000 to
+     * convert us to ns, but since linux can do some preprocessing of constant
+     * values something else might be required. */
+    uint64_t argMultToNs;
+
+  public:
+    UDelayEvent(PCEventQueue *q, const std::string &desc, Addr addr,
+            uint64_t mult, uint64_t div)
+        : SkipFuncEvent(q, desc, addr), argDivToNs(div), argMultToNs(mult) {}
+    virtual void process(ThreadContext *xc);
+};
+
+
 }
 
 #endif
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index dffac2234..5c7ae5274 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -48,6 +48,7 @@ class BaseCache(MemObject):
     size = Param.MemorySize("capacity in bytes")
     forward_snoops = Param.Bool(True,
         "forward snoops from mem side to cpu side")
+    is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)")
     subblock_size = Param.Int(0,
         "Size of subblock in IIC used for compression")
     tgts_per_mshr = Param.Int("max number of accesses per MSHR")
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 9166e1a09..b7e331d54 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -58,6 +58,7 @@ BaseCache::BaseCache(const Params *p)
       hitLatency(p->latency),
       numTarget(p->tgts_per_mshr),
       forwardSnoops(p->forward_snoops),
+      isTopLevel(p->is_top_level),
       blocked(0),
       noTargetMSHR(NULL),
       missCount(p->max_miss_count),
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index e8a644296..28ddf5054 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -194,6 +194,11 @@ class BaseCache : public MemObject
     /** Do we forward snoops from mem side port through to cpu side port? */
     bool forwardSnoops;
 
+    /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
+     * never try to forward ownership and similar optimizations to the cpu
+     * side */
+    bool isTopLevel;
+
     /**
      * Bit vector of the blocking reasons for the access path.
      * @sa #BlockedCause
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index e4e4a3c92..0b2b273f9 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -216,7 +216,7 @@ Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
                 
                 if (blk->isDirty()) {
                     // special considerations if we're owner:
-                    if (!deferred_response) {
+                    if (!deferred_response && !isTopLevel) {
                         // if we are responding immediately and can
                         // signal that we're transferring ownership
                         // along with exclusivity, do so
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index f3b10f6d2..bcff2f5c1 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -85,6 +97,28 @@ quiesce(ThreadContext *tc)
         tc->getKernelStats()->quiesce();
 }
 
+void
+quiesceSkip(ThreadContext *tc)
+{
+    BaseCPU *cpu = tc->getCpuPtr();
+
+    if (!cpu->params()->do_quiesce)
+        return;
+
+    EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
+
+    Tick resume = curTick() + 1;
+
+    cpu->reschedule(quiesceEvent, resume, true);
+
+    DPRINTF(Quiesce, "%s: quiesceSkip() until %d\n",
+            cpu->name(), resume);
+
+    tc->suspend();
+    if (tc->getKernelStats())
+        tc->getKernelStats()->quiesce();
+}
+
 void
 quiesceNs(ThreadContext *tc, uint64_t ns)
 {
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index 296b1556b..aec3b5d8a 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -45,6 +45,7 @@ extern bool doQuiesce;
 #if FULL_SYSTEM
 void arm(ThreadContext *tc);
 void quiesce(ThreadContext *tc);
+void quiesceSkip(ThreadContext *tc);
 void quiesceNs(ThreadContext *tc, uint64_t ns);
 void quiesceCycles(ThreadContext *tc, uint64_t cycles);
 uint64_t quiesceTime(ThreadContext *tc);
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index e0469744e..506b22fdf 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -97,6 +97,18 @@ ignoreFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
 }
 
 
+SyscallReturn
+ignoreWarnOnceFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
+           ThreadContext *tc)
+{
+    int index = 0;
+    warn_once("ignoring syscall %s(%d, %d, ...)", desc->name,
+         process->getSyscallArg(tc, index), process->getSyscallArg(tc, index));
+
+    return 0;
+}
+
+
 SyscallReturn
 exitFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
          ThreadContext *tc)
@@ -802,6 +814,8 @@ cloneFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
 
             for (int y = 8; y < 32; y++)
                 ctc->setIntReg(y, tc->readIntReg(y));
+        #elif THE_ISA == ARM_ISA
+            TheISA::copyRegs(tc, ctc);
         #else
             fatal("sys_clone is not implemented for this ISA\n");
         #endif
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 1dc51ad56..5091c275d 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -187,6 +187,8 @@ SyscallReturn unimplementedFunc(SyscallDesc *desc, int num,
 /// trace flag is enabled.  Return success to the target program.
 SyscallReturn ignoreFunc(SyscallDesc *desc, int num,
                          LiveProcess *p, ThreadContext *tc);
+SyscallReturn ignoreWarnOnceFunc(SyscallDesc *desc, int num,
+                         LiveProcess *p, ThreadContext *tc);
 
 /// Target exit() handler: terminate current context.
 SyscallReturn exitFunc(SyscallDesc *desc, int num,
diff --git a/tests/SConscript b/tests/SConscript
index 2e4d2d19a..00ceebdec 100644
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -276,7 +276,8 @@ if env['FULL_SYSTEM']:
                     't1000-simple-timing']
     if env['TARGET_ISA'] == 'arm':
         configs += ['realview-simple-atomic',
-                    'realview-simple-timing']
+                    'realview-simple-timing',
+                    'realview-o3']
     if env['TARGET_ISA'] == 'x86':
         configs += ['pc-simple-atomic',
                     'pc-simple-timing']
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index af58cafa5..ddf37b5ec 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -37,8 +37,12 @@ class MyCache(BaseCache):
     mshrs = 10
     tgts_per_mshr = 5
 
+class MyL1Cache(MyCache):
+    is_top_level = True
+
 cpu = InOrderCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
                               MyCache(size = '2MB', latency='10ns'))
 
 cpu.clock = '2GHz'
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index d75bd3d8c..f62381473 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -38,6 +38,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 12
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 5c770cdbc..35811282c 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -39,6 +39,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index a4c054122..d4a69d94a 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -37,8 +37,12 @@ class MyCache(BaseCache):
     mshrs = 10
     tgts_per_mshr = 5
 
+class MyL1Cache(MyCache):
+    is_top_level = True
+
 cpu = DerivO3CPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
                               MyCache(size = '2MB'))
 cpu.clock = '2GHz'
 
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index 382899eb5..1c35ff2d9 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -43,6 +43,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -65,6 +66,7 @@ class PageTableWalkerCache(BaseCache):
     mshrs = 10
     size = '1kB'
     tgts_per_mshr = 12
+    is_top_level = True
 
 # ---------------------
 # I/O Cache
@@ -78,6 +80,7 @@ class IOCache(BaseCache):
     tgts_per_mshr = 12
     addr_range = AddrRange(0, size=mem_size)
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index 7452e2542..9c9f4aeca 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -44,6 +44,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
new file mode 100644
index 000000000..2d805fe0a
--- /dev/null
+++ b/tests/configs/realview-o3.py
@@ -0,0 +1,99 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+    is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    addr_range=AddrRange(0, size='128MB')
+    forward_snoops = False
+
+#cpu
+cpu = DerivO3CPU(cpu_id=0)
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index ab6d612d4..7340be7a4 100644
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -40,6 +40,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 53b6ab2b2..83b643c52 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -41,6 +41,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index d88a9b395..4db741b8a 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -38,6 +38,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index f5793b282..6f4090ec2 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -38,6 +38,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 739e11e55..bc9d016c5 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -36,8 +36,12 @@ class MyCache(BaseCache):
     mshrs = 10
     tgts_per_mshr = 5
 
+class MyL1Cache(MyCache):
+    is_top_level = True
+
 cpu = TimingSimpleCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
                               MyCache(size = '2MB', latency='10ns'))
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index 7744560f9..125e228a7 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -41,6 +41,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -65,6 +66,7 @@ class IOCache(BaseCache):
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index fd2d66431..13212d5d9 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -41,6 +41,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -65,6 +66,7 @@ class IOCache(BaseCache):
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpu = DerivO3CPU(cpu_id=0)
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 9d3dbaa91..2e56ce851 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -40,6 +40,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -64,6 +65,7 @@ class IOCache(BaseCache):
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index cbacf1995..3c1981464 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -40,6 +40,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -64,6 +65,7 @@ class IOCache(BaseCache):
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index f0105461d..747cdac18 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -40,6 +40,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -64,6 +65,7 @@ class IOCache(BaseCache):
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 9a262b3b2..110e6ee74 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -41,6 +41,7 @@ class L1(BaseCache):
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -65,6 +66,7 @@ class IOCache(BaseCache):
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
index b2393d69d..d33b7fe91 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
@@ -115,6 +115,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -413,6 +414,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -448,6 +450,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -493,7 +496,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
index 3549187ab..7c98f6fbe 100755
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 21 2011 14:34:16
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 14:34:24
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:10:13
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
@@ -43,4 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 216988269500 because target called exit()
+Exiting @ tick 212151683000 because target called exit()
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
index 70c39bd1c..c117cacbc 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -1,130 +1,142 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  84615                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 256696                       # Number of bytes of host memory used
-host_seconds                                  7097.77                       # Real time elapsed on the host
-host_tick_rate                               30571310                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 130169                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 255152                       # Number of bytes of host memory used
+host_seconds                                  4627.51                       # Real time elapsed on the host
+host_tick_rate                               45845717                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   600581343                       # Number of instructions simulated
-sim_seconds                                  0.216988                       # Number of seconds simulated
-sim_ticks                                216988269500                       # Number of ticks simulated
+sim_insts                                   602359950                       # Number of instructions simulated
+sim_seconds                                  0.212152                       # Number of seconds simulated
+sim_ticks                                212151683000                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 80605280                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              86769998                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            3926724                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           92457743                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 92457743                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               70067581                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           7237688                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                 77353146                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              83702663                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                1593                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect            3826409                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           84369915                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 91120892                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  1482138                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches               70826872                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events           7259535                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    415627277                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.445000                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.803105                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples    408127750                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.475910                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.811076                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    151327612     36.41%     36.41% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    131463127     31.63%     68.04% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     59591085     14.34%     82.38% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     19300079      4.64%     87.02% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     16801337      4.04%     91.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     14774918      3.55%     94.62% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     12865599      3.10%     97.71% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      2265832      0.55%     98.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      7237688      1.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0    143768271     35.23%     35.23% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1    130628056     32.01%     67.23% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2     60243177     14.76%     81.99% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3     18962619      4.65%     86.64% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4     17622510      4.32%     90.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5     14296756      3.50%     94.46% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6     13120148      3.21%     97.68% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7      2226678      0.55%     98.22% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8      7259535      1.78%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    415627277                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 600581394                       # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total    408127750                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                 602360001                       # Number of instructions committed
 system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             531746837                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 148953025                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  219174038                       # Number of memory references committed
+system.cpu.commit.COM:function_calls           997573                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             533522759                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                 148952624                       # Number of loads committed
+system.cpu.commit.COM:membars                    1328                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                  219173667                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts           4754311                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts      600581394                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls            3642                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       121349980                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                   600581343                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             600581343                       # Number of Instructions Simulated
-system.cpu.cpi                               0.722594                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.722594                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses          140357692                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13126.895414                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7797.393105                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              140121332                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     3102673000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.001684                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               236360                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits             40725                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   1525443000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001394                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          195635                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          69418858                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 17787.364223                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10360.276216                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              67933393                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   26422506996                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.021399                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1485465                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1237601                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   2567939504                       # number of WriteReq MSHR miss cycles
+system.cpu.commit.branchMispredicts           3887306                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts      602360001                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls            6327                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts       105586113                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                   602359950                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             602359950                       # Number of Instructions Simulated
+system.cpu.cpi                               0.704402                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.704402                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses         1392                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 10807.692308                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits             1379                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency       140500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.009339                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses             13                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits           13                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.ReadReq_accesses          139573989                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 13187.861272                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7875.361074                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              139338017                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency     3111966000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.001691                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               235972                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits             40375                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency   1540397000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001401                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses          195597                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses          1357                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits              1357                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses          69417531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 19453.548688                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10358.949737                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              68088613                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   25852171016                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.019144                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1328918                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          1081042                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   2567735025                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.003571                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         247864                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4386.427788                       # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_mshr_misses         247876                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  4395.291476                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 469.123191                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs              2188                       # number of cycles access was blocked
+system.cpu.dcache.avg_refs                 467.742670                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs              2182                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs      9597504                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs      9590526                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           209776550                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 17147.607914                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  9229.744608                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               208054725                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     29525179996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.008208                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1721825                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            1278326                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   4093382504                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.002114                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           443499                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses           208991520                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 18508.736727                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  9263.544849                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               207426630                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     28964137016                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.007488                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1564890                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            1121417                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency   4108132025                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.002122                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           443473                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.999739                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4094.932523                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          209776550                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 17147.607914                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  9229.744608                       # average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0           4094.932917                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          208991520                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 18508.736727                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  9263.544849                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              208054725                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    29525179996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.008208                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1721825                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           1278326                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   4093382504                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.002114                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          443499                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits              207426630                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    28964137016                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.007488                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1564890                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           1121417                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency   4108132025                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.002122                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          443473                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 439401                       # number of replacements
-system.cpu.dcache.sampled_refs                 443497                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                 439373                       # number of replacements
+system.cpu.dcache.sampled_refs                 443469                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.932523                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                208054728                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               90723000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   394050                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       84141897                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts       763381678                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         172755507                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          145178933                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        17467706                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles       13550939                       # Number of cycles decode is unblocking
+system.cpu.dcache.tagsinuse               4094.932917                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                207429374                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               89412000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   394062                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       84592597                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred           1269                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved       6208796                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts       740088879                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles         168706146                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles          141255851                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles        15304229                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts           4703                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles       13573155                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -146,242 +158,242 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                    92457743                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  75163466                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     161721841                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                803288                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      727645114                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                 2139                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                 5447051                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.213048                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           75163466                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           80605280                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.676692                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          433094982                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.793896                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.871529                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                    91120892                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                  73409824                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                     157341177                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                853332                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                      706778220                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                 2056                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                 4584124                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.214754                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles           73409824                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches           78835284                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.665738                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples          423431978                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.775923                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.853239                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                271374463     62.66%     62.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 26620223      6.15%     68.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 18536414      4.28%     73.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 23464508      5.42%     78.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 11465886      2.65%     81.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 12676535      2.93%     84.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5122176      1.18%     85.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  7816549      1.80%     87.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 56018228     12.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                266090925     62.84%     62.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 25382675      5.99%     68.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 18707202      4.42%     73.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 23120734      5.46%     78.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 11518747      2.72%     81.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 12813304      3.03%     84.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  4581816      1.08%     85.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  7541689      1.78%     87.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 53674886     12.68%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            433094982                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            423431978                       # Number of instructions fetched each cycle (Total)
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses           75163466                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35392.896175                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34027.443106                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               75162551                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       32384500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000012                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  915                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               168                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     25418500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_accesses           73409824                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35098.824786                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34224.447514                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               73408888                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       32852500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000013                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                  936                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               212                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency     24778500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             747                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses             724                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               100889.330201                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               101956.788889                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            75163466                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35392.896175                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34027.443106                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                75162551                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        32384500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000012                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   915                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                168                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     25418500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_accesses            73409824                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35098.824786                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34224.447514                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                73408888                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        32852500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000013                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                   936                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                212                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency     24778500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000010                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              747                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses              724                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.323287                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            662.091546                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses           75163466                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35392.896175                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34027.443106                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.307623                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            630.012478                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses           73409824                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35098.824786                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34224.447514                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               75162551                       # number of overall hits
-system.cpu.icache.overall_miss_latency       32384500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000012                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  915                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               168                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     25418500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_hits               73408888                       # number of overall hits
+system.cpu.icache.overall_miss_latency       32852500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000013                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                  936                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               212                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency     24778500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000010                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             747                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses             724                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                     23                       # number of replacements
-system.cpu.icache.sampled_refs                    745                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                     33                       # number of replacements
+system.cpu.icache.sampled_refs                    720                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                662.091546                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 75162551                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                630.012478                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 73408888                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          881558                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 74261585                       # Number of branches executed
-system.cpu.iew.EXEC:nop                         62913                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.487680                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    240772759                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   74373435                       # Number of stores executed
+system.cpu.idleCycles                          871389                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                 73892971                       # Number of branches executed
+system.cpu.iew.EXEC:nop                         61798                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.506493                       # Inst execution rate
+system.cpu.iew.EXEC:refs                    238982736                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                   73900874                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 747728792                       # num instructions consuming a value
-system.cpu.iew.WB:count                     638494059                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.593986                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                 738975685                       # num instructions consuming a value
+system.cpu.iew.WB:count                     633750064                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.595052                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 444140095                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.471264                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      640207091                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts              5262481                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                  938808                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             184696679                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts               3886                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           3056896                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             88578804                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           721929028                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             166399324                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7744349                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             645618045                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  15544                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                 439728869                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.493625                       # insts written-back per cycle
+system.cpu.iew.WB:sent                      634774515                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts              4294677                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                  946102                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             181732576                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts               5902                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts           2934920                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts             84682953                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts           707943366                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts             165081862                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           6085968                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             639209952                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                  15519                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 10568                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               17467706                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                 68840                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                  2353                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles               15304229                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                 50818                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked         8986                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads        24659910                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses        40290                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked         8944                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads        24296735                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses        57403                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation       927620                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads        15164                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads     35743653                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores     18357791                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         927620                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      1455468                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        3807013                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads               1741672216                       # number of integer regfile reads
-system.cpu.int_regfile_writes               500762058                       # number of integer regfile writes
-system.cpu.ipc                               1.383903                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.383903                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation       930118                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads        15159                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads     32779951                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores     14461910                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents         930118                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       636408                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect        3658269                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               1727320002                       # number of integer regfile reads
+system.cpu.int_regfile_writes               496802288                       # number of integer regfile writes
+system.cpu.ipc                               1.419645                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.419645                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       408522313     62.53%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult           6689      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            3      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      168909835     25.85%     88.38% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      75923554     11.62%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu       402470959     62.37%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult           6564      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            3      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     62.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead      167645097     25.98%     88.35% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite      75173297     11.65%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        653362394                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               7689776                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.011770                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total        645295920                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt               7755028                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.012018                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu            110224      1.43%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      1.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          7362915     95.75%     97.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          216637      2.82%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu            198697      2.56%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      2.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead          7348141     94.75%     97.32% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite          208190      2.68%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    433094982                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.508589                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.485286                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples    423431978                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.523966                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.473546                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     131707315     30.41%     30.41% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     125173244     28.90%     59.31% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      78416793     18.11%     77.42% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      46415103     10.72%     88.14% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      32898080      7.60%     95.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      12956560      2.99%     98.72% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       3885385      0.90%     99.62% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        717191      0.17%     99.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        925311      0.21%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0     124767045     29.47%     29.47% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1     123576315     29.18%     58.65% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2      78343969     18.50%     77.15% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3      46750040     11.04%     88.19% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4      32770284      7.74%     95.93% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5      12193598      2.88%     98.81% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6       3344839      0.79%     99.60% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7        823717      0.19%     99.80% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8        862171      0.20%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    433094982                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.505525                       # Inst issue rate
+system.cpu.iq.ISSUE:issued_per_cycle::total    423431978                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.520836                       # Inst issue rate
 system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses              661052150                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads         1748135502                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    638494043                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         843674084                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  721862229                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 653362394                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                3886                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       120901183                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            625992                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved            244                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    239953447                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.int_alu_accesses              653050928                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         1722505687                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    633750048                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         814020305                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                  707874308                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                 645295920                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded                7260                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined       105229644                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued            726877                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved            933                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined    212022368                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -403,114 +415,114 @@ system.cpu.itb.read_misses                          0                       # DT
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          247865                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34472.344792                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.636053                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              189395                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   2015598000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.235895                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             58470                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1828569500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235895                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        58470                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            196377                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34258.354481                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31117.674945                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                163670                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1120488000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.166552                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               32707                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               11                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1017423500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.166496                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          32696                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses          247874                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.539920                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31261.130694                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits              189432                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   2008274000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.235773                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             58442                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1826963000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235773                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        58442                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses            196316                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34255.152982                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31104.089447                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                163665                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1118465000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.166319                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               32651                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits                6                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1015393000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.166288                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          32645                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses              3                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        32000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_hits                  2                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_miss_rate      0.333333                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency        32000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.333333                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          394050                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              394050                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  6190.332326                       # average number of cycles each access was blocked
+system.cpu.l2cache.Writeback_accesses          394062                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              394062                       # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  5824.362606                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  4.731748                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs              331                       # number of cycles access was blocked
+system.cpu.l2cache.avg_refs                  4.737794                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs              353                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs      2049000                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs      2056000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             444242                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34395.582219                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.701775                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 353065                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     3136086000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.205242                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                91177                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                11                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   2845993000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.205217                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           91166                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_accesses             444190                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34324.690152                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.848112                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                 353097                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     3126739000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.205077                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                91093                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                 6                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency   2842356000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.205063                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           91087                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.056947                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.488639                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          1866.034580                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16011.711774                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses            444242                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34395.582219                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.701775                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.056232                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.489259                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1842.604757                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16032.025879                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses            444190                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34324.690152                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.848112                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                353065                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    3136086000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.205242                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               91177                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               11                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   2845993000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.205217                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          91166                       # number of overall MSHR misses
+system.cpu.l2cache.overall_hits                353097                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    3126739000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.205077                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               91093                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits                6                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency   2842356000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.205063                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          91087                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 72987                       # number of replacements
-system.cpu.l2cache.sampled_refs                 88484                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                 72891                       # number of replacements
+system.cpu.l2cache.sampled_refs                 88396                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             17877.746353                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  418684                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             17874.630636                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  418802                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   58152                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          56143840                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         33466009                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            184696679                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            88578804                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               960863165                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                   9367                       # number of misc regfile writes
-system.cpu.numCycles                        433976540                       # number of cpu cycles simulated
+system.cpu.l2cache.writebacks                   58120                       # number of writebacks
+system.cpu.memDep0.conflictingLoads          59394757                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         28028248                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            181732576                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            84682953                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               939363465                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                   9368                       # number of misc regfile writes
+system.cpu.numCycles                        424303367                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         12394449                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      469246940                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents        63310870                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         190431449                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        3181742                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents              1                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     2146129409                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       749361548                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    579635255                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          140764920                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        17467706                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       71980154                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         110388312                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:BlockCycles         12681660                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps      471025546                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents        63633162                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles         186161185                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        2954668                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups     2083466922                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts       728669573                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands    566468470                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles          137330990                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles        15304229                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles       71846492                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps          95442921                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.RENAME:fp_rename_lookups           96                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   2146129313                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles        56304                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts         3959                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts          128598458                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts         3953                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                   1130320351                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1461345715                       # The number of ROB writes
-system.cpu.timesIdled                           36569                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:int_rename_lookups   2083466826                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles       107422                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts         6263                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts          128424972                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts         6268                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   1108813717                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1431196844                       # The number of ROB writes
+system.cpu.timesIdled                           36620                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
index 17d38a039..e931d99dc 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
@@ -66,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
index f425b3c91..cf49f4125 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:00:03
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:23:27
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -43,4 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 300302141500 because target called exit()
+Exiting @ tick 301191370000 because target called exit()
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
index fb68d0899..0eb8d8824 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1026292                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 229344                       # Number of bytes of host memory used
-host_seconds                                   585.20                       # Real time elapsed on the host
-host_tick_rate                              513165203                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1838558                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 246240                       # Number of bytes of host memory used
+host_seconds                                   327.63                       # Real time elapsed on the host
+host_tick_rate                              919312999                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   600581394                       # Number of instructions simulated
-sim_seconds                                  0.300302                       # Number of seconds simulated
-sim_ticks                                300302141500                       # Number of ticks simulated
+sim_insts                                   602359851                       # Number of instructions simulated
+sim_seconds                                  0.301191                       # Number of seconds simulated
+sim_ticks                                301191370000                       # Number of ticks simulated
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -52,24 +52,24 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        600604284                       # number of cpu cycles simulated
+system.cpu.numCycles                        602382741                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  600604284                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                  602382741                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     67016068                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_fp_insts                            16                       # number of float instructions
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     1993596                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        600581394                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             531746837                       # Number of integer alu accesses
-system.cpu.num_int_insts                    531746837                       # number of integer instructions
-system.cpu.num_int_register_reads          1690709529                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          456307392                       # number of times the integer registers were written
-system.cpu.num_load_insts                   148953025                       # Number of load instructions
-system.cpu.num_mem_refs                     219174038                       # number of memory refs
+system.cpu.num_insts                        602359851                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             533522639                       # Number of integer alu accesses
+system.cpu.num_int_insts                    533522639                       # number of integer instructions
+system.cpu.num_int_register_reads          1694262461                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          458085654                       # number of times the integer registers were written
+system.cpu.num_load_insts                   148952594                       # Number of load instructions
+system.cpu.num_mem_refs                     219173607                       # number of memory refs
 system.cpu.num_store_insts                   70221013                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
 
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
index de769cd56..cd3bf6aae 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
@@ -166,7 +169,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
index 70559ac7d..3d2816f3e 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:25
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:13:11
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -43,4 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 796759936000 because target called exit()
+Exiting @ tick 796762926000 because target called exit()
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
index 2b5fb88ae..bc2095464 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -1,27 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 452045                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 237056                       # Number of bytes of host memory used
-host_seconds                                  1324.25                       # Real time elapsed on the host
-host_tick_rate                              601669731                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 732997                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 253960                       # Number of bytes of host memory used
+host_seconds                                   819.10                       # Real time elapsed on the host
+host_tick_rate                              972728993                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   598619824                       # Number of instructions simulated
-sim_seconds                                  0.796760                       # Number of seconds simulated
-sim_ticks                                796759936000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses          147793610                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 20842.812219                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.812219                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              147603767                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     3956862000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.001285                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               189843                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3387333000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001285                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          189843                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          69418858                       # number of WriteReq accesses(hits+misses)
+sim_insts                                   600398281                       # Number of instructions simulated
+sim_seconds                                  0.796763                       # Number of seconds simulated
+sim_ticks                                796762926000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses         1327                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits             1327                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses          147791852                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              147602036                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency     3956274000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.001284                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               189816                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   3386826000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001284                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses          189816                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses          1327                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits              1327                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses          69417531                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              69171110                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits              69169783                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency    5923414000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.003569                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses              247748                       # number of WriteReq misses
@@ -30,49 +34,49 @@ system.cpu.dcache.WriteReq_mshr_miss_rate     0.003569                       # m
 system.cpu.dcache.WriteReq_mshr_misses         247748                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 495.382394                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                 495.412038                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           217212468                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22578.791611                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19578.791611                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               216774877                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency      9880276000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.002015                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                437591                       # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses           217209383                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 22578.841038                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               216771819                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      9879688000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.002014                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                437564                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   8567503000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.002015                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           437591                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency   8566996000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.002014                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           437564                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.999566                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4094.223177                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          217212468                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22578.791611                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19578.791611                       # average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0           4094.222434                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          217209383                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 22578.841038                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              216774877                       # number of overall hits
-system.cpu.dcache.overall_miss_latency     9880276000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.002015                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               437591                       # number of overall misses
+system.cpu.dcache.overall_hits              216771819                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     9879688000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.002014                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               437564                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   8567503000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.002015                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          437591                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency   8566996000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.002014                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          437564                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 433495                       # number of replacements
-system.cpu.dcache.sampled_refs                 437591                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                 433468                       # number of replacements
+system.cpu.dcache.sampled_refs                 437564                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.223177                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                216774877                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              537003000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   392389                       # number of writebacks
+system.cpu.dcache.tagsinuse               4094.222434                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                216774473                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              537031000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   392392                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -94,10 +98,10 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses          570070553                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses          570074535                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 54236.391913                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              570069910                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits              570073892                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       34874000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  643                       # number of ReadReq misses
@@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # ms
 system.cpu.icache.ReadReq_mshr_misses             643                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               886578.398134                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               886584.590980                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           570070553                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses           570074535                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 54236.391913                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               570069910                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits               570073892                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        34874000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   643                       # number of demand (read+write) misses
@@ -127,12 +131,12 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.occ_%::0                   0.282094                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            577.728453                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses          570070553                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0            577.728532                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses          570074535                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 54236.391913                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              570069910                       # number of overall hits
+system.cpu.icache.overall_hits              570073892                       # number of overall hits
 system.cpu.icache.overall_miss_latency       34874000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  643                       # number of overall misses
@@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                     12                       # number of replacements
 system.cpu.icache.sampled_refs                    643                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                577.728453                       # Cycle average of tags in use
-system.cpu.icache.total_refs                570069910                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                577.728532                       # Cycle average of tags in use
+system.cpu.icache.total_refs                570073892                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses             58451                       # nu
 system.cpu.l2cache.ReadExReq_mshr_miss_latency   2338040000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235929                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses        58451                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            190486                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses            190459                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                158940                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1640392000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.165608                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               31546                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1261840000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165608                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          31546                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          392389                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              392389                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                158918                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1640132000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.165605                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               31541                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1261640000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165605                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          31541                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          392392                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              392392                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  4.718118                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.718237                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             438234                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses             438207                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 348237                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     4679844000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.205363                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                89997                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 348215                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     4679584000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.205364                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                89992                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   3599880000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.205363                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           89997                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   3599680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.205364                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           89992                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.053819                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.492601                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          1763.554655                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16141.554862                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses            438234                       # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::0                  0.053777                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.492610                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1762.179345                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16141.835335                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses            438207                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                348237                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    4679844000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.205363                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               89997                       # number of overall misses
+system.cpu.l2cache.overall_hits                348215                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    4679584000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.205364                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               89992                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   3599880000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.205363                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          89997                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   3599680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.205364                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          89992                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 71809                       # number of replacements
-system.cpu.l2cache.sampled_refs                 87292                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                 71804                       # number of replacements
+system.cpu.l2cache.sampled_refs                 87286                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             17905.109517                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  411854                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             17904.014680                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  411836                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   57886                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1593519872                       # number of cpu cycles simulated
+system.cpu.numCycles                       1593525852                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 1593519872                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                 1593525852                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     67016068                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_fp_insts                            16                       # number of float instructions
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     1993596                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        598619824                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             531746837                       # Number of integer alu accesses
-system.cpu.num_int_insts                    531746837                       # number of integer instructions
-system.cpu.num_int_register_reads          1837343724                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          456308029                       # number of times the integer registers were written
-system.cpu.num_load_insts                   148953025                       # Number of load instructions
-system.cpu.num_mem_refs                     219174038                       # number of memory refs
+system.cpu.num_insts                        600398281                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             533522639                       # Number of integer alu accesses
+system.cpu.num_int_insts                    533522639                       # number of integer instructions
+system.cpu.num_int_register_reads          1840897552                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          458086291                       # number of times the integer registers were written
+system.cpu.num_load_insts                   148952594                       # Number of load instructions
+system.cpu.num_mem_refs                     219173607                       # number of memory refs
 system.cpu.num_store_insts                   70221013                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
 
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index b96a83286..80aefb4cf 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -10,12 +10,12 @@ type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/chips/pd/randd/dist/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -142,6 +142,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -440,6 +441,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -573,6 +575,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -871,6 +874,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -922,7 +926,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -942,7 +946,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -967,6 +971,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -998,6 +1003,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
@@ -1068,7 +1074,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index dcb4e3644..66e1dd01f 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Mar 15 2011 18:10:57
+M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip
+M5 started Mar 15 2011 18:10:59
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 118370500
-Exiting @ tick 1900831034500 because m5_exit instruction encountered
+Exiting @ tick 1900831106500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 3a665541f..6dbfe53f2 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,395 +1,395 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  67358                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 313516                       # Number of bytes of host memory used
-host_seconds                                   846.09                       # Real time elapsed on the host
-host_tick_rate                             2246601111                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 185731                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 330796                       # Number of bytes of host memory used
+host_seconds                                   306.85                       # Real time elapsed on the host
+host_tick_rate                             6194726969                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    56990797                       # Number of instructions simulated
+sim_insts                                    56990828                       # Number of instructions simulated
 sim_seconds                                  1.900831                       # Number of seconds simulated
-sim_ticks                                1900831034500                       # Number of ticks simulated
+sim_ticks                                1900831106500                       # Number of ticks simulated
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.BTBHits                 5875698                       # Number of BTB hits
-system.cpu0.BPredUnit.BTBLookups             11164328                       # Number of BTB lookups
-system.cpu0.BPredUnit.RASInCorrect              27744                       # Number of incorrect RAS predictions.
-system.cpu0.BPredUnit.condIncorrect            509294                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.condPredicted          10430748                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.lookups                12489171                       # Number of BP lookups
-system.cpu0.BPredUnit.usedRAS                  879952                       # Number of times the RAS was used to get a target.
-system.cpu0.commit.COM:branches               7522146                       # Number of branches committed
-system.cpu0.commit.COM:bw_lim_events           923087                       # number cycles where commit BW limit reached
+system.cpu0.BPredUnit.BTBHits                 5875746                       # Number of BTB hits
+system.cpu0.BPredUnit.BTBLookups             11164335                       # Number of BTB lookups
+system.cpu0.BPredUnit.RASInCorrect              27734                       # Number of incorrect RAS predictions.
+system.cpu0.BPredUnit.condIncorrect            509345                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.condPredicted          10431005                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.lookups                12489231                       # Number of BP lookups
+system.cpu0.BPredUnit.usedRAS                  879926                       # Number of times the RAS was used to get a target.
+system.cpu0.commit.COM:branches               7522155                       # Number of branches committed
+system.cpu0.commit.COM:bw_lim_events           922955                       # number cycles where commit BW limit reached
 system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples     78252168                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean     0.636069                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev     1.403085                       # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::samples     78251630                       # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::mean     0.636074                       # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::stdev     1.403101                       # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0     56997236     72.84%     72.84% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1      9310198     11.90%     84.74% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2      5423748      6.93%     91.67% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3      2443659      3.12%     94.79% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4      1857092      2.37%     97.16% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::5       632524      0.81%     97.97% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::6       342942      0.44%     98.41% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::7       321682      0.41%     98.82% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::8       923087      1.18%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::0     56997001     72.84%     72.84% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::1      9309948     11.90%     84.74% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::2      5423861      6.93%     91.67% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::3      2443172      3.12%     94.79% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::4      1857246      2.37%     97.16% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::5       632479      0.81%     97.97% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::6       343172      0.44%     98.41% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::7       321796      0.41%     98.82% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::8       922955      1.18%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total     78252168                       # Number of insts commited each cycle
-system.cpu0.commit.COM:count                 49773781                       # Number of instructions committed
+system.cpu0.commit.COM:committed_per_cycle::total     78251630                       # Number of insts commited each cycle
+system.cpu0.commit.COM:count                 49773809                       # Number of instructions committed
 system.cpu0.commit.COM:fp_insts                245595                       # Number of committed floating point instructions.
-system.cpu0.commit.COM:function_calls          636046                       # Number of function calls committed.
-system.cpu0.commit.COM:int_insts             46098576                       # Number of committed integer instructions.
-system.cpu0.commit.COM:loads                  7894849                       # Number of loads committed
+system.cpu0.commit.COM:function_calls          636047                       # Number of function calls committed.
+system.cpu0.commit.COM:int_insts             46098602                       # Number of committed integer instructions.
+system.cpu0.commit.COM:loads                  7894859                       # Number of loads committed
 system.cpu0.commit.COM:membars                 191655                       # Number of memory barriers committed
-system.cpu0.commit.COM:refs                  13318728                       # Number of memory references committed
+system.cpu0.commit.COM:refs                  13318738                       # Number of memory references committed
 system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
-system.cpu0.commit.branchMispredicts           652792                       # The number of times a branch was mispredicted
-system.cpu0.commit.commitCommittedInsts      49773781                       # The number of committed instructions
-system.cpu0.commit.commitNonSpecStalls         564764                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.commitSquashedInsts        7279166                       # The number of squashed insts skipped by commit
-system.cpu0.committedInsts                   46913211                       # Number of Instructions Simulated
-system.cpu0.committedInsts_total             46913211                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.403631                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.403631                       # CPI: Total CPI of All Threads
-system.cpu0.dcache.LoadLockedReq_accesses::0       178258                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       178258                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14381.476316                       # average LoadLockedReq miss latency
+system.cpu0.commit.branchMispredicts           652841                       # The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts      49773809                       # The number of committed instructions
+system.cpu0.commit.commitNonSpecStalls         564763                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.commitSquashedInsts        7279602                       # The number of squashed insts skipped by commit
+system.cpu0.committedInsts                   46913237                       # Number of Instructions Simulated
+system.cpu0.committedInsts_total             46913237                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.403611                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.403611                       # CPI: Total CPI of All Threads
+system.cpu0.dcache.LoadLockedReq_accesses::0       178261                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       178261                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14383.272201                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10558.033333                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits::0       158899                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       158899                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency    278411000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.108601                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::0        19359                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19359                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_hits         4359                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    158370500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.084148                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10560.425277                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits::0       158904                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       158904                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency    278417000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.108588                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses::0        19357                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        19357                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_hits         4355                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    158427500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.084157                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses        15000                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses::0        8018067                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8018067                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 23754.598189                       # average ReadReq miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_misses        15002                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses::0        8017759                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8017759                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 23757.902186                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.786651                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.503104                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits::0            6640677                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6640677                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency   32719346000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate::0      0.171786                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::0          1377390                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1377390                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits           392262                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_miss_latency  23413327000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122864                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_hits::0            6640640                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6640640                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency   32717458500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate::0      0.171759                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses::0          1377119                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1377119                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits           391971                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_miss_latency  23413523000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122871                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses         985128                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    920863000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_misses         985148                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    920844000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.StoreCondReq_accesses::0       185114                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       185114                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13329.315068                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13326.438356                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10326.164384                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10323.150685                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_hits::0        181464                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total       181464                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency     48652000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency     48641500                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_rate::0     0.019718                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_misses::0         3650                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total         3650                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency     37690500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency     37679500                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.019718                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_misses         3650                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.WriteReq_accesses::0       5223711                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total      5223711                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 32400.753552                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 32402.197389                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30590.522294                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30590.574400                       # average WriteReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits::0           3606992                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3606992                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency  52382913882                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate::0     0.309496                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0         1616719                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1616719                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits         1353304                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency   8058002430                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.050427                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_hits::0           3607020                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3607020                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency  52384340899                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate::0     0.309491                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0         1616691                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1616691                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_hits         1353284                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency   8057771431                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.050425                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses        263415                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1320187498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8768.456221                       # average number of cycles each access was blocked
+system.cpu0.dcache.WriteReq_mshr_misses        263407                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1320171998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8769.741125                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets        21500                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs                  8.499270                       # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs            83762                       # number of cycles access was blocked
+system.cpu0.dcache.avg_refs                  8.499136                       # Average number of references to valid blocks.
+system.cpu0.dcache.blocked::no_mshrs            83743                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs    734463430                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_mshrs    734404431                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets       150500                       # number of cycles access was blocked
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.demand_accesses::0        13241778                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::0        13241470                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     13241778                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency::0 28423.233717                       # average overall miss latency
+system.cpu0.dcache.demand_accesses::total     13241470                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency::0 28425.918612                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 25206.444175                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0            10247669                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_avg_mshr_miss_latency 25206.173882                       # average overall mshr miss latency
+system.cpu0.dcache.demand_hits::0            10247660                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10247669                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency    85102259882                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::0       0.226111                       # miss rate for demand accesses
+system.cpu0.dcache.demand_hits::total        10247660                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency    85101799399                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate::0       0.226093                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses::0           2994109                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::0           2993810                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2994109                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits           1745566                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency  31471329430                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0     0.094288                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_misses::total       2993810                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits           1745255                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency  31471294431                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate::0     0.094291                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses         1248543                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses         1248555                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.973184                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_%::0                  0.973190                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_%::1                 -0.001953                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0           498.270236                       # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::0           498.273055                       # Average occupied blocks per context
 system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
-system.cpu0.dcache.overall_accesses::0       13241778                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::0       13241470                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     13241778                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency::0 28423.233717                       # average overall miss latency
+system.cpu0.dcache.overall_accesses::total     13241470                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency::0 28425.918612                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 25206.444175                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 25206.173882                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits::0           10247669                       # number of overall hits
+system.cpu0.dcache.overall_hits::0           10247660                       # number of overall hits
 system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10247669                       # number of overall hits
-system.cpu0.dcache.overall_miss_latency   85102259882                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate::0      0.226111                       # miss rate for overall accesses
+system.cpu0.dcache.overall_hits::total       10247660                       # number of overall hits
+system.cpu0.dcache.overall_miss_latency   85101799399                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate::0      0.226093                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses::0          2994109                       # number of overall misses
+system.cpu0.dcache.overall_misses::0          2993810                       # number of overall misses
 system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2994109                       # number of overall misses
-system.cpu0.dcache.overall_mshr_hits          1745566                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency  31471329430                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate::0     0.094288                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_misses::total      2993810                       # number of overall misses
+system.cpu0.dcache.overall_mshr_hits          1745255                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency  31471294431                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate::0     0.094291                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses        1248543                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency   2241050498                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_misses        1248555                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency   2241015998                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements               1246737                       # number of replacements
-system.cpu0.dcache.sampled_refs               1247249                       # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements               1246755                       # number of replacements
+system.cpu0.dcache.sampled_refs               1247267                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse               497.270236                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                10600706                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               497.273055                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                10600692                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks                  721582                       # number of writebacks
-system.cpu0.decode.DECODE:BlockedCycles      33790460                       # Number of cycles decode is blocked
-system.cpu0.decode.DECODE:BranchMispred         33337                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DECODE:BranchResolved       520850                       # Number of times decode resolved a branch
-system.cpu0.decode.DECODE:DecodedInsts       62592464                       # Number of instructions handled by decode
-system.cpu0.decode.DECODE:IdleCycles         32176672                       # Number of cycles decode is idle
-system.cpu0.decode.DECODE:RunCycles          11304141                       # Number of cycles decode is running
-system.cpu0.decode.DECODE:SquashCycles        1271125                       # Number of cycles decode is squashing
-system.cpu0.decode.DECODE:SquashedInsts        100674                       # Number of squashed instructions handled by decode
-system.cpu0.decode.DECODE:UnblockCycles        980894                       # Number of cycles decode is unblocking
-system.cpu0.dtb.data_accesses                  795039                       # DTB accesses
-system.cpu0.dtb.data_acv                          690                       # DTB access violations
-system.cpu0.dtb.data_hits                    14240441                       # DTB hits
-system.cpu0.dtb.data_misses                     32243                       # DTB misses
+system.cpu0.dcache.writebacks                  721595                       # number of writebacks
+system.cpu0.decode.DECODE:BlockedCycles      33789769                       # Number of cycles decode is blocked
+system.cpu0.decode.DECODE:BranchMispred         33336                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DECODE:BranchResolved       520770                       # Number of times decode resolved a branch
+system.cpu0.decode.DECODE:DecodedInsts       62593203                       # Number of instructions handled by decode
+system.cpu0.decode.DECODE:IdleCycles         32176765                       # Number of cycles decode is idle
+system.cpu0.decode.DECODE:RunCycles          11304168                       # Number of cycles decode is running
+system.cpu0.decode.DECODE:SquashCycles        1271210                       # Number of cycles decode is squashing
+system.cpu0.decode.DECODE:SquashedInsts        100660                       # Number of squashed instructions handled by decode
+system.cpu0.decode.DECODE:UnblockCycles        980927                       # Number of cycles decode is unblocking
+system.cpu0.dtb.data_accesses                  794756                       # DTB accesses
+system.cpu0.dtb.data_acv                          688                       # DTB access violations
+system.cpu0.dtb.data_hits                    14240512                       # DTB hits
+system.cpu0.dtb.data_misses                     32288                       # DTB misses
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.read_accesses                  599364                       # DTB read accesses
-system.cpu0.dtb.read_acv                          521                       # DTB read access violations
-system.cpu0.dtb.read_hits                     8656203                       # DTB read hits
-system.cpu0.dtb.read_misses                     26609                       # DTB read misses
-system.cpu0.dtb.write_accesses                 195675                       # DTB write accesses
+system.cpu0.dtb.read_accesses                  599054                       # DTB read accesses
+system.cpu0.dtb.read_acv                          519                       # DTB read access violations
+system.cpu0.dtb.read_hits                     8656143                       # DTB read hits
+system.cpu0.dtb.read_misses                     26649                       # DTB read misses
+system.cpu0.dtb.write_accesses                 195702                       # DTB write accesses
 system.cpu0.dtb.write_acv                         169                       # DTB write access violations
-system.cpu0.dtb.write_hits                    5584238                       # DTB write hits
-system.cpu0.dtb.write_misses                     5634                       # DTB write misses
-system.cpu0.fetch.Branches                   12489171                       # Number of branches that fetch encountered
-system.cpu0.fetch.CacheLines                  7790772                       # Number of cache lines fetched
-system.cpu0.fetch.Cycles                     12447663                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.IcacheSquashes               374479                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.Insts                      63679882                       # Number of instructions fetch has processed
-system.cpu0.fetch.MiscStallCycles               30613                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.SquashCycles                 745308                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.branchRate                 0.110757                       # Number of branch fetches per cycle
-system.cpu0.fetch.icacheStallCycles           7790769                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.predictedBranches           6755650                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.rate                       0.564728                       # Number of inst fetches per cycle
-system.cpu0.fetch.rateDist::samples          79523293                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.800770                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.103978                       # Number of instructions fetched each cycle (Total)
+system.cpu0.dtb.write_hits                    5584369                       # DTB write hits
+system.cpu0.dtb.write_misses                     5639                       # DTB write misses
+system.cpu0.fetch.Branches                   12489231                       # Number of branches that fetch encountered
+system.cpu0.fetch.CacheLines                  7790870                       # Number of cache lines fetched
+system.cpu0.fetch.Cycles                     12447773                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.IcacheSquashes               374462                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.Insts                      63680808                       # Number of instructions fetch has processed
+system.cpu0.fetch.MiscStallCycles               30775                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.SquashCycles                 745389                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.branchRate                 0.110758                       # Number of branch fetches per cycle
+system.cpu0.fetch.icacheStallCycles           7790867                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.predictedBranches           6755672                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.rate                       0.564741                       # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist::samples          79522840                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.800786                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.103997                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                67075630     84.35%     84.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  894785      1.13%     85.47% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1774565      2.23%     87.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  813228      1.02%     88.73% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2745570      3.45%     92.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  583311      0.73%     92.91% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  681126      0.86%     93.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  829932      1.04%     94.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4125146      5.19%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                67075067     84.35%     84.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  894690      1.13%     85.47% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1774768      2.23%     87.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  813051      1.02%     88.73% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2745482      3.45%     92.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  583376      0.73%     92.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  681368      0.86%     93.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  829891      1.04%     94.81% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4125147      5.19%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            79523293                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fp_regfile_reads                   120916                       # number of floating regfile reads
+system.cpu0.fetch.rateDist::total            79522840                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fp_regfile_reads                   120909                       # number of floating regfile reads
 system.cpu0.fp_regfile_writes                  122710                       # number of floating regfile writes
-system.cpu0.icache.ReadReq_accesses::0        7790772                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      7790772                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.907100                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_accesses::0        7790870                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      7790870                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.877874                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12016.512006                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits::0            6933292                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        6933292                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency   12919571500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate::0      0.110064                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses::0           857480                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       857480                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_hits            36653                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_miss_latency   9863477500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.105359                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12016.582299                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits::0            6933419                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        6933419                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency   12919109500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate::0      0.110058                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses::0           857451                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       857451                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_hits            36636                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_miss_latency   9863391000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.105356                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses         820827                       # number of ReadReq MSHR misses
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 11372.727273                       # average number of cycles each access was blocked
+system.cpu0.icache.ReadReq_mshr_misses         820815                       # number of ReadReq MSHR misses
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 11214.285714                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs                  8.447909                       # Average number of references to valid blocks.
-system.cpu0.icache.blocked::no_mshrs               55                       # number of cycles access was blocked
+system.cpu0.icache.avg_refs                  8.448187                       # Average number of references to valid blocks.
+system.cpu0.icache.blocked::no_mshrs               56                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_mshrs       625500                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_mshrs       628000                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.demand_accesses::0         7790772                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::0         7790870                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      7790772                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency::0 15066.907100                       # average overall miss latency
+system.cpu0.icache.demand_accesses::total      7790870                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency::0 15066.877874                       # average overall miss latency
 system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 12016.512006                       # average overall mshr miss latency
-system.cpu0.icache.demand_hits::0             6933292                       # number of demand (read+write) hits
+system.cpu0.icache.demand_avg_mshr_miss_latency 12016.582299                       # average overall mshr miss latency
+system.cpu0.icache.demand_hits::0             6933419                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         6933292                       # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency    12919571500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate::0       0.110064                       # miss rate for demand accesses
+system.cpu0.icache.demand_hits::total         6933419                       # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency    12919109500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate::0       0.110058                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_misses::0            857480                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::0            857451                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        857480                       # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits             36653                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency   9863477500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate::0     0.105359                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_misses::total        857451                       # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits             36636                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency   9863391000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate::0     0.105356                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses          820827                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses          820815                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.occ_%::0                  0.995823                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_blocks::0           509.861442                       # Average occupied blocks per context
-system.cpu0.icache.overall_accesses::0        7790772                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::0        7790870                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      7790772                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency::0 15066.907100                       # average overall miss latency
+system.cpu0.icache.overall_accesses::total      7790870                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency::0 15066.877874                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 12016.512006                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 12016.582299                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits::0            6933292                       # number of overall hits
+system.cpu0.icache.overall_hits::0            6933419                       # number of overall hits
 system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.icache.overall_hits::total        6933292                       # number of overall hits
-system.cpu0.icache.overall_miss_latency   12919571500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate::0      0.110064                       # miss rate for overall accesses
+system.cpu0.icache.overall_hits::total        6933419                       # number of overall hits
+system.cpu0.icache.overall_miss_latency   12919109500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate::0      0.110058                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_misses::0           857480                       # number of overall misses
+system.cpu0.icache.overall_misses::0           857451                       # number of overall misses
 system.cpu0.icache.overall_misses::1                0                       # number of overall misses
-system.cpu0.icache.overall_misses::total       857480                       # number of overall misses
-system.cpu0.icache.overall_mshr_hits            36653                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency   9863477500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate::0     0.105359                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_misses::total       857451                       # number of overall misses
+system.cpu0.icache.overall_mshr_hits            36636                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency   9863391000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate::0     0.105356                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses         820827                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses         820815                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements                820200                       # number of replacements
-system.cpu0.icache.sampled_refs                820711                       # Sample count of references to valid blocks.
+system.cpu0.icache.replacements                820188                       # number of replacements
+system.cpu0.icache.sampled_refs                820699                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu0.icache.tagsinuse               509.861442                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                 6933292                       # Total number of references to valid blocks.
+system.cpu0.icache.total_refs                 6933419                       # Total number of references to valid blocks.
 system.cpu0.icache.warmup_cycle           24435382000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks                     107                       # number of writebacks
-system.cpu0.idleCycles                       33238734                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.iew.EXEC:branches                 8088887                       # Number of branches executed
-system.cpu0.iew.EXEC:nop                      3190702                       # number of nop insts executed
+system.cpu0.icache.writebacks                     160                       # number of writebacks
+system.cpu0.idleCycles                       33238338                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.iew.EXEC:branches                 8088609                       # Number of branches executed
+system.cpu0.iew.EXEC:nop                      3190653                       # number of nop insts executed
 system.cpu0.iew.EXEC:rate                    0.446643                       # Inst execution rate
-system.cpu0.iew.EXEC:refs                    14307235                       # number of memory reference insts executed
-system.cpu0.iew.EXEC:stores                   5602635                       # Number of stores executed
+system.cpu0.iew.EXEC:refs                    14307346                       # number of memory reference insts executed
+system.cpu0.iew.EXEC:stores                   5602769                       # Number of stores executed
 system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu0.iew.WB:consumers                 31606218                       # num instructions consuming a value
-system.cpu0.iew.WB:count                     49988672                       # cumulative count of insts written-back
-system.cpu0.iew.WB:fanout                    0.757998                       # average fanout of values written-back
+system.cpu0.iew.WB:consumers                 31606079                       # num instructions consuming a value
+system.cpu0.iew.WB:count                     49988014                       # cumulative count of insts written-back
+system.cpu0.iew.WB:fanout                    0.757991                       # average fanout of values written-back
 system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
 system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.iew.WB:producers                 23957449                       # num instructions producing a value
-system.cpu0.iew.WB:rate                      0.443311                       # insts written-back per cycle
-system.cpu0.iew.WB:sent                      50070625                       # cumulative count of insts sent to commit
-system.cpu0.iew.branchMispredicts              711853                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewBlockCycles                9019183                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewDispLoadInsts              9134564                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispNonSpecInsts           1512032                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewDispSquashedInsts           755923                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispStoreInsts             5843380                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispatchedInsts           57163450                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewExecLoadInsts              8704600                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           462366                       # Number of squashed instructions skipped in execute
-system.cpu0.iew.iewExecutedInsts             50364381                       # Number of executed instructions
-system.cpu0.iew.iewIQFullEvents                 59583                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.WB:producers                 23957137                       # num instructions producing a value
+system.cpu0.iew.WB:rate                      0.443309                       # insts written-back per cycle
+system.cpu0.iew.WB:sent                      50069991                       # cumulative count of insts sent to commit
+system.cpu0.iew.branchMispredicts              711883                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewBlockCycles                9018658                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewDispLoadInsts              9134985                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispNonSpecInsts           1511781                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewDispSquashedInsts           755973                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispStoreInsts             5843371                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispatchedInsts           57163675                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewExecLoadInsts              8704577                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           462590                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewExecutedInsts             50363992                       # Number of executed instructions
+system.cpu0.iew.iewIQFullEvents                 59575                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewLSQFullEvents                 7004                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.iewSquashCycles               1271125                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewUnblockCycles               547384                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewLSQFullEvents                 7002                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles               1271210                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewUnblockCycles               547356                       # Number of cycles IEW is unblocking
 system.cpu0.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread.0.cacheBlocked       122021                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.lsq.thread.0.forwLoads         410783                       # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread.0.ignoredResponses        10667                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread.0.cacheBlocked       122264                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread.0.forwLoads         410769                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread.0.ignoredResponses        10661                       # Number of memory responses ignored because the instruction is squashed
 system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread.0.memOrderViolation        38522                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread.0.rescheduledLoads        18606                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread.0.squashedLoads      1239715                       # Number of loads squashed
-system.cpu0.iew.lsq.thread.0.squashedStores       419501                       # Number of stores squashed
-system.cpu0.iew.memOrderViolationEvents         38522                       # Number of memory order violations
-system.cpu0.iew.predictedNotTakenIncorrect       332064                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.predictedTakenIncorrect        379789                       # Number of branches that were predicted taken incorrectly
-system.cpu0.int_regfile_reads                66329266                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               36276231                       # number of integer regfile writes
-system.cpu0.ipc                              0.416037                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.416037                       # IPC: Total IPC of All Threads
+system.cpu0.iew.lsq.thread.0.memOrderViolation        38527                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread.0.rescheduledLoads        18607                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread.0.squashedLoads      1240126                       # Number of loads squashed
+system.cpu0.iew.lsq.thread.0.squashedStores       419492                       # Number of stores squashed
+system.cpu0.iew.memOrderViolationEvents         38527                       # Number of memory order violations
+system.cpu0.iew.predictedNotTakenIncorrect       332123                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect        379760                       # Number of branches that were predicted taken incorrectly
+system.cpu0.int_regfile_reads                66329017                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               36275514                       # number of integer regfile writes
+system.cpu0.ipc                              0.416041                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.416041                       # IPC: Total IPC of All Threads
 system.cpu0.iq.ISSUE:FU_type_0::No_OpClass         3762      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntAlu       35322205     69.50%     69.50% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntMult         55712      0.11%     69.61% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntAlu       35321880     69.49%     69.50% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntMult         55711      0.11%     69.61% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     69.61% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::FloatAdd        15323      0.03%     69.64% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     69.64% # Type of FU issued
@@ -417,15 +417,15 @@ system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     69.65%
 system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     69.65% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     69.65% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     69.65% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemRead       9003021     17.71%     87.36% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemWrite      5645656     11.11%     98.47% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IprAccess       779190      1.53%    100.00% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemRead       9003030     17.71%     87.36% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemWrite      5645816     11.11%     98.47% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IprAccess       779182      1.53%    100.00% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::total        50826749                       # Type of FU issued
-system.cpu0.iq.ISSUE:fu_busy_cnt               382289                       # FU busy when requested
+system.cpu0.iq.ISSUE:FU_type_0::total        50826584                       # Type of FU issued
+system.cpu0.iq.ISSUE:fu_busy_cnt               382291                       # FU busy when requested
 system.cpu0.iq.ISSUE:fu_busy_rate            0.007521                       # FU busy rate (busy events/executed inst)
 system.cpu0.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntAlu            40958     10.71%     10.71% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntAlu            40945     10.71%     10.71% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%     10.71% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%     10.71% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%     10.71% # attempts to use FU when none available
@@ -454,51 +454,51 @@ system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     10.71% #
 system.cpu0.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     10.71% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     10.71% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     10.71% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemRead          226307     59.20%     69.91% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemWrite         115024     30.09%    100.00% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemRead          226304     59.20%     69.91% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemWrite         115042     30.09%    100.00% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:issued_per_cycle::samples     79523293                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::mean     0.639143                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.209985                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::samples     79522840                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::mean     0.639144                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.209964                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::0     54765331     68.87%     68.87% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::1     12086611     15.20%     84.07% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::2      5449422      6.85%     90.92% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::3      3416951      4.30%     95.22% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::4      2222762      2.80%     98.01% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::5       992615      1.25%     99.26% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::6       434574      0.55%     99.81% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::7       111342      0.14%     99.95% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::8        43685      0.05%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::0     54765189     68.87%     68.87% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::1     12085919     15.20%     84.07% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::2      5449520      6.85%     90.92% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::3      3416832      4.30%     95.21% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::4      2223696      2.80%     98.01% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::5       992162      1.25%     99.26% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::6       434798      0.55%     99.81% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::7       111045      0.14%     99.95% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::8        43679      0.05%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::total     79523293                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:rate                    0.450743                       # Inst issue rate
-system.cpu0.iq.fp_alu_accesses                 260476                       # Number of floating point alu accesses
-system.cpu0.iq.fp_inst_queue_reads             508189                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       246844                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_writes            251997                       # Number of floating instruction queue writes
-system.cpu0.iq.int_alu_accesses              50944800                       # Number of integer alu accesses
-system.cpu0.iq.int_inst_queue_reads         181074941                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_wakeup_accesses     49741828                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.int_inst_queue_writes         60494151                       # Number of integer instruction queue writes
-system.cpu0.iq.iqInstsAdded                  52250537                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqInstsIssued                 50826749                       # Number of instructions issued
-system.cpu0.iq.iqNonSpecInstsAdded            1722211                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqSquashedInstsExamined        6740578                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedInstsIssued            24052                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedNonSpecRemoved       1157447                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.iqSquashedOperandsExamined      3424469                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.ISSUE:issued_per_cycle::total     79522840                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:rate                    0.450745                       # Inst issue rate
+system.cpu0.iq.fp_alu_accesses                 260468                       # Number of floating point alu accesses
+system.cpu0.iq.fp_inst_queue_reads             508171                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       246837                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_writes            251931                       # Number of floating instruction queue writes
+system.cpu0.iq.int_alu_accesses              50944645                       # Number of integer alu accesses
+system.cpu0.iq.int_inst_queue_reads         181074223                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_wakeup_accesses     49741177                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.int_inst_queue_writes         60494022                       # Number of integer instruction queue writes
+system.cpu0.iq.iqInstsAdded                  52251057                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqInstsIssued                 50826584                       # Number of instructions issued
+system.cpu0.iq.iqNonSpecInstsAdded            1721965                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqSquashedInstsExamined        6740106                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsIssued            24097                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedNonSpecRemoved       1157202                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.iqSquashedOperandsExamined      3425536                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_hits                           0                       # DTB hits
 system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.fetch_accesses                 951927                       # ITB accesses
-system.cpu0.itb.fetch_acv                         732                       # ITB acv
-system.cpu0.itb.fetch_hits                     922973                       # ITB hits
-system.cpu0.itb.fetch_misses                    28954                       # ITB misses
+system.cpu0.itb.fetch_accesses                 951932                       # ITB accesses
+system.cpu0.itb.fetch_acv                         733                       # ITB acv
+system.cpu0.itb.fetch_hits                     923000                       # ITB hits
+system.cpu0.itb.fetch_misses                    28932                       # ITB misses
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
 system.cpu0.itb.read_hits                           0                       # DTB read hits
@@ -515,7 +515,7 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.22% # nu
 system.cpu0.kern.callpal::swpctx                 3287      2.03%      2.25% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      43      0.03%      2.27% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.28% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               147045     90.75%     93.03% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               147044     90.75%     93.03% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6369      3.93%     96.96% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.96% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     3      0.00%     96.96% # number of callpals executed
@@ -524,45 +524,45 @@ system.cpu0.kern.callpal::whami                     2      0.00%     96.96% # nu
 system.cpu0.kern.callpal::rti                    4450      2.75%     99.71% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 330      0.20%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     138      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                162037                       # number of callpals executed
+system.cpu0.kern.callpal::total                162036                       # number of callpals executed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    176106                       # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei                    176105                       # number of hwrei instructions executed
 system.cpu0.kern.inst.quiesce                    6624                       # number of quiesce instructions executed
 system.cpu0.kern.ipl_count::0                   62137     40.37%     40.37% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    238      0.15%     40.53% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1925      1.25%     41.78% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::30                    254      0.17%     41.94% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  89359     58.06%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              153913                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  89358     58.06%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              153912                       # number of times we switched to this ipl
 system.cpu0.kern.ipl_good::0                    61267     49.13%     49.13% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     238      0.19%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1925      1.54%     50.87% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::30                     254      0.20%     51.07% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   61013     48.93%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total               124697                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1862706719500     97.99%     97.99% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               96293500      0.01%     98.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              398446500      0.02%     98.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              103381000      0.01%     98.03% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            37525343500      1.97%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1900830184000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1862707102000     97.99%     97.99% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               96290500      0.01%     98.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              398437500      0.02%     98.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              103382500      0.01%     98.03% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            37525043500      1.97%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1900830256000                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.985999                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.682785                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good::kernel               1172                      
-system.cpu0.kern.mode_good::user                 1173                      
+system.cpu0.kern.ipl_used::31                0.682793                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good::kernel               1171                      
+system.cpu0.kern.mode_good::user                 1172                      
 system.cpu0.kern.mode_good::idle                    0                      
 system.cpu0.kern.mode_switch::kernel             6890                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1173                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1172                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_switch_good::kernel     0.170102                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.169956                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1898860791500     99.90%     99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1969384500      0.10%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel      1898861301500     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1968946500      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    3288                       # number of times the context was actually changed
 system.cpu0.kern.syscall::2                         6      2.99%      2.99% # number of syscalls executed
@@ -595,526 +595,526 @@ system.cpu0.kern.syscall::132                       1      0.50%     98.51% # nu
 system.cpu0.kern.syscall::144                       1      0.50%     99.00% # number of syscalls executed
 system.cpu0.kern.syscall::147                       2      1.00%    100.00% # number of syscalls executed
 system.cpu0.kern.syscall::total                   201                       # number of syscalls executed
-system.cpu0.memDep0.conflictingLoads          2324520                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1920330                       # Number of conflicting stores.
-system.cpu0.memDep0.insertedLoads             9134564                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5843380                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.misc_regfile_reads                1626369                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                787165                       # number of misc regfile writes
-system.cpu0.numCycles                       112762027                       # number of cpu cycles simulated
+system.cpu0.memDep0.conflictingLoads          2323915                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1919788                       # Number of conflicting stores.
+system.cpu0.memDep0.insertedLoads             9134985                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            5843371                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.misc_regfile_reads                1626355                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                787160                       # number of misc regfile writes
+system.cpu0.numCycles                       112761178                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.rename.RENAME:BlockCycles        12784616                       # Number of cycles rename is blocking
-system.cpu0.rename.RENAME:CommittedMaps      33979042                       # Number of HB maps that are committed
-system.cpu0.rename.RENAME:IQFullEvents        1006695                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.RENAME:IdleCycles         33581656                       # Number of cycles rename is idle
-system.cpu0.rename.RENAME:LSQFullEvents       1371330                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RENAME:ROBFullEvents         43310                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.RENAME:RenameLookups      72537525                       # Number of register rename lookups that rename has made
-system.cpu0.rename.RENAME:RenamedInsts       59326371                       # Number of instructions processed by rename
-system.cpu0.rename.RENAME:RenamedOperands     39979107                       # Number of destination operands rename has renamed
-system.cpu0.rename.RENAME:RunCycles          11035754                       # Number of cycles rename is running
-system.cpu0.rename.RENAME:SquashCycles        1271125                       # Number of cycles rename is squashing
-system.cpu0.rename.RENAME:UnblockCycles       3987965                       # Number of cycles rename is unblocking
-system.cpu0.rename.RENAME:UndoneMaps          6000063                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:fp_rename_lookups       359001                       # Number of floating rename lookups
-system.cpu0.rename.RENAME:int_rename_lookups     72178524                       # Number of integer rename lookups
-system.cpu0.rename.RENAME:serializeStallCycles     16862175                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RENAME:serializingInsts      1393641                       # count of serializing insts renamed
-system.cpu0.rename.RENAME:skidInsts          10087757                       # count of insts added to the skid buffer
-system.cpu0.rename.RENAME:tempSerializingInsts       207582                       # count of temporary serializing insts renamed
-system.cpu0.rob.rob_reads                   134196739                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  115376344                       # The number of ROB writes
-system.cpu0.timesIdled                        1187239                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.rename.RENAME:BlockCycles        12784143                       # Number of cycles rename is blocking
+system.cpu0.rename.RENAME:CommittedMaps      33979065                       # Number of HB maps that are committed
+system.cpu0.rename.RENAME:IQFullEvents        1006573                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.RENAME:IdleCycles         33581705                       # Number of cycles rename is idle
+system.cpu0.rename.RENAME:LSQFullEvents       1371242                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RENAME:ROBFullEvents         43321                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.RENAME:RenameLookups      72539076                       # Number of register rename lookups that rename has made
+system.cpu0.rename.RENAME:RenamedInsts       59327188                       # Number of instructions processed by rename
+system.cpu0.rename.RENAME:RenamedOperands     39979686                       # Number of destination operands rename has renamed
+system.cpu0.rename.RENAME:RunCycles          11035795                       # Number of cycles rename is running
+system.cpu0.rename.RENAME:SquashCycles        1271210                       # Number of cycles rename is squashing
+system.cpu0.rename.RENAME:UnblockCycles       3987790                       # Number of cycles rename is unblocking
+system.cpu0.rename.RENAME:UndoneMaps          6000619                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:fp_rename_lookups       358919                       # Number of floating rename lookups
+system.cpu0.rename.RENAME:int_rename_lookups     72180157                       # Number of integer rename lookups
+system.cpu0.rename.RENAME:serializeStallCycles     16862195                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RENAME:serializingInsts      1393628                       # count of serializing insts renamed
+system.cpu0.rename.RENAME:skidInsts          10087517                       # count of insts added to the skid buffer
+system.cpu0.rename.RENAME:tempSerializingInsts       207585                       # count of temporary serializing insts renamed
+system.cpu0.rob.rob_reads                   134196797                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  115377386                       # The number of ROB writes
+system.cpu0.timesIdled                        1187168                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.BTBHits                 1159872                       # Number of BTB hits
-system.cpu1.BPredUnit.BTBLookups              2699541                       # Number of BTB lookups
-system.cpu1.BPredUnit.RASInCorrect               8252                       # Number of incorrect RAS predictions.
+system.cpu1.BPredUnit.BTBHits                 1161804                       # Number of BTB hits
+system.cpu1.BPredUnit.BTBLookups              2701483                       # Number of BTB lookups
+system.cpu1.BPredUnit.RASInCorrect               8265                       # Number of incorrect RAS predictions.
 system.cpu1.BPredUnit.condIncorrect            107435                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.condPredicted           2484356                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.lookups                 2997970                       # Number of BP lookups
-system.cpu1.BPredUnit.usedRAS                  209804                       # Number of times the RAS was used to get a target.
-system.cpu1.commit.COM:branches               1520810                       # Number of branches committed
-system.cpu1.commit.COM:bw_lim_events           200192                       # number cycles where commit BW limit reached
+system.cpu1.BPredUnit.condPredicted           2484023                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.lookups                 2997822                       # Number of BP lookups
+system.cpu1.BPredUnit.usedRAS                  209923                       # Number of times the RAS was used to get a target.
+system.cpu1.commit.COM:branches               1520807                       # Number of branches committed
+system.cpu1.commit.COM:bw_lim_events           198341                       # number cycles where commit BW limit reached
 system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu1.commit.COM:committed_per_cycle::samples     17838555                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::mean     0.594502                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::stdev     1.408069                       # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::samples     17840200                       # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::mean     0.594448                       # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::stdev     1.407345                       # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::0     13455309     75.43%     75.43% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::1      2068240     11.59%     87.02% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::2       796982      4.47%     91.49% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::3       568404      3.19%     94.68% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::4       398869      2.24%     96.91% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::5       150882      0.85%     97.76% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::6       111519      0.63%     98.38% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::7        88158      0.49%     98.88% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::8       200192      1.12%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::0     13454331     75.42%     75.42% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::1      2070557     11.61%     87.02% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::2       797281      4.47%     91.49% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::3       568657      3.19%     94.68% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::4       399402      2.24%     96.92% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::5       150078      0.84%     97.76% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::6       111624      0.63%     98.38% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::7        89929      0.50%     98.89% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::8       198341      1.11%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::total     17838555                       # Number of insts commited each cycle
-system.cpu1.commit.COM:count                 10605058                       # Number of instructions committed
+system.cpu1.commit.COM:committed_per_cycle::total     17840200                       # Number of insts commited each cycle
+system.cpu1.commit.COM:count                 10605063                       # Number of instructions committed
 system.cpu1.commit.COM:fp_insts                116296                       # Number of committed floating point instructions.
 system.cpu1.commit.COM:function_calls          166623                       # Number of function calls committed.
-system.cpu1.commit.COM:int_insts              9814589                       # Number of committed integer instructions.
-system.cpu1.commit.COM:loads                  1991974                       # Number of loads committed
+system.cpu1.commit.COM:int_insts              9814594                       # Number of committed integer instructions.
+system.cpu1.commit.COM:loads                  1991971                       # Number of loads committed
 system.cpu1.commit.COM:membars                  52733                       # Number of memory barriers committed
-system.cpu1.commit.COM:refs                   3376359                       # Number of memory references committed
+system.cpu1.commit.COM:refs                   3376356                       # Number of memory references committed
 system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
-system.cpu1.commit.branchMispredicts           164468                       # The number of times a branch was mispredicted
-system.cpu1.commit.commitCommittedInsts      10605058                       # The number of committed instructions
+system.cpu1.commit.branchMispredicts           164474                       # The number of times a branch was mispredicted
+system.cpu1.commit.commitCommittedInsts      10605063                       # The number of committed instructions
 system.cpu1.commit.commitNonSpecStalls         163004                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.commitSquashedInsts        1721791                       # The number of squashed insts skipped by commit
-system.cpu1.committedInsts                   10077586                       # Number of Instructions Simulated
-system.cpu1.committedInsts_total             10077586                       # Number of Instructions Simulated
-system.cpu1.cpi                              1.948890                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.948890                       # CPI: Total CPI of All Threads
-system.cpu1.dcache.LoadLockedReq_accesses::0        46378                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        46378                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11069.539376                       # average LoadLockedReq miss latency
+system.cpu1.commit.commitSquashedInsts        1721637                       # The number of squashed insts skipped by commit
+system.cpu1.committedInsts                   10077591                       # Number of Instructions Simulated
+system.cpu1.committedInsts_total             10077591                       # Number of Instructions Simulated
+system.cpu1.cpi                              1.948947                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.948947                       # CPI: Total CPI of All Threads
+system.cpu1.dcache.LoadLockedReq_accesses::0        46373                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        46373                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11076.917360                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  7993.965806                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits::0        39648                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        39648                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency     74498000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.145112                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses::0         6730                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         6730                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_hits          764                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     47692000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.128639                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  7999.664711                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits::0        39645                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        39645                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency     74525500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.145084                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses::0         6728                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         6728                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_hits          763                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     47718000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.128631                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses         5966                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses::0        2062902                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2062902                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 15016.821540                       # average ReadReq miss latency
+system.cpu1.dcache.LoadLockedReq_mshr_misses         5965                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses::0        2063020                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2063020                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 15006.932779                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11679.389313                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11671.409798                       # average ReadReq mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits::0            1868657                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1868657                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency    2916942500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate::0      0.094161                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses::0           194245                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       194245                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_hits            99139                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_miss_latency   1110780000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.046103                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_hits::0            1868365                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1868365                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency    2921174500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate::0      0.094354                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses::0           194655                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       194655                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_hits            99535                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_miss_latency   1110184500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.046107                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses          95106                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses          95120                       # number of ReadReq MSHR misses
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     17677500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.StoreCondReq_accesses::0        43196                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total        43196                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13130.603783                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13132.452048                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10135.856884                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits::0         39337                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        39337                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency     50671000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.089337                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::0         3859                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         3859                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency     39094000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.089291                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10137.707469                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits::0         39338                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        39338                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency     50665000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate::0     0.089314                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses::0         3858                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         3858                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency     39091000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.089268                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses         3857                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses         3856                       # number of StoreCondReq MSHR misses
 system.cpu1.dcache.WriteReq_accesses::0       1334800                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total      1334800                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 21227.985433                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 21239.554449                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18769.279348                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18778.969096                       # average WriteReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits::0           1085325                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1085325                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency   5295851666                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate::0     0.186901                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::0          249475                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       249475                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_hits          201005                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_miss_latency    909746970                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.036313                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_hits::0           1085291                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1085291                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency   5299459991                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate::0     0.186926                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses::0          249509                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       249509                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_hits          201036                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_miss_latency    910272969                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.036315                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses         48470                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    377654500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs  9972.984645                       # average number of cycles each access was blocked
+system.cpu1.dcache.WriteReq_mshr_misses         48473                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    377656000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs  9801.734092                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs                 22.879556                       # Average number of references to valid blocks.
-system.cpu1.dcache.blocked::no_mshrs             5275                       # number of cycles access was blocked
+system.cpu1.dcache.avg_refs                 22.873773                       # Average number of references to valid blocks.
+system.cpu1.dcache.blocked::no_mshrs             5359                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_mshrs     52607494                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_mshrs     52527493                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.demand_accesses::0         3397702                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::0         3397820                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3397702                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 18508.956473                       # average overall miss latency
+system.cpu1.dcache.demand_accesses::total      3397820                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency::0 18508.106220                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 14072.874088                       # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::0             2953982                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_avg_mshr_miss_latency 14070.723984                       # average overall mshr miss latency
+system.cpu1.dcache.demand_hits::0             2953656                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         2953982                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency     8212794166                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::0       0.130594                       # miss rate for demand accesses
+system.cpu1.dcache.demand_hits::total         2953656                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency     8220634491                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate::0       0.130720                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_misses::0            443720                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::0            444164                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        443720                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits            300144                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency   2020526970                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0     0.042257                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_misses::total        444164                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits            300571                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency   2020457469                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate::0     0.042260                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses          143576                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses          143593                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.933238                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0           477.817937                       # Average occupied blocks per context
-system.cpu1.dcache.overall_accesses::0        3397702                       # number of overall (read+write) accesses
+system.cpu1.dcache.occ_%::0                  0.933239                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::0           477.818308                       # Average occupied blocks per context
+system.cpu1.dcache.overall_accesses::0        3397820                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3397702                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency::0 18508.956473                       # average overall miss latency
+system.cpu1.dcache.overall_accesses::total      3397820                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency::0 18508.106220                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 14072.874088                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 14070.723984                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits::0            2953982                       # number of overall hits
+system.cpu1.dcache.overall_hits::0            2953656                       # number of overall hits
 system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        2953982                       # number of overall hits
-system.cpu1.dcache.overall_miss_latency    8212794166                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate::0      0.130594                       # miss rate for overall accesses
+system.cpu1.dcache.overall_hits::total        2953656                       # number of overall hits
+system.cpu1.dcache.overall_miss_latency    8220634491                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate::0      0.130720                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_misses::0           443720                       # number of overall misses
+system.cpu1.dcache.overall_misses::0           444164                       # number of overall misses
 system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       443720                       # number of overall misses
-system.cpu1.dcache.overall_mshr_hits           300144                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency   2020526970                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate::0     0.042257                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_misses::total       444164                       # number of overall misses
+system.cpu1.dcache.overall_mshr_hits           300571                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency   2020457469                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate::0     0.042260                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses         143576                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency    395332000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_misses         143593                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency    395333500                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.replacements                132522                       # number of replacements
-system.cpu1.dcache.sampled_refs                132916                       # Sample count of references to valid blocks.
+system.cpu1.dcache.replacements                132541                       # number of replacements
+system.cpu1.dcache.sampled_refs                132935                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse               477.817937                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 3041059                       # Total number of references to valid blocks.
+system.cpu1.dcache.tagsinuse               477.818308                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 3040725                       # Total number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle          1877659429000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks                   88703                       # number of writebacks
-system.cpu1.decode.DECODE:BlockedCycles       6965197                       # Number of cycles decode is blocked
-system.cpu1.decode.DECODE:BranchMispred          7952                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DECODE:BranchResolved       127936                       # Number of times decode resolved a branch
-system.cpu1.decode.DECODE:DecodedInsts       13953075                       # Number of instructions handled by decode
-system.cpu1.decode.DECODE:IdleCycles          8268454                       # Number of cycles decode is idle
-system.cpu1.decode.DECODE:RunCycles           2505615                       # Number of cycles decode is running
-system.cpu1.decode.DECODE:SquashCycles         305805                       # Number of cycles decode is squashing
-system.cpu1.decode.DECODE:SquashedInsts         23745                       # Number of squashed instructions handled by decode
-system.cpu1.decode.DECODE:UnblockCycles         99288                       # Number of cycles decode is unblocking
-system.cpu1.dtb.data_accesses                  453627                       # DTB accesses
-system.cpu1.dtb.data_acv                          183                       # DTB access violations
-system.cpu1.dtb.data_hits                     3614601                       # DTB hits
-system.cpu1.dtb.data_misses                     12965                       # DTB misses
+system.cpu1.dcache.writebacks                   88729                       # number of writebacks
+system.cpu1.decode.DECODE:BlockedCycles       6964749                       # Number of cycles decode is blocked
+system.cpu1.decode.DECODE:BranchMispred          7942                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DECODE:BranchResolved       127908                       # Number of times decode resolved a branch
+system.cpu1.decode.DECODE:DecodedInsts       13950494                       # Number of instructions handled by decode
+system.cpu1.decode.DECODE:IdleCycles          8268833                       # Number of cycles decode is idle
+system.cpu1.decode.DECODE:RunCycles           2507185                       # Number of cycles decode is running
+system.cpu1.decode.DECODE:SquashCycles         305915                       # Number of cycles decode is squashing
+system.cpu1.decode.DECODE:SquashedInsts         23718                       # Number of squashed instructions handled by decode
+system.cpu1.decode.DECODE:UnblockCycles         99432                       # Number of cycles decode is unblocking
+system.cpu1.dtb.data_accesses                  453938                       # DTB accesses
+system.cpu1.dtb.data_acv                          180                       # DTB access violations
+system.cpu1.dtb.data_hits                     3612649                       # DTB hits
+system.cpu1.dtb.data_misses                     12920                       # DTB misses
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.read_accesses                  321686                       # DTB read accesses
+system.cpu1.dtb.read_accesses                  321913                       # DTB read accesses
 system.cpu1.dtb.read_acv                           80                       # DTB read access violations
-system.cpu1.dtb.read_hits                     2187439                       # DTB read hits
-system.cpu1.dtb.read_misses                     10558                       # DTB read misses
-system.cpu1.dtb.write_accesses                 131941                       # DTB write accesses
-system.cpu1.dtb.write_acv                         103                       # DTB write access violations
-system.cpu1.dtb.write_hits                    1427162                       # DTB write hits
-system.cpu1.dtb.write_misses                     2407                       # DTB write misses
-system.cpu1.fetch.Branches                    2997970                       # Number of branches that fetch encountered
-system.cpu1.fetch.CacheLines                  1676515                       # Number of cache lines fetched
-system.cpu1.fetch.Cycles                      2637646                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.IcacheSquashes               103832                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.Insts                      14205200                       # Number of instructions fetch has processed
-system.cpu1.fetch.MiscStallCycles                9114                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.SquashCycles                 191574                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.branchRate                 0.152645                       # Number of branch fetches per cycle
-system.cpu1.fetch.icacheStallCycles           1676514                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.predictedBranches           1369676                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.rate                       0.723275                       # Number of inst fetches per cycle
-system.cpu1.fetch.rateDist::samples          18144360                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.782899                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.130950                       # Number of instructions fetched each cycle (Total)
+system.cpu1.dtb.read_hits                     2185375                       # DTB read hits
+system.cpu1.dtb.read_misses                     10510                       # DTB read misses
+system.cpu1.dtb.write_accesses                 132025                       # DTB write accesses
+system.cpu1.dtb.write_acv                         100                       # DTB write access violations
+system.cpu1.dtb.write_hits                    1427274                       # DTB write hits
+system.cpu1.dtb.write_misses                     2410                       # DTB write misses
+system.cpu1.fetch.Branches                    2997822                       # Number of branches that fetch encountered
+system.cpu1.fetch.CacheLines                  1676432                       # Number of cache lines fetched
+system.cpu1.fetch.Cycles                      2639364                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.IcacheSquashes               103824                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.Insts                      14202816                       # Number of instructions fetch has processed
+system.cpu1.fetch.MiscStallCycles                9160                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.SquashCycles                 191448                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.branchRate                 0.152633                       # Number of branch fetches per cycle
+system.cpu1.fetch.icacheStallCycles           1676430                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.predictedBranches           1371727                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.rate                       0.723132                       # Number of inst fetches per cycle
+system.cpu1.fetch.rateDist::samples          18146115                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.782692                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.130549                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                15506714     85.46%     85.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  209351      1.15%     86.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  321604      1.77%     88.39% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  202250      1.11%     89.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  379744      2.09%     91.60% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  126923      0.70%     92.30% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  169833      0.94%     93.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  250226      1.38%     94.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                  977715      5.39%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                15506751     85.45%     85.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  211557      1.17%     86.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  323359      1.78%     88.40% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  200500      1.10%     89.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  379117      2.09%     91.60% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  126850      0.70%     92.30% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  170740      0.94%     93.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  250045      1.38%     94.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                  977196      5.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            18144360                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fp_regfile_reads                    63103                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   63156                       # number of floating regfile writes
-system.cpu1.icache.ReadReq_accesses::0        1676515                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1676515                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.731413                       # average ReadReq miss latency
+system.cpu1.fetch.rateDist::total            18146115                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fp_regfile_reads                    63126                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   63154                       # number of floating regfile writes
+system.cpu1.icache.ReadReq_accesses::0        1676432                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1676432                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.725411                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11628.822702                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits::0            1412481                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1412481                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency    3874364000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate::0      0.157490                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses::0           264034                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       264034                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_hits             8194                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_miss_latency   2975118000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.152602                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11629.810943                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits::0            1412386                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1412386                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency    3874538500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate::0      0.157505                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses::0           264046                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       264046                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_hits             8197                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_miss_latency   2975475500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.152615                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses         255840                       # number of ReadReq MSHR misses
-system.cpu1.icache.avg_blocked_cycles::no_mshrs         5000                       # average number of cycles each access was blocked
+system.cpu1.icache.ReadReq_mshr_misses         255849                       # number of ReadReq MSHR misses
+system.cpu1.icache.avg_blocked_cycles::no_mshrs  5555.555556                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs                  5.522142                       # Average number of references to valid blocks.
-system.cpu1.icache.blocked::no_mshrs                8                       # number of cycles access was blocked
+system.cpu1.icache.avg_refs                  5.521576                       # Average number of references to valid blocks.
+system.cpu1.icache.blocked::no_mshrs                9                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_mshrs        40000                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_mshrs        50000                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.demand_accesses::0         1676515                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::0         1676432                       # number of demand (read+write) accesses
 system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1676515                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency::0 14673.731413                       # average overall miss latency
+system.cpu1.icache.demand_accesses::total      1676432                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency::0 14673.725411                       # average overall miss latency
 system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11628.822702                       # average overall mshr miss latency
-system.cpu1.icache.demand_hits::0             1412481                       # number of demand (read+write) hits
+system.cpu1.icache.demand_avg_mshr_miss_latency 11629.810943                       # average overall mshr miss latency
+system.cpu1.icache.demand_hits::0             1412386                       # number of demand (read+write) hits
 system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1412481                       # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency     3874364000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate::0       0.157490                       # miss rate for demand accesses
+system.cpu1.icache.demand_hits::total         1412386                       # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency     3874538500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate::0       0.157505                       # miss rate for demand accesses
 system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_misses::0            264034                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::0            264046                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        264034                       # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits              8194                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency   2975118000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate::0     0.152602                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_misses::total        264046                       # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits              8197                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency   2975475500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate::0     0.152615                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses          255840                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses          255849                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.occ_%::0                  0.900434                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_blocks::0           461.022394                       # Average occupied blocks per context
-system.cpu1.icache.overall_accesses::0        1676515                       # number of overall (read+write) accesses
+system.cpu1.icache.occ_blocks::0           461.022397                       # Average occupied blocks per context
+system.cpu1.icache.overall_accesses::0        1676432                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1676515                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency::0 14673.731413                       # average overall miss latency
+system.cpu1.icache.overall_accesses::total      1676432                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency::0 14673.725411                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11628.822702                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11629.810943                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits::0            1412481                       # number of overall hits
+system.cpu1.icache.overall_hits::0            1412386                       # number of overall hits
 system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1412481                       # number of overall hits
-system.cpu1.icache.overall_miss_latency    3874364000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate::0      0.157490                       # miss rate for overall accesses
+system.cpu1.icache.overall_hits::total        1412386                       # number of overall hits
+system.cpu1.icache.overall_miss_latency    3874538500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate::0      0.157505                       # miss rate for overall accesses
 system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_misses::0           264034                       # number of overall misses
+system.cpu1.icache.overall_misses::0           264046                       # number of overall misses
 system.cpu1.icache.overall_misses::1                0                       # number of overall misses
-system.cpu1.icache.overall_misses::total       264034                       # number of overall misses
-system.cpu1.icache.overall_mshr_hits             8194                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency   2975118000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate::0     0.152602                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_misses::total       264046                       # number of overall misses
+system.cpu1.icache.overall_mshr_hits             8197                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency   2975475500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate::0     0.152615                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses         255840                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses         255849                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.replacements                255273                       # number of replacements
-system.cpu1.icache.sampled_refs                255785                       # Sample count of references to valid blocks.
+system.cpu1.icache.replacements                255282                       # number of replacements
+system.cpu1.icache.sampled_refs                255794                       # Sample count of references to valid blocks.
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse               461.022394                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 1412481                       # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1897915849000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks                      13                       # number of writebacks
-system.cpu1.idleCycles                        1495744                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.iew.EXEC:branches                 1630347                       # Number of branches executed
-system.cpu1.iew.EXEC:nop                       601729                       # number of nop insts executed
-system.cpu1.iew.EXEC:rate                    0.552052                       # Inst execution rate
-system.cpu1.iew.EXEC:refs                     3644132                       # number of memory reference insts executed
-system.cpu1.iew.EXEC:stores                   1436628                       # Number of stores executed
+system.cpu1.icache.tagsinuse               461.022397                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 1412386                       # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1897915594000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks                      23                       # number of writebacks
+system.cpu1.idleCycles                        1494579                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.iew.EXEC:branches                 1630757                       # Number of branches executed
+system.cpu1.iew.EXEC:nop                       601681                       # number of nop insts executed
+system.cpu1.iew.EXEC:rate                    0.552014                       # Inst execution rate
+system.cpu1.iew.EXEC:refs                     3642117                       # number of memory reference insts executed
+system.cpu1.iew.EXEC:stores                   1436733                       # Number of stores executed
 system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu1.iew.WB:consumers                  6274106                       # num instructions consuming a value
-system.cpu1.iew.WB:count                     10735003                       # cumulative count of insts written-back
-system.cpu1.iew.WB:fanout                    0.735138                       # average fanout of values written-back
+system.cpu1.iew.WB:consumers                  6271876                       # num instructions consuming a value
+system.cpu1.iew.WB:count                     10737023                       # cumulative count of insts written-back
+system.cpu1.iew.WB:fanout                    0.735626                       # average fanout of values written-back
 system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
 system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.iew.WB:producers                  4612335                       # num instructions producing a value
-system.cpu1.iew.WB:rate                      0.546586                       # insts written-back per cycle
-system.cpu1.iew.WB:sent                      10758148                       # cumulative count of insts sent to commit
-system.cpu1.iew.branchMispredicts              178810                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewBlockCycles                 256636                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewDispLoadInsts              2309588                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispNonSpecInsts            500342                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewDispSquashedInsts           209309                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispStoreInsts             1512714                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispatchedInsts           12409933                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewExecLoadInsts              2207504                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           107468                       # Number of squashed instructions skipped in execute
-system.cpu1.iew.iewExecutedInsts             10842361                       # Number of executed instructions
-system.cpu1.iew.iewIQFullEvents                  2486                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.WB:producers                  4613753                       # num instructions producing a value
+system.cpu1.iew.WB:rate                      0.546672                       # insts written-back per cycle
+system.cpu1.iew.WB:sent                      10760010                       # cumulative count of insts sent to commit
+system.cpu1.iew.branchMispredicts              178779                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewBlockCycles                 257448                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewDispLoadInsts              2307630                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispNonSpecInsts            500245                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewDispSquashedInsts           209270                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispStoreInsts             1513195                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispatchedInsts           12409620                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewExecLoadInsts              2205384                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           107607                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewExecutedInsts             10841947                       # Number of executed instructions
+system.cpu1.iew.iewIQFullEvents                  2515                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewLSQFullEvents                 4828                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.iewSquashCycles                305805                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewUnblockCycles                10156                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewLSQFullEvents                 4902                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                305915                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewUnblockCycles                10123                       # Number of cycles IEW is unblocking
 system.cpu1.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread.0.cacheBlocked        22318                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.lsq.thread.0.forwLoads          68189                       # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread.0.ignoredResponses         2236                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread.0.cacheBlocked        20397                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread.0.forwLoads          68108                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread.0.ignoredResponses         2244                       # Number of memory responses ignored because the instruction is squashed
 system.cpu1.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu1.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread.0.memOrderViolation        10653                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread.0.rescheduledLoads          380                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread.0.squashedLoads       317614                       # Number of loads squashed
-system.cpu1.iew.lsq.thread.0.squashedStores       128329                       # Number of stores squashed
-system.cpu1.iew.memOrderViolationEvents         10653                       # Number of memory order violations
-system.cpu1.iew.predictedNotTakenIncorrect       104816                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.predictedTakenIncorrect         73994                       # Number of branches that were predicted taken incorrectly
-system.cpu1.int_regfile_reads                13933756                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                7611585                       # number of integer regfile writes
-system.cpu1.ipc                              0.513113                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.513113                       # IPC: Total IPC of All Threads
+system.cpu1.iew.lsq.thread.0.memOrderViolation        10644                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread.0.rescheduledLoads          381                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread.0.squashedLoads       315659                       # Number of loads squashed
+system.cpu1.iew.lsq.thread.0.squashedStores       128810                       # Number of stores squashed
+system.cpu1.iew.memOrderViolationEvents         10644                       # Number of memory order violations
+system.cpu1.iew.predictedNotTakenIncorrect       104770                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.predictedTakenIncorrect         74009                       # Number of branches that were predicted taken incorrectly
+system.cpu1.int_regfile_reads                13934200                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                7613029                       # number of integer regfile writes
+system.cpu1.ipc                              0.513098                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.513098                       # IPC: Total IPC of All Threads
 system.cpu1.iq.ISSUE:FU_type_0::No_OpClass         3524      0.03%      0.03% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntAlu        6870860     62.75%     62.78% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntMult         18138      0.17%     62.95% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     62.95% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatAdd        11432      0.10%     63.05% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     63.05% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     63.05% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     63.05% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatDiv         1762      0.02%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemRead       2282503     20.85%     83.91% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemWrite      1453754     13.28%     97.19% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntAlu        6872542     62.77%     62.80% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntMult         18152      0.17%     62.96% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     62.96% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatAdd        11432      0.10%     63.07% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatDiv         1762      0.02%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemRead       2280411     20.83%     83.91% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemWrite      1453875     13.28%     97.19% # Type of FU issued
 system.cpu1.iq.ISSUE:FU_type_0::IprAccess       307856      2.81%    100.00% # Type of FU issued
 system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::total        10949829                       # Type of FU issued
-system.cpu1.iq.ISSUE:fu_busy_cnt               154910                       # FU busy when requested
-system.cpu1.iq.ISSUE:fu_busy_rate            0.014147                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.ISSUE:FU_type_0::total        10949554                       # Type of FU issued
+system.cpu1.iq.ISSUE:fu_busy_cnt               155065                       # FU busy when requested
+system.cpu1.iq.ISSUE:fu_busy_rate            0.014162                       # FU busy rate (busy events/executed inst)
 system.cpu1.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntAlu             4092      2.64%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAdd               0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAlu               0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCmp               0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCvt               0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMisc              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMult              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShift             0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemRead           90881     58.67%     61.31% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemWrite          59937     38.69%    100.00% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntAlu             4030      2.60%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAdd               0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAlu               0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdCmp               0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdCvt               0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMisc              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMult              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdShift             0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemRead           91114     58.76%     61.36% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemWrite          59921     38.64%    100.00% # attempts to use FU when none available
 system.cpu1.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:issued_per_cycle::samples     18144360                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.603484                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.209438                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::samples     18146115                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.603410                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.208341                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::0     12920190     71.21%     71.21% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::1      2565455     14.14%     85.35% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::2      1066502      5.88%     91.22% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::3       689185      3.80%     95.02% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::4       526783      2.90%     97.93% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::5       236336      1.30%     99.23% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::6        93675      0.52%     99.75% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::7        36919      0.20%     99.95% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::8         9315      0.05%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::0     12918859     71.19%     71.19% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::1      2566374     14.14%     85.34% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::2      1069941      5.90%     91.23% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::3       687798      3.79%     95.02% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::4       527186      2.91%     97.93% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::5       238422      1.31%     99.24% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::6        93189      0.51%     99.76% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::7        34852      0.19%     99.95% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::8         9494      0.05%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::total     18144360                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:rate                    0.557524                       # Inst issue rate
-system.cpu1.iq.fp_alu_accesses                 125165                       # Number of floating point alu accesses
-system.cpu1.iq.fp_inst_queue_reads             243017                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       117535                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_writes            119622                       # Number of floating instruction queue writes
-system.cpu1.iq.int_alu_accesses              10976050                       # Number of integer alu accesses
-system.cpu1.iq.int_inst_queue_reads          39966063                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_wakeup_accesses     10617468                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.int_inst_queue_writes         13352810                       # Number of integer instruction queue writes
-system.cpu1.iq.iqInstsAdded                  11252421                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqInstsIssued                 10949829                       # Number of instructions issued
-system.cpu1.iq.iqNonSpecInstsAdded             555783                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqSquashedInstsExamined        1655590                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedInstsIssued            10152                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedNonSpecRemoved        392779                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.iqSquashedOperandsExamined       854299                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.ISSUE:issued_per_cycle::total     18146115                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:rate                    0.557493                       # Inst issue rate
+system.cpu1.iq.fp_alu_accesses                 125187                       # Number of floating point alu accesses
+system.cpu1.iq.fp_inst_queue_reads             243060                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       117556                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_writes            119680                       # Number of floating instruction queue writes
+system.cpu1.iq.int_alu_accesses              10975908                       # Number of integer alu accesses
+system.cpu1.iq.int_inst_queue_reads          39967405                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_wakeup_accesses     10619467                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.int_inst_queue_writes         13352100                       # Number of integer instruction queue writes
+system.cpu1.iq.iqInstsAdded                  11252265                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqInstsIssued                 10949554                       # Number of instructions issued
+system.cpu1.iq.iqNonSpecInstsAdded             555674                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqSquashedInstsExamined        1655179                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsIssued            10177                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedNonSpecRemoved        392670                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.iqSquashedOperandsExamined       852165                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_hits                           0                       # DTB hits
 system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.fetch_accesses                 448461                       # ITB accesses
-system.cpu1.itb.fetch_acv                         279                       # ITB acv
-system.cpu1.itb.fetch_hits                     439821                       # ITB hits
-system.cpu1.itb.fetch_misses                     8640                       # ITB misses
+system.cpu1.itb.fetch_accesses                 448608                       # ITB accesses
+system.cpu1.itb.fetch_acv                         274                       # ITB acv
+system.cpu1.itb.fetch_hits                     439933                       # ITB hits
+system.cpu1.itb.fetch_misses                     8675                       # ITB misses
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
 system.cpu1.itb.read_hits                           0                       # DTB read hits
@@ -1154,11 +1154,11 @@ system.cpu1.kern.ipl_good::22                    1922      4.55%     52.28% # nu
 system.cpu1.kern.ipl_good::30                     351      0.83%     53.11% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::31                   19806     46.89%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::total                42236                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1870770703000     98.44%     98.44% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              347961500      0.02%     98.46% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              137588500      0.01%     98.46% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            29223568000      1.54%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1900479821000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::0            1870770905000     98.44%     98.44% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              347965500      0.02%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              137591500      0.01%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            29223562000      1.54%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1900480024000                       # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_used::0                 0.975465                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
@@ -1173,9 +1173,9 @@ system.cpu1.kern.mode_switch_good::kernel     0.480747                       # f
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::idle      0.108619                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::total     1.589366                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        6317362000      0.33%      0.33% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1020701000      0.05%      0.39% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1893129288000     99.61%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::kernel        6317215000      0.33%      0.33% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1021115000      0.05%      0.39% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1893129227000     99.61%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                    1451                       # number of times the context was actually changed
 system.cpu1.kern.syscall::2                         2      1.60%      1.60% # number of syscalls executed
 system.cpu1.kern.syscall::3                        13     10.40%     12.00% # number of syscalls executed
@@ -1200,37 +1200,37 @@ system.cpu1.kern.syscall::92                        2      1.60%     96.80% # nu
 system.cpu1.kern.syscall::132                       3      2.40%     99.20% # number of syscalls executed
 system.cpu1.kern.syscall::144                       1      0.80%    100.00% # number of syscalls executed
 system.cpu1.kern.syscall::total                   125                       # number of syscalls executed
-system.cpu1.memDep0.conflictingLoads           496033                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          413880                       # Number of conflicting stores.
-system.cpu1.memDep0.insertedLoads             2309588                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1512714                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.misc_regfile_reads                 594436                       # number of misc regfile reads
+system.cpu1.memDep0.conflictingLoads           495102                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          416651                       # Number of conflicting stores.
+system.cpu1.memDep0.insertedLoads             2307630                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1513195                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.misc_regfile_reads                 594453                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                255211                       # number of misc regfile writes
-system.cpu1.numCycles                        19640104                       # number of cpu cycles simulated
+system.cpu1.numCycles                        19640694                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.rename.RENAME:BlockCycles          522822                       # Number of cycles rename is blocking
-system.cpu1.rename.RENAME:CommittedMaps       7159583                       # Number of HB maps that are committed
-system.cpu1.rename.RENAME:IQFullEvents          32718                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.RENAME:IdleCycles          8500925                       # Number of cycles rename is idle
-system.cpu1.rename.RENAME:LSQFullEvents        256778                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RENAME:ROBFullEvents         15506                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.RENAME:RenameLookups      15473473                       # Number of register rename lookups that rename has made
-system.cpu1.rename.RENAME:RenamedInsts       12930857                       # Number of instructions processed by rename
-system.cpu1.rename.RENAME:RenamedOperands      8489204                       # Number of destination operands rename has renamed
-system.cpu1.rename.RENAME:RunCycles           2359874                       # Number of cycles rename is running
-system.cpu1.rename.RENAME:SquashCycles         305805                       # Number of cycles rename is squashing
-system.cpu1.rename.RENAME:UnblockCycles        801183                       # Number of cycles rename is unblocking
-system.cpu1.rename.RENAME:UndoneMaps          1329621                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.RENAME:fp_rename_lookups       171444                       # Number of floating rename lookups
-system.cpu1.rename.RENAME:int_rename_lookups     15302029                       # Number of integer rename lookups
-system.cpu1.rename.RENAME:serializeStallCycles      5653749                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RENAME:serializingInsts       515468                       # count of serializing insts renamed
-system.cpu1.rename.RENAME:skidInsts           2303190                       # count of insts added to the skid buffer
-system.cpu1.rename.RENAME:tempSerializingInsts        52722                       # count of temporary serializing insts renamed
-system.cpu1.rob.rob_reads                    29861070                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   24957765                       # The number of ROB writes
-system.cpu1.timesIdled                         194766                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.rename.RENAME:BlockCycles          523712                       # Number of cycles rename is blocking
+system.cpu1.rename.RENAME:CommittedMaps       7159591                       # Number of HB maps that are committed
+system.cpu1.rename.RENAME:IQFullEvents          32710                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.RENAME:IdleCycles          8501498                       # Number of cycles rename is idle
+system.cpu1.rename.RENAME:LSQFullEvents        256763                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RENAME:ROBFullEvents         15504                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.RENAME:RenameLookups      15470992                       # Number of register rename lookups that rename has made
+system.cpu1.rename.RENAME:RenamedInsts       12928500                       # Number of instructions processed by rename
+system.cpu1.rename.RENAME:RenamedOperands      8487290                       # Number of destination operands rename has renamed
+system.cpu1.rename.RENAME:RunCycles           2361527                       # Number of cycles rename is running
+system.cpu1.rename.RENAME:SquashCycles         305915                       # Number of cycles rename is squashing
+system.cpu1.rename.RENAME:UnblockCycles        801170                       # Number of cycles rename is unblocking
+system.cpu1.rename.RENAME:UndoneMaps          1327699                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.RENAME:fp_rename_lookups       171482                       # Number of floating rename lookups
+system.cpu1.rename.RENAME:int_rename_lookups     15299510                       # Number of integer rename lookups
+system.cpu1.rename.RENAME:serializeStallCycles      5652291                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RENAME:serializingInsts       515456                       # count of serializing insts renamed
+system.cpu1.rename.RENAME:skidInsts           2302074                       # count of insts added to the skid buffer
+system.cpu1.rename.RENAME:tempSerializingInsts        52719                       # count of temporary serializing insts renamed
+system.cpu1.rob.rob_reads                    29864417                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   24957573                       # The number of ROB writes
+system.cpu1.timesIdled                         194633                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1261,37 +1261,37 @@ system.iocache.ReadReq_mshr_misses                172                       # nu
 system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137704.871149                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137701.983202                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85701.289902                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5721912806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85698.425972                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5721792806                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3561059998                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3560940996                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs  6175.549096                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6175.644708                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs      64590068                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      64591068                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::1               41724                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41724                       # number of demand (read+write) accesses
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137612.376666                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137609.500623                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85608.810181                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85605.958058                       # average overall mshr miss latency
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5741738804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency         5741618804                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
@@ -1299,7 +1299,7 @@ system.iocache.demand_misses::0                     0                       # nu
 system.iocache.demand_misses::1                 41724                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41724                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3571941996                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3571822994                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
@@ -1313,14 +1313,14 @@ system.iocache.overall_accesses::0                  0                       # nu
 system.iocache.overall_accesses::1              41724                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41724                       # number of overall (read+write) accesses
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137612.376666                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137609.500623                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85608.810181                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85605.958058                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.overall_hits::0                      0                       # number of overall hits
 system.iocache.overall_hits::1                      0                       # number of overall hits
 system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency        5741738804                       # number of overall miss cycles
+system.iocache.overall_miss_latency        5741618804                       # number of overall miss cycles
 system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
@@ -1328,7 +1328,7 @@ system.iocache.overall_misses::0                    0                       # nu
 system.iocache.overall_misses::1                41724                       # number of overall misses
 system.iocache.overall_misses::total            41724                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3571941996                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3571822994                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
@@ -1342,55 +1342,55 @@ system.iocache.tagsinuse                     0.467303                       # Cy
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.warmup_cycle              1711286190000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41520                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               257294                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                42294                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           299588                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 55984.033368                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 838025.398663                       # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0               257283                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                42295                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           299578                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 55985.536569                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 837818.012343                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40323.668210                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0                   140895                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                    34518                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               175413                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency          6516485500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.452397                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.183856                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 116399                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                   7776                       # number of ReadExReq misses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40324.759412                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0                   140886                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1                    34517                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               175403                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency          6516548500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0            0.452408                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1            0.183899                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 116397                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                   7778                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             124175                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency     5007191500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       0.482619                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       2.935996                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_latency     5007327000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0       0.482640                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       2.935926                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_misses               124175                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0                1807450                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 343665                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2151115                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   52801.925207                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   3681603.345555                       # average ReadReq miss latency
+system.l2c.ReadReq_accesses::0                1807428                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 343680                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2151108                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   52801.503186                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   3683358.780376                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40018.264766                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40018.194749                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                    1503171                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     339301                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1842472                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           16066517000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.168347                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.012698                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   304279                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     4364                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               308643                       # number of ReadReq misses
+system.l2c.ReadReq_hits::0                    1503141                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     339318                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1842459                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           16066811000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.168354                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.012692                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   304287                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     4362                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               308649                       # number of ReadReq misses
 system.l2c.ReadReq_mshr_hits                       16                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency      12350717000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.170753                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.898046                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_latency      12350935500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.170758                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         0.898024                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 308627                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    840465500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_misses                 308633                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    840464000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.SCUpgradeReq_accesses::0               609                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::1               601                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total          1210                       # number of SCUpgradeReq accesses(hits+misses)
@@ -1414,120 +1414,120 @@ system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.886855                       # m
 system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_misses              1134                       # number of SCUpgradeReq MSHR misses
-system.l2c.UpgradeReq_accesses::0                2885                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                2883                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::1                1622                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            4507                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            4505                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_avg_miss_latency::0  5855.677656                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 12557.737628                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 12567.610063                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.987260                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0                     155                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                     349                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 504                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.991504                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0                     153                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                     350                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 503                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_miss_latency           15986000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0           0.946274                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.784834                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.946930                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1           0.784217                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_misses::0                  2730                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                  1273                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              4003                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency     160188000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0      1.387522                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      2.467941                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::1                  1272                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              4002                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency     160148000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0      1.388137                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1      2.467324                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses                4003                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                4002                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1532818498                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0               810405                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           810405                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   810405                       # number of Writeback hits
-system.l2c.Writeback_hits::total               810405                       # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency   1532817998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0               810507                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           810507                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   810507                       # number of Writeback hits
+system.l2c.Writeback_hits::total               810507                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          5.657708                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          5.658014                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 2064744                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  385959                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::0                 2064711                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  385975                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2450703                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    53682.394848                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    1860214.373970                       # average overall miss latency
+system.l2c.demand_accesses::total             2450686                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    53682.477822                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    1860243.780890                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40105.887912                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1644066                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      373819                       # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency  40106.149840                       # average overall mshr miss latency
+system.l2c.demand_hits::0                     1644027                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      373835                       # number of demand (read+write) hits
 system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2017885                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            22583002500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.203743                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.031454                       # miss rate for demand accesses
+system.l2c.demand_hits::total                 2017862                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            22583359500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.203750                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.031453                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    420678                       # number of demand (read+write) misses
+system.l2c.demand_misses::0                    420684                       # number of demand (read+write) misses
 system.l2c.demand_misses::1                     12140                       # number of demand (read+write) misses
 system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                432818                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                432824                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                        16                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       17357908500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0          0.209615                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.121368                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_latency       17358262500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          0.209622                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          1.121337                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  432802                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses                  432808                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.187715                       # Average percentage of cache occupancy
+system.l2c.occ_%::0                          0.187716                       # Average percentage of cache occupancy
 system.l2c.occ_%::1                          0.005740                       # Average percentage of cache occupancy
 system.l2c.occ_%::2                          0.351851                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                 12302.114841                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                   376.171902                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 23058.891094                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                2064744                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 385959                       # number of overall (read+write) accesses
+system.l2c.occ_blocks::0                 12302.143800                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                   376.171509                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                 23058.900248                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                2064711                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 385975                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2450703                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   53682.394848                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   1860214.373970                       # average overall miss latency
+system.l2c.overall_accesses::total            2450686                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   53682.477822                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   1860243.780890                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40105.887912                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40106.149840                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1644066                       # number of overall hits
-system.l2c.overall_hits::1                     373819                       # number of overall hits
+system.l2c.overall_hits::0                    1644027                       # number of overall hits
+system.l2c.overall_hits::1                     373835                       # number of overall hits
 system.l2c.overall_hits::2                          0                       # number of overall hits
-system.l2c.overall_hits::total                2017885                       # number of overall hits
-system.l2c.overall_miss_latency           22583002500                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.203743                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.031454                       # miss rate for overall accesses
+system.l2c.overall_hits::total                2017862                       # number of overall hits
+system.l2c.overall_miss_latency           22583359500                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.203750                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.031453                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   420678                       # number of overall misses
+system.l2c.overall_misses::0                   420684                       # number of overall misses
 system.l2c.overall_misses::1                    12140                       # number of overall misses
 system.l2c.overall_misses::2                        0                       # number of overall misses
-system.l2c.overall_misses::total               432818                       # number of overall misses
+system.l2c.overall_misses::total               432824                       # number of overall misses
 system.l2c.overall_mshr_hits                       16                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      17357908500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0         0.209615                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.121368                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency      17358262500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         0.209622                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         1.121337                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 432802                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   2373283998                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses                 432808                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   2373281998                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                        395562                       # number of replacements
-system.l2c.sampled_refs                        431632                       # Sample count of references to valid blocks.
+system.l2c.replacements                        395559                       # number of replacements
+system.l2c.sampled_refs                        431638                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     35737.177838                       # Cycle average of tags in use
-system.l2c.total_refs                         2442048                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     35737.215556                       # Cycle average of tags in use
+system.l2c.total_refs                         2442214                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                    9270445000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          121361                       # number of writebacks
+system.l2c.writebacks                          121360                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 838d9a364..a3d5d3586 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -10,12 +10,12 @@ type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/chips/pd/randd/dist/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -142,6 +142,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -440,6 +441,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -491,7 +493,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -511,7 +513,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -536,6 +538,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -567,6 +570,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
@@ -637,7 +641,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index bdb8a98f8..9021122e3 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Mar 15 2011 18:10:57
+M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip
+M5 started Mar 15 2011 18:10:59
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1866702838500 because m5_exit instruction encountered
+Exiting @ tick 1865724648500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index e3a6bbb06..2e169bdbb 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,103 +1,103 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  66360                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 311288                       # Number of bytes of host memory used
-host_seconds                                   799.45                       # Real time elapsed on the host
-host_tick_rate                             2334981918                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 180508                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 328492                       # Number of bytes of host memory used
+host_seconds                                   293.90                       # Real time elapsed on the host
+host_tick_rate                             6348189027                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    53051251                       # Number of instructions simulated
-sim_seconds                                  1.866703                       # Number of seconds simulated
-sim_ticks                                1866702838500                       # Number of ticks simulated
+sim_insts                                    53051011                       # Number of instructions simulated
+sim_seconds                                  1.865725                       # Number of seconds simulated
+sim_ticks                                1865724648500                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                  6623157                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              12789444                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect               40569                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect             601028                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           11937575                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 14339384                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                  1014923                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                8457250                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           1007675                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                  6620966                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              12786893                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect               40572                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect             600914                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           11937031                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 14338397                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  1014681                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches                8457274                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events           1008616                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples     89231545                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.630319                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.393269                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples     89227396                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.630345                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.393343                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     65110491     72.97%     72.97% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     10643752     11.93%     84.90% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      6057329      6.79%     91.68% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      2842358      3.19%     94.87% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      2098441      2.35%     97.22% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5       701144      0.79%     98.01% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       394504      0.44%     98.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       375851      0.42%     98.87% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      1007675      1.13%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0     65107231     72.97%     72.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1     10642774     11.93%     84.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2      6057714      6.79%     91.68% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3      2842201      3.19%     94.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4      2098462      2.35%     97.22% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5       700908      0.79%     98.01% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6       394479      0.44%     98.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7       375011      0.42%     98.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8      1008616      1.13%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total     89231545                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                  56244349                       # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total     89227396                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                  56244072                       # Number of instructions committed
 system.cpu.commit.COM:fp_insts                 324384                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls           744090                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts              52084301                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                   9107235                       # Number of loads committed
-system.cpu.commit.COM:membars                  227951                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   15496318                       # Number of memory references committed
+system.cpu.commit.COM:function_calls           744089                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts              52084090                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                   9107066                       # Number of loads committed
+system.cpu.commit.COM:membars                  227958                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                   15496059                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts            771510                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts       56244349                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls          667563                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts         8699299                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                    53051251                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              53051251                       # Number of Instructions Simulated
-system.cpu.cpi                               2.358137                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.358137                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses::0       215722                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       215722                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14725.540425                       # average LoadLockedReq miss latency
+system.cpu.commit.branchMispredicts            771395                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts       56244072                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls          667553                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts         8698928                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                    53051011                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              53051011                       # Number of Instructions Simulated
+system.cpu.cpi                               2.358035                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.358035                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses::0       215741                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       215741                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14722.823889                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11882.875143                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0        193471                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       193471                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency    327658000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11882.359679                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits::0        193488                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       193488                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency    327627000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_rate::0     0.103147                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0        22251                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22251                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits         4791                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    207475000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.080938                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0        22253                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22253                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits         4793                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency    207466000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.080930                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_misses        17460                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0         9297964                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9297964                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 22717.133732                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses::0         9298482                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9298482                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 22717.267883                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.439279                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.415740                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0             7723736                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7723736                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    35761948000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0       0.169309                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0           1574228                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1574228                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            490302                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency  24691226500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.116577                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_hits::0             7724340                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7724340                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    35760205500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0       0.169290                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0           1574142                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1574142                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            490275                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency  24689857000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.116564                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1083926                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency    905134500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0       219685                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       219685                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_mshr_misses         1083867                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency    905506500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses::0       219687                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       219687                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_avg_miss_latency::0        14000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency        11000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits::0         219682                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       219682                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::0         219684                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       219684                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_miss_latency        42000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_rate::0     0.000014                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_misses::0            3                       # number of StoreCondReq misses
@@ -107,287 +107,287 @@ system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.000014
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_misses            3                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::0        6154252                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6154252                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 29747.302403                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses::0        6154158                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6154158                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 29745.716858                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28091.080381                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28090.291333                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0            4299090                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4299090                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   55186065021                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0      0.301444                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0          1855162                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1855162                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1555538                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   8416761868                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.048686                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_hits::0            4298986                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4298986                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   55183421035                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0      0.301450                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0          1855172                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1855172                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          1555560                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   8416188367                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.048684                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         299624                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1235207998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  8963.151072                       # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_mshr_misses         299612                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1235453998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  8964.775985                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                   8.877326                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs             83371                       # number of cycles access was blocked
+system.cpu.dcache.avg_refs                   8.878146                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs             83356                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs    747266868                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs    747267867                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::0         15452216                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0         15452640                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15452216                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 26520.172107                       # average overall miss latency
+system.cpu.dcache.demand_accesses::total     15452640                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 26519.480729                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23929.737536                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0             12022826                       # number of demand (read+write) hits
+system.cpu.dcache.demand_avg_mshr_miss_latency 23929.561177                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits::0             12023326                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         12022826                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     90948013021                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0        0.221935                       # miss rate for demand accesses
+system.cpu.dcache.demand_hits::total         12023326                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     90943626535                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0        0.221924                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0            3429390                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0            3429314                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3429390                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            2045840                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  33107988368                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0     0.089537                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_misses::total        3429314                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            2045835                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency  33106045367                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0     0.089530                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1383550                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses          1383479                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.999991                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0            511.995490                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0        15452216                       # number of overall (read+write) accesses
+system.cpu.dcache.occ_blocks::0            511.995488                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0        15452640                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15452216                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 26520.172107                       # average overall miss latency
+system.cpu.dcache.overall_accesses::total     15452640                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0 26519.480729                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23929.737536                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23929.561177                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0            12022826                       # number of overall hits
+system.cpu.dcache.overall_hits::0            12023326                       # number of overall hits
 system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        12022826                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    90948013021                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0       0.221935                       # miss rate for overall accesses
+system.cpu.dcache.overall_hits::total        12023326                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    90943626535                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::0       0.221924                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0           3429390                       # number of overall misses
+system.cpu.dcache.overall_misses::0           3429314                       # number of overall misses
 system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3429390                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           2045840                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  33107988368                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0     0.089537                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_misses::total       3429314                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           2045835                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency  33106045367                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::0     0.089530                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1383550                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency   2140342498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_misses         1383479                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency   2140960498                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1400366                       # number of replacements
-system.cpu.dcache.sampled_refs                1400878                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                1400295                       # number of replacements
+system.cpu.dcache.sampled_refs                1400807                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                511.995490                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 12436050                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                511.995488                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 12436569                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               21271000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   832764                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       37803166                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          42143                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved        613837                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts        71397647                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          37493968                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           12849862                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         1515496                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts         134350                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        1084548                       # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses                  1235511                       # DTB accesses
-system.cpu.dtb.data_acv                           814                       # DTB access violations
-system.cpu.dtb.data_hits                     16593720                       # DTB hits
-system.cpu.dtb.data_misses                      46888                       # DTB misses
+system.cpu.dcache.writebacks                   832735                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       37803322                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          42125                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved        613661                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts        71395902                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          37491497                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           12847985                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         1515320                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts         134367                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        1084591                       # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses                  1236212                       # DTB accesses
+system.cpu.dtb.data_acv                           809                       # DTB access violations
+system.cpu.dtb.data_hits                     16593947                       # DTB hits
+system.cpu.dtb.data_misses                      46903                       # DTB misses
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                   910670                       # DTB read accesses
-system.cpu.dtb.read_acv                           580                       # DTB read access violations
-system.cpu.dtb.read_hits                     10006545                       # DTB read hits
-system.cpu.dtb.read_misses                      38646                       # DTB read misses
-system.cpu.dtb.write_accesses                  324841                       # DTB write accesses
-system.cpu.dtb.write_acv                          234                       # DTB write access violations
-system.cpu.dtb.write_hits                     6587175                       # DTB write hits
+system.cpu.dtb.read_accesses                   911157                       # DTB read accesses
+system.cpu.dtb.read_acv                           576                       # DTB read access violations
+system.cpu.dtb.read_hits                     10006781                       # DTB read hits
+system.cpu.dtb.read_misses                      38661                       # DTB read misses
+system.cpu.dtb.write_accesses                  325055                       # DTB write accesses
+system.cpu.dtb.write_acv                          233                       # DTB write access violations
+system.cpu.dtb.write_hits                     6587166                       # DTB write hits
 system.cpu.dtb.write_misses                      8242                       # DTB write misses
-system.cpu.fetch.Branches                    14339384                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                   8856318                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      14115387                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                454337                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                       72663163                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                43087                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                  884394                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.114621                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles            8856315                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches            7638080                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.580831                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples           90747041                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.800722                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.110012                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                    14338397                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                   8855922                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                      14113501                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                454413                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                       72660960                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                42720                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                  884189                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.114619                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles            8855919                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches            7635647                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        0.580841                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples           90742716                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.800736                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.110037                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 76631654     84.45%     84.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1046048      1.15%     85.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1970042      2.17%     87.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   921005      1.01%     88.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2984540      3.29%     92.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   648959      0.72%     92.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   776516      0.86%     93.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1074251      1.18%     94.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4694026      5.17%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 76629215     84.45%     84.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1044484      1.15%     85.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1968851      2.17%     87.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   922109      1.02%     88.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2984062      3.29%     92.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   649093      0.72%     92.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   777227      0.86%     93.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1074028      1.18%     94.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4693647      5.17%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             90747041                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                    164450                       # number of floating regfile reads
+system.cpu.fetch.rateDist::total             90742716                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                    164464                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                   166718                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses::0         8856318                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8856318                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14954.328072                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses::0         8855922                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8855922                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 14953.893584                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.426022                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::0             7816051                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7816051                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency    15556494000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0       0.117460                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0           1040267                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1040267                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits             47648                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency  11850308500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.112080                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.313504                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits::0             7815698                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7815698                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency    15555399000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::0       0.117461                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0           1040224                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1040224                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits             47681                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency  11849289500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.112077                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses          992619                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs        12375                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_mshr_misses          992543                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs 12554.545455                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                   7.875653                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                56                       # number of cycles access was blocked
+system.cpu.icache.avg_refs                   7.875900                       # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs                55                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs       693000                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs       690500                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::0          8856318                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::0          8855922                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8856318                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14954.328072                       # average overall miss latency
+system.cpu.icache.demand_accesses::total      8855922                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0 14953.893584                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11938.426022                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::0              7816051                       # number of demand (read+write) hits
+system.cpu.icache.demand_avg_mshr_miss_latency 11938.313504                       # average overall mshr miss latency
+system.cpu.icache.demand_hits::0              7815698                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7816051                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency     15556494000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0        0.117460                       # miss rate for demand accesses
+system.cpu.icache.demand_hits::total          7815698                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency     15555399000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::0        0.117461                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::0            1040267                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::0            1040224                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1040267                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits              47648                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency  11850308500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0     0.112080                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_misses::total        1040224                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits              47681                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency  11849289500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::0     0.112077                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses           992619                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses           992543                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.995726                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            509.811601                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0         8856318                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.995724                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            509.810451                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses::0         8855922                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8856318                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14954.328072                       # average overall miss latency
+system.cpu.icache.overall_accesses::total      8855922                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::0 14953.893584                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11938.426022                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11938.313504                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0             7816051                       # number of overall hits
+system.cpu.icache.overall_hits::0             7815698                       # number of overall hits
 system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total         7816051                       # number of overall hits
-system.cpu.icache.overall_miss_latency    15556494000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0       0.117460                       # miss rate for overall accesses
+system.cpu.icache.overall_hits::total         7815698                       # number of overall hits
+system.cpu.icache.overall_miss_latency    15555399000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::0       0.117461                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::0           1040267                       # number of overall misses
+system.cpu.icache.overall_misses::0           1040224                       # number of overall misses
 system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total       1040267                       # number of overall misses
-system.cpu.icache.overall_mshr_hits             47648                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency  11850308500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0     0.112080                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_misses::total       1040224                       # number of overall misses
+system.cpu.icache.overall_mshr_hits             47681                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency  11849289500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::0     0.112077                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses          992619                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses          992543                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                 991921                       # number of replacements
-system.cpu.icache.sampled_refs                 992432                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                 991845                       # number of replacements
+system.cpu.icache.sampled_refs                 992356                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                509.811601                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  7816050                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                509.810451                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  7815697                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle            24432989000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                       92                       # number of writebacks
-system.cpu.idleCycles                        34355081                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                  9120774                       # Number of branches executed
-system.cpu.iew.EXEC:nop                       3587033                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.456767                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     16683612                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                    6610329                       # Number of stores executed
+system.cpu.icache.writebacks                      176                       # number of writebacks
+system.cpu.idleCycles                        34353421                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                  9120660                       # Number of branches executed
+system.cpu.iew.EXEC:nop                       3587020                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     0.456799                       # Inst execution rate
+system.cpu.iew.EXEC:refs                     16683854                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                    6610322                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  35257849                       # num instructions consuming a value
-system.cpu.iew.WB:count                      56697227                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.757274                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                  35263910                       # num instructions consuming a value
+system.cpu.iew.WB:count                      56698677                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.757187                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  26699852                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.453208                       # insts written-back per cycle
-system.cpu.iew.WB:sent                       56799146                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts               837773                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                 9250897                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              10628246                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            1790214                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts            887997                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts              6943382                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts            65075490                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              10073283                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            520965                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts              57142461                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  61275                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                  26701367                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.453241                       # insts written-back per cycle
+system.cpu.iew.WB:sent                       56800727                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts               837733                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                 9250224                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts              10628233                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts            1789856                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts            887489                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts              6943615                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts            65074740                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              10073532                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            521272                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts              57143754                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                  61252                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 11738                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                1515496                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                557834                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                 11749                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                1515320                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                557849                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked       132328                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads          438613                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses         9607                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked       132030                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads          438592                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses         9600                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation        42661                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads        17611                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads      1521011                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores       554299                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents          42661                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       406369                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect         431404                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                 74886349                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40928930                       # number of integer regfile writes
-system.cpu.ipc                               0.424064                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.424064                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation        42579                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads        17615                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads      1521167                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores       554622                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents          42579                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       406353                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect         431380                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                 74888686                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40930439                       # number of integer regfile writes
+system.cpu.ipc                               0.424082                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.424082                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass         7281      0.01%      0.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        39527901     68.55%     68.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          62346      0.11%     68.67% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu        39529083     68.55%     68.56% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult          62345      0.11%     68.67% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     68.67% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatAdd         25607      0.04%     68.71% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     68.71% # Type of FU issued
@@ -415,15 +415,15 @@ system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     68.72%
 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     68.72% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     68.72% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     68.72% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       10424527     18.08%     86.80% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite       6659257     11.55%     98.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess       952873      1.65%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead       10424979     18.08%     86.80% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite       6659276     11.55%     98.35% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess       952821      1.65%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total         57663428                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                432905                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.007507                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total         57665028                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt                432817                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.007506                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             49058     11.33%     11.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu             49052     11.33%     11.33% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     11.33% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     11.33% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     11.33% # attempts to use FU when none available
@@ -452,51 +452,51 @@ system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     11.33% #
 system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     11.33% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     11.33% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     11.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead           267419     61.77%     73.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          116428     26.89%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead           267357     61.77%     73.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite          116408     26.90%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples     90747041                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.635430                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.200309                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples     90742716                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.635478                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.200410                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      62366198     68.73%     68.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      14061379     15.50%     84.22% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2       6226874      6.86%     91.08% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       3821617      4.21%     95.29% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       2539194      2.80%     98.09% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       1091409      1.20%     99.29% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6        462366      0.51%     99.80% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        128599      0.14%     99.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8         49405      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0      62361590     68.72%     68.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      14062254     15.50%     84.22% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2       6225923      6.86%     91.08% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3       3822183      4.21%     95.29% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4       2538846      2.80%     98.09% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5       1090826      1.20%     99.29% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6        462139      0.51%     99.80% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7        129609      0.14%     99.95% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8         49346      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total     90747041                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.460931                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                  341243                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads              667907                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses       325691                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes             334133                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses               57747809                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          205867710                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses     56371536                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes          69251365                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                   59448706                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                  57663428                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             2039751                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined         8060465                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued             28817                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved        1372188                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined      4168617                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total     90742716                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     0.460966                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                  341264                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads              667947                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses       325705                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes             334327                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses               57749300                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          205866504                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses     56372972                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes          69249578                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                   59448335                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                  57665028                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded             2039385                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined         8059661                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued             28864                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved        1371832                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined      4166065                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                 1294583                       # ITB accesses
-system.cpu.itb.fetch_acv                          923                       # ITB acv
-system.cpu.itb.fetch_hits                     1255493                       # ITB hits
-system.cpu.itb.fetch_misses                     39090                       # ITB misses
+system.cpu.itb.fetch_accesses                 1294620                       # ITB accesses
+system.cpu.itb.fetch_acv                          913                       # ITB acv
+system.cpu.itb.fetch_hits                     1255661                       # ITB hits
+system.cpu.itb.fetch_misses                     38959                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -512,8 +512,8 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4176      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175591     91.19%     93.39% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6793      3.53%     96.92% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175578     91.19%     93.39% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6792      3.53%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
@@ -521,42 +521,42 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.93% # nu
 system.cpu.kern.callpal::rti                     5221      2.71%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192561                       # number of callpals executed
+system.cpu.kern.callpal::total                 192547                       # number of callpals executed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     211718                       # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce                     6427                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count::0                    74916     40.95%     40.95% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     238      0.13%     41.08% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1890      1.03%     42.11% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105896     57.89%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182940                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73549     49.29%     49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      238      0.16%     49.45% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1890      1.27%     50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73550     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149227                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1827171336500     97.88%     97.88% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                97547000      0.01%     97.89% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               392033000      0.02%     97.91% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             39041048500      2.09%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1866701965000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981753                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.hwrei                     211704                       # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce                     6424                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count::0                    74914     40.95%     40.95% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     239      0.13%     41.08% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1889      1.03%     42.12% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105885     57.88%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182927                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73547     49.29%     49.29% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      239      0.16%     49.45% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1889      1.27%     50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73548     49.29%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149223                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1826194216500     97.88%     97.88% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                97924500      0.01%     97.89% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               391796500      0.02%     97.91% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             39039837500      2.09%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1865723775000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981752                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694549                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694603                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.mode_good::kernel                1906                      
 system.cpu.kern.mode_good::user                  1736                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch::kernel              5956                       # number of protection mode switches
+system.cpu.kern.mode_switch::kernel              5959                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1736                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2107                       # number of protection mode switches
-system.cpu.kern.mode_switch_good::kernel     0.320013                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch::idle                2104                       # number of protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.319852                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080683                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      1.400697                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        30086574000      1.61%      1.61% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           3015068000      0.16%      1.77% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1833600315000     98.23%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.080798                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      1.400651                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        30091122000      1.61%      1.61% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           3014546000      0.16%      1.77% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1832618099000     98.23%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
@@ -589,37 +589,37 @@ system.cpu.kern.syscall::132                        4      1.23%     98.77% # nu
 system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
 system.cpu.kern.syscall::total                    326                       # number of syscalls executed
-system.cpu.memDep0.conflictingLoads           3018201                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2591237                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             10628246                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6943382                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                 1993439                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 949389                       # number of misc regfile writes
-system.cpu.numCycles                        125102122                       # number of cpu cycles simulated
+system.cpu.memDep0.conflictingLoads           3018997                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2591949                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             10628233                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6943615                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                 1993395                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 949366                       # number of misc regfile writes
+system.cpu.numCycles                        125096137                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         13297534                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       38227478                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         1065628                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          39060011                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        1661101                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents          58596                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups       82213921                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts        67573183                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands     45293711                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           12514369                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         1515496                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        4654173                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps           7066231                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups       474968                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups     81738953                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles     19705456                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts      1694142                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           11744700                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts       247271                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    152916375                       # The number of ROB reads
-system.cpu.rob.rob_writes                   131403689                       # The number of ROB writes
-system.cpu.timesIdled                         1310957                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:BlockCycles         13296621                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps       38227330                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents         1065712                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          39057588                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        1661249                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents          58583                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups       82211156                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts        67570562                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands     45292482                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           12512523                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         1515320                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles        4654421                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps           7065150                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups       475144                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups     81736012                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles     19706241                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts      1694164                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           11744747                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts       247277                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    152910637                       # The number of ROB reads
+system.cpu.rob.rob_writes                   131402179                       # The number of ROB writes
+system.cpu.timesIdled                         1310794                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -650,37 +650,37 @@ system.iocache.ReadReq_mshr_misses                173                       # nu
 system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137707.205574                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137705.665335                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85703.600260                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5722009806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85702.060021                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5721945806                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3561155998                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3561091998                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs  6170.205040                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6170.968690                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs      64639068                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      64647068                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::1               41725                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137614.087573                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137612.553721                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85610.497208                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85608.963355                       # average overall mshr miss latency
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5741947804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency         5741883804                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
@@ -688,7 +688,7 @@ system.iocache.demand_misses::0                     0                       # nu
 system.iocache.demand_misses::1                 41725                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3572097996                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3572033996                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
@@ -696,20 +696,20 @@ system.iocache.demand_mshr_misses               41725                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.081528                       # Average percentage of cache occupancy
-system.iocache.occ_blocks::1                 1.304443                       # Average occupied blocks per context
+system.iocache.occ_%::1                      0.081046                       # Average percentage of cache occupancy
+system.iocache.occ_blocks::1                 1.296738                       # Average occupied blocks per context
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137614.087573                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137612.553721                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85610.497208                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85608.963355                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.overall_hits::0                      0                       # number of overall hits
 system.iocache.overall_hits::1                      0                       # number of overall hits
 system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency        5741947804                       # number of overall miss cycles
+system.iocache.overall_miss_latency        5741883804                       # number of overall miss cycles
 system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
@@ -717,7 +717,7 @@ system.iocache.overall_misses::0                    0                       # nu
 system.iocache.overall_misses::1                41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3572097996                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3572033996                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
@@ -727,145 +727,145 @@ system.iocache.overall_mshr_uncacheable_misses            0
 system.iocache.replacements                     41685                       # number of replacements
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     1.304443                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.296738                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.warmup_cycle              1711281262000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41512                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               300850                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           300850                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52488.966283                       # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0               300822                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           300822                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 52489.461538                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40339.814538                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0                   183845                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               183845                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency          6141471500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.388915                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 117005                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             117005                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency     4719960000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       0.388915                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40340.521368                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0                   183822                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               183822                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency          6141267000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0            0.388934                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 117000                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             117000                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency     4719841000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0       0.388934                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               117005                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0                2092533                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2092533                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   52046.060634                       # average ReadReq miss latency
+system.l2c.ReadExReq_mshr_misses               117000                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0                2092337                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2092337                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   52046.096131                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40015.025123                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40015.012554                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                    1785047                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1785047                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           16003435000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.146944                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   307486                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               307486                       # number of ReadReq misses
+system.l2c.ReadReq_hits::0                    1784860                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1784860                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           16002977500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.146954                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   307477                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               307477                       # number of ReadReq misses
 system.l2c.ReadReq_mshr_hits                        1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency      12304020000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.146944                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_latency      12303656000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.146953                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 307485                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    810593000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_misses                 307476                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    810924000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.SCUpgradeReq_accesses::0                 3                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             3                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_hits::0                     3                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
-system.l2c.UpgradeReq_accesses::0                  25                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              25                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0        21400                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_accesses::0                  22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 22928.571429                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency        44000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0                      10                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  10                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_avg_mshr_miss_latency 44285.714286                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0                       8                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   8                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_miss_latency             321000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0           0.600000                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                    15                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                15                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency        660000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.600000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.636364                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                    14                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                14                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency        620000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.636364                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses                  15                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                  14                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1115666998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0               832856                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           832856                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   832856                       # number of Writeback hits
-system.l2c.Writeback_hits::total               832856                       # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency   1115890498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0               832911                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           832911                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   832911                       # number of Writeback hits
+system.l2c.Writeback_hits::total               832911                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          5.629154                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          5.628523                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 2393383                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::0                 2393159                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2393383                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    52168.141374                       # average overall miss latency
+system.l2c.demand_accesses::total             2393159                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    52168.302405                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40104.548988                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1968892                       # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency  40104.733837                       # average overall mshr miss latency
+system.l2c.demand_hits::0                     1968682                       # number of demand (read+write) hits
 system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1968892                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            22144906500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.177360                       # miss rate for demand accesses
+system.l2c.demand_hits::total                 1968682                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            22144244500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.177371                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    424491                       # number of demand (read+write) misses
+system.l2c.demand_misses::0                    424477                       # number of demand (read+write) misses
 system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                424491                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                424477                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       17023980000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0          0.177360                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_latency       17023497000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          0.177371                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  424490                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses                  424476                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.186942                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.344679                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                 12251.423039                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 22588.894949                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                2393383                       # number of overall (read+write) accesses
+system.l2c.occ_%::0                          0.186906                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.344678                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                 12249.050591                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 22588.829074                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                2393159                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2393383                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   52168.141374                       # average overall miss latency
+system.l2c.overall_accesses::total            2393159                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   52168.302405                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40104.548988                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40104.733837                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1968892                       # number of overall hits
+system.l2c.overall_hits::0                    1968682                       # number of overall hits
 system.l2c.overall_hits::1                          0                       # number of overall hits
-system.l2c.overall_hits::total                1968892                       # number of overall hits
-system.l2c.overall_miss_latency           22144906500                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.177360                       # miss rate for overall accesses
+system.l2c.overall_hits::total                1968682                       # number of overall hits
+system.l2c.overall_miss_latency           22144244500                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.177371                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   424491                       # number of overall misses
+system.l2c.overall_misses::0                   424477                       # number of overall misses
 system.l2c.overall_misses::1                        0                       # number of overall misses
-system.l2c.overall_misses::total               424491                       # number of overall misses
+system.l2c.overall_misses::total               424477                       # number of overall misses
 system.l2c.overall_mshr_hits                        1                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      17023980000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0         0.177360                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency      17023497000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         0.177371                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::1              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 424490                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   1926259998                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses                 424476                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   1926814498                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                        390992                       # number of replacements
-system.l2c.sampled_refs                        423734                       # Sample count of references to valid blocks.
+system.l2c.replacements                        390976                       # number of replacements
+system.l2c.sampled_refs                        423725                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     34840.317988                       # Cycle average of tags in use
-system.l2c.total_refs                         2385264                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     34837.879666                       # Cycle average of tags in use
+system.l2c.total_refs                         2384946                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                    5637119000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          117628                       # number of writebacks
+system.l2c.writebacks                          117616                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
new file mode 100644
index 000000000..c2ce6a46c
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -0,0 +1,950 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+boot_cpu_frequency=500
+boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
+init_param=0
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
+load_addr_mask=268435455
+machine_type=RealView_PBX
+mem_mode=timing
+physmem=system.physmem
+readfile=tests/halt.sh
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+
+[system.bridge]
+type=Bridge
+delay=50000
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:134217727
+nack_delay=4000
+req_size_a=16
+req_size_b=16
+resp_size_a=16
+resp_size_b=16
+write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache interrupts itb tracer
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu.interrupts
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[4]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[3]
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.diskmem]
+type=PhysicalMemory
+file=/chips/pd/randd/dist/disks/ael-arm.ext2
+latency=30000
+latency_var=0
+null=false
+range=134217728:268435455
+zero=false
+port=system.membus.port[1]
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:134217727
+assoc=8
+block_size=64
+forward_snoops=false
+hash_delay=1
+is_top_level=false
+latency=50000
+max_miss_count=0
+mshrs=20
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[25]
+mem_side=system.membus.port[5]
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[6]
+
+[system.membus]
+type=Bus
+children=badaddr_responder
+block_size=64
+bus_id=1
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+default=system.membus.badaddr_responder.pio
+port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+pio_addr=0
+pio_latency=1000
+pio_size=8
+platform=system.realview
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=true
+port=system.membus.port[2]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+intrctrl=system.intrctrl
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268451840
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[20]
+
+[system.realview.cf0_fake]
+type=IsaFake
+pio_addr=402653184
+pio_latency=1000
+pio_size=4095
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[24]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=41667
+gic=system.realview.gic
+int_num=55
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pio_addr=268566528
+pio_latency=10000
+platform=system.realview
+system=system
+vnc=system.vncserver
+dma=system.iobus.port[26]
+pio=system.iobus.port[5]
+
+[system.realview.dmac_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268632064
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[8]
+
+[system.realview.flash_fake]
+type=IsaFake
+pio_addr=1073741824
+pio_latency=1000
+pio_size=67108864
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[23]
+
+[system.realview.gic]
+type=Gic
+cpu_addr=520093952
+cpu_pio_delay=10000
+dist_addr=520097792
+dist_pio_delay=10000
+it_lines=128
+platform=system.realview
+system=system
+pio=system.membus.port[3]
+
+[system.realview.gpio0_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268513280
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[15]
+
+[system.realview.gpio1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268517376
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[16]
+
+[system.realview.gpio2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268521472
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[17]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=52
+is_mouse=false
+pio_addr=268460032
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=53
+is_mouse=true
+pio_addr=268464128
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+pio_addr=520101888
+pio_latency=1000
+pio_size=4095
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.port[4]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268455936
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[21]
+
+[system.realview.realview_io]
+type=RealViewCtrl
+pio_addr=268435456
+pio_latency=1000
+platform=system.realview
+proc_id=201326592
+system=system
+pio=system.iobus.port[2]
+
+[system.realview.rtc_fake]
+type=AmbaFake
+amba_id=266289
+ignore_access=false
+pio_addr=268529664
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[22]
+
+[system.realview.sci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268492800
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[19]
+
+[system.realview.smc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=269357056
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[12]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=true
+pio_addr=268439552
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[13]
+
+[system.realview.ssp_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268488704
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[18]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=36
+int_num1=36
+pio_addr=268505088
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[3]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=37
+int_num1=37
+pio_addr=268509184
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[4]
+
+[system.realview.uart]
+type=Pl011
+end_on_eot=false
+gic=system.realview.gic
+int_delay=100000
+int_num=44
+pio_addr=268472320
+pio_latency=1000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.port[1]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268476416
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[9]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268480512
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[10]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268484608
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268500992
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[14]
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+number=0
+port=5900
+
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr
new file mode 100755
index 000000000..701e9297b
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr
@@ -0,0 +1,43 @@
+warn: Sockets disabled, not accepting vnc client connections
+For more information see: http://www.m5sim.org/warn/af6a84f6
+warn: Sockets disabled, not accepting terminal connections
+For more information see: http://www.m5sim.org/warn/8742226b
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: The clidr register always reports 0 caches.
+For more information see: http://www.m5sim.org/warn/23a3c326
+warn: The csselr register isn't implemented.
+For more information see: http://www.m5sim.org/warn/c0c486b8
+warn: Need to flush all TLBs in MP
+For more information see: http://www.m5sim.org/warn/6cccf999
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: The ccsidr register isn't implemented and always reads as 0.
+For more information see: http://www.m5sim.org/warn/2c4acb9c
+warn: 	instruction 'mcr dccimvac' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: Need to flush all TLBs in MP
+For more information see: http://www.m5sim.org/warn/6cccf999
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr dccmvau' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr icimvau' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+For more information see: http://www.m5sim.org/warn/7998f2ea
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+For more information see: http://www.m5sim.org/warn/7998f2ea
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: Need to flush all TLBs in MP
+For more information see: http://www.m5sim.org/warn/6cccf999
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+hack: be nice to actually delete the event here
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
new file mode 100755
index 000000000..b92737e2d
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -0,0 +1,16 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Mar 11 2011 20:10:37
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:12:00
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 84388283500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
new file mode 100644
index 000000000..2142ffa48
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -0,0 +1,750 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                 136897                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 384172                       # Number of bytes of host memory used
+host_seconds                                   379.57                       # Real time elapsed on the host
+host_tick_rate                              222327398                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                    51961461                       # Number of instructions simulated
+sim_seconds                                  0.084388                       # Number of seconds simulated
+sim_ticks                                 84388283500                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                  9710586                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              12489985                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect              157419                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect             644152                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           11960647                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 14006556                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                   818238                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches                8358835                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events            766788                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples     96225527                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.541277                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.325518                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0     74314309     77.23%     77.23% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1     10868177     11.29%     88.52% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2      3539344      3.68%     92.20% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3      1575243      1.64%     93.84% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4      3605097      3.75%     97.59% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5       765856      0.80%     98.38% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6       506916      0.53%     98.91% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7       283797      0.29%     99.20% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8       766788      0.80%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total     96225527                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                  52084641                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                   6017                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls           529465                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts              42494142                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                   9208604                       # Number of loads committed
+system.cpu.commit.COM:membars                       3                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                   16292498                       # Number of memory references committed
+system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts            712712                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts       52084641                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls         2962577                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts        21317023                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                    51961461                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              51961461                       # Number of Instructions Simulated
+system.cpu.cpi                               3.248111                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.248111                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses::0       110709                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       110709                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15013.262803                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11890.992284                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency          inf                       # average LoadLockedReq mshr uncacheable latency
+system.cpu.dcache.LoadLockedReq_hits::0        104187                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       104187                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency     97916500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.058911                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0         6522                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         6522                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits          949                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency     66268500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.050339                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses         5573                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency    312424000                       # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_accesses::0        10044139                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     10044139                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 14270.972361                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13253.335400                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_hits::0             9552480                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         9552480                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency     7016452000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0       0.048950                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0            491659                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        491659                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            243263                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency   3292075500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.024730                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses          248396                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency  38191881500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses::0       104612                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       104612                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::0         104612                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       104612                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::0        6670215                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6670215                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 39957.308282                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38553.884427                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_hits::0            4625539                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4625539                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   81699749268                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0      0.306538                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0          2044676                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2044676                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          1874256                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   6570352984                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.025549                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         170420                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency    939854183                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  7310.688742                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 21687.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                  34.045188                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs               906                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              24                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs      6623484                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       520500                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses::0         16714354                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     16714354                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 34978.108676                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23548.356519                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits::0             14178019                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         14178019                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     88716201268                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0        0.151746                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses::0            2536335                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2536335                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            2117519                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency   9862428484                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0     0.025057                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           418816                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.999523                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0            511.755643                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0        16714354                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     16714354                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0 34978.108676                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23548.356519                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits::0            14178019                       # number of overall hits
+system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::total        14178019                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    88716201268                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::0       0.151746                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses::0           2536335                       # number of overall misses
+system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2536335                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           2117519                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency   9862428484                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::0     0.025057                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          418816                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency  39131735683                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements                 422122                       # number of replacements
+system.cpu.dcache.sampled_refs                 422634                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse                511.755643                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14388654                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               48260000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   390579                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       54500037                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          71855                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved       1270879                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts        84249767                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          24736930                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           15841745                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         3334409                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts         234983                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        1146787                       # Number of cycles decode is unblocking
+system.cpu.dtb.accesses                      36041317                       # DTB accesses
+system.cpu.dtb.align_faults                      1606                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries                     2757                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid               33670                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits                          35961278                       # DTB hits
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.misses                           80039                       # DTB misses
+system.cpu.dtb.perms_faults                       987                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults                   1022                       # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses                 28355137                       # DTB read accesses
+system.cpu.dtb.read_hits                     28285868                       # DTB read hits
+system.cpu.dtb.read_misses                      69269                       # DTB read misses
+system.cpu.dtb.write_accesses                 7686180                       # DTB write accesses
+system.cpu.dtb.write_hits                     7675410                       # DTB write hits
+system.cpu.dtb.write_misses                     10770                       # DTB write misses
+system.cpu.fetch.Branches                    14006556                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                   6998275                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                      17468426                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                310113                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                       71954338                       # Number of instructions fetch has processed
+system.cpu.fetch.ItlbSquashes                    4839                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.MiscStallCycles                24771                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                 1293063                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       7917                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.branchRate                  0.082989                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles            6996896                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches           10528824                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        0.426329                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples           99559908                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.876249                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.150340                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 82110011     82.47%     82.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1333573      1.34%     83.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1775516      1.78%     85.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1526454      1.53%     87.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4859277      4.88%     92.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   919627      0.92%     92.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   887823      0.89%     93.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   767860      0.77%     94.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  5379767      5.40%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total             99559908                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                      5295                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     1908                       # number of floating regfile writes
+system.cpu.icache.ReadReq_accesses::0         6998182                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      6998182                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 14604.698564                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12005.361734                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_hits::0             6432138                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         6432138                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency     8266901994                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::0       0.080884                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0            566044                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        566044                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits             56788                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency   6113802495                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.072770                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses          509256                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable_latency      4968000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.avg_blocked_cycles::no_mshrs  6198.435115                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs                  12.630486                       # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs               131                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs       811995                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses::0          6998182                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      6998182                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0 14604.698564                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12005.361734                       # average overall mshr miss latency
+system.cpu.icache.demand_hits::0              6432138                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          6432138                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency      8266901994                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::0        0.080884                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_misses::0             566044                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         566044                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits              56788                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency   6113802495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::0     0.072770                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses           509256                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.968631                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            495.939326                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses::0         6998182                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      6998182                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::0 14604.698564                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12005.361734                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits::0             6432138                       # number of overall hits
+system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::total         6432138                       # number of overall hits
+system.cpu.icache.overall_miss_latency     8266901994                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::0       0.080884                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_misses::0            566044                       # number of overall misses
+system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::total        566044                       # number of overall misses
+system.cpu.icache.overall_mshr_hits             56788                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency   6113802495                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::0     0.072770                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses          509256                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency      4968000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements                 508743                       # number of replacements
+system.cpu.icache.sampled_refs                 509255                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse                495.939326                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  6432138                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle             6683845000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                    41856                       # number of writebacks
+system.cpu.idleCycles                        69216660                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                 10300528                       # Number of branches executed
+system.cpu.iew.EXEC:nop                        233998                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     0.477549                       # Inst execution rate
+system.cpu.iew.EXEC:refs                     36776263                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                    7992235                       # Number of stores executed
+system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
+system.cpu.iew.WB:consumers                  64109547                       # num instructions consuming a value
+system.cpu.iew.WB:count                      62439853                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.508921                       # average fanout of values written-back
+system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers                  32626666                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.369956                       # insts written-back per cycle
+system.cpu.iew.WB:sent                       79765366                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts               803947                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                21361717                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts              14069931                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts            4021819                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts            473480                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts              9383175                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts            75615816                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              28784028                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1481918                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts              80599112                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                  30204                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents                 45946                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                3334409                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                259259                       # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked         8096                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads          314225                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses        20180                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation       524894                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads     17006252                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads      4861327                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores      2299281                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents         524894                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       291334                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect         512613                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                187216676                       # number of integer regfile reads
+system.cpu.int_regfile_writes                45171594                       # number of integer regfile writes
+system.cpu.ipc                               0.307871                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.307871                       # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass      2392951      2.92%      2.92% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu        42044414     51.22%     54.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult          91848      0.11%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu             12      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            7      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc          869      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            7      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     54.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead       29326853     35.73%     89.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite       8224069     10.02%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total         82081030                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt               4843845                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.059013                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu              4773      0.10%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                1      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead          4516251     93.24%     93.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite          322820      6.66%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples     99559908                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.824439                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.384503                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0      62623940     62.90%     62.90% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      16850481     16.92%     79.83% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2       7354837      7.39%     87.21% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3       4227768      4.25%     91.46% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4       6061654      6.09%     97.55% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5       1452072      1.46%     99.01% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6        668981      0.67%     99.68% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7        244691      0.25%     99.92% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8         75484      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total     99559908                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     0.486330                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                    8335                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads               15849                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses         6220                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes               8867                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses               84523589                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          268809983                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses     62433633                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes          98520423                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                   71330415                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                  82081030                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded             4051403                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined        22670381                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued            180259                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved        1088826                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined     31630143                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses                       7013299                       # DTB accesses
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries                     1597                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid               33670                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits                           7005382                       # DTB hits
+system.cpu.itb.inst_accesses                  7013299                       # ITB inst accesses
+system.cpu.itb.inst_hits                      7005382                       # ITB inst hits
+system.cpu.itb.inst_misses                       7917                       # ITB inst misses
+system.cpu.itb.misses                            7917                       # DTB misses
+system.cpu.itb.perms_faults                      6664                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
+system.cpu.memDep0.conflictingLoads             10842                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores            21645                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             14069931                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             9383175                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                92602547                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 661893                       # number of misc regfile writes
+system.cpu.numCycles                        168776568                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.rename.RENAME:BlockCycles         32961979                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps       36893255                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents          568385                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          26505270                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        2459966                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents         448573                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups      208179443                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts        80158855                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands     58599384                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           14253451                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         3334409                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles        5274094                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps          21706128                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups        46818                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    208132625                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles     17230705                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts       870043                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           14712923                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts       727497                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    167920116                       # The number of ROB reads
+system.cpu.rob.rob_writes                   150187680                       # The number of ROB writes
+system.cpu.timesIdled                         1086772                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
+system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
+system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
+system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                    0                       # number of overall misses
+system.iocache.overall_misses::total                0                       # number of overall misses
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.replacements                         0                       # number of replacements
+system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse                            0                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
+system.iocache.writebacks                           0                       # number of writebacks
+system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency          inf                       # average LoadLockedReq mshr uncacheable latency
+system.l2c.LoadLockedReq_mshr_uncacheable_latency    234163500                       # number of LoadLockedReq MSHR uncacheable cycles
+system.l2c.ReadExReq_accesses::0               168750                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           168750                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 52449.907829                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40012.010079                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0                    60799                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                60799                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency          5662020000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0            0.639710                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 107951                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             107951                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency     4319336500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0       0.639710                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses               107951                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0                 760723                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 115478                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             876201                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   52673.934298                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   6776716.981132                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 6829390.915430                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40041.287971                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits::0                     740267                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     115319                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 855586                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency            1077498000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.026890                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.001377                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.028267                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                    20456                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                      159                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                20615                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits                       40                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency        823849500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.027047                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         0.178172                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.205219                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses                  20575                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency  28940574500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses::0                1755                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1755                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0   785.423926                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.580720                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0                      33                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  33                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_latency            1352500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0           0.981197                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                  1722                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1722                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency      68881000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.981197                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses                1722                       # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency    746022447                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0               432435                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           432435                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   432435                       # number of Writeback hits
+system.l2c.Writeback_hits::total               432435                       # number of Writeback hits
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_refs                          8.330108                       # Average number of references to valid blocks.
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.demand_accesses::0                  929473                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  115478                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1044951                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    52485.596580                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    42386905.660377                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 42439391.256957                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency  40016.697011                       # average overall mshr miss latency
+system.l2c.demand_hits::0                      801066                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      115319                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  916385                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency             6739518000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.138150                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.001377                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.139527                       # miss rate for demand accesses
+system.l2c.demand_misses::0                    128407                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                       159                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                128566                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                        40                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency        5143186000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          0.138278                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          1.112991                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      1.251270                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                  128526                       # number of demand (read+write) MSHR misses
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.occ_%::0                          0.099103                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.480856                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                  6494.821877                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 31513.354871                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                 929473                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 115478                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1044951                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   52485.596580                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   42386905.660377                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 42439391.256957                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40016.697011                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_hits::0                     801066                       # number of overall hits
+system.l2c.overall_hits::1                     115319                       # number of overall hits
+system.l2c.overall_hits::total                 916385                       # number of overall hits
+system.l2c.overall_miss_latency            6739518000                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.138150                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.001377                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.139527                       # miss rate for overall accesses
+system.l2c.overall_misses::0                   128407                       # number of overall misses
+system.l2c.overall_misses::1                      159                       # number of overall misses
+system.l2c.overall_misses::total               128566                       # number of overall misses
+system.l2c.overall_mshr_hits                       40                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency       5143186000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         0.138278                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         1.112991                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     1.251270                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                 128526                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency  29686596947                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.replacements                         94872                       # number of replacements
+system.l2c.sampled_refs                        127034                       # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse                     38008.176748                       # Cycle average of tags in use
+system.l2c.total_refs                         1058207                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                           87774                       # number of writebacks
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
new file mode 100644
index 000000000..9541cca97
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
@@ -0,0 +1 @@
+build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 passed.
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
new file mode 100644
index 000000000..2766f586d
Binary files /dev/null and b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal differ
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
index 9285fee06..a74b5cf43 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -115,6 +115,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -413,6 +414,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -448,6 +450,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -493,9 +496,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
index 09f9f450a..69008c385 100755
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 21 2011 14:34:16
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 15:32:42
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 21:03:35
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -28,4 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 56054651500 because target called exit()
+Exiting @ tick 45750115000 because target called exit()
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 1e441ade1..012c275ff 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,130 +1,142 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  61070                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 389424                       # Number of bytes of host memory used
-host_seconds                                  1493.21                       # Real time elapsed on the host
-host_tick_rate                               37539692                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 113142                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 388016                       # Number of bytes of host memory used
+host_seconds                                   806.51                       # Real time elapsed on the host
+host_tick_rate                               56726347                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    91190126                       # Number of instructions simulated
-sim_seconds                                  0.056055                       # Number of seconds simulated
-sim_ticks                                 56054651500                       # Number of ticks simulated
+sim_insts                                    91249480                       # Number of instructions simulated
+sim_seconds                                  0.045750                       # Number of seconds simulated
+sim_ticks                                 45750115000                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 20717897                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              22133091                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            1885129                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           22369140                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 22369140                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               18672384                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events            365813                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                 25060777                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              26802034                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect               13379                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect            1583014                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           23911601                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 29845348                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                    62467                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches               18706972                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events            599512                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    109380669                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.833810                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.220279                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples     85858585                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.062935                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.459577                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     55493600     50.73%     50.73% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     34988153     31.99%     82.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      8951302      8.18%     90.91% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      6346851      5.80%     96.71% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      1763725      1.61%     98.32% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5       198423      0.18%     98.50% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       611708      0.56%     99.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       661094      0.60%     99.67% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8       365813      0.33%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0     40879742     47.61%     47.61% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1     22675219     26.41%     74.02% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2      9677073     11.27%     85.29% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3      7600715      8.85%     94.15% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4      2662481      3.10%     97.25% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5       219814      0.26%     97.50% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6       922714      1.07%     98.58% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7       621315      0.72%     99.30% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8       599512      0.70%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    109380669                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                  91202735                       # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total     85858585                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                  91262089                       # Number of instructions committed
 system.cpu.commit.COM:fp_insts                     48                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts              72483223                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  22585492                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   27330336                       # Number of memory references committed
+system.cpu.commit.COM:function_calls            56148                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts              72532978                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                  22575791                       # Number of loads committed
+system.cpu.commit.COM:membars                    3888                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                   27322459                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts           1941617                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts       91202735                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls          544722                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        11836562                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                    91190126                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              91190126                       # Number of Instructions Simulated
-system.cpu.cpi                               1.229402                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.229402                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses           23356359                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  5257.244166                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2204.745551                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               22405801                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     4997315500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.040698                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               950558                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits             47017                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   1992078000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.038685                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          903541                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses           4738868                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 21505.165872                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20098.081505                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits               4602377                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    2935261595                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.028802                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              136491                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits            89917                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency    936048048                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009828                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          46574                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  2906.794309                       # average number of cycles each access was blocked
+system.cpu.commit.branchMispredicts           1602069                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts       91262089                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls          554321                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts        39090054                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                    91249480                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              91249480                       # Number of Instructions Simulated
+system.cpu.cpi                               1.002748                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.002748                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses         6707                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 17642.857143                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits             6700                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency       123500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.001044                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses              7                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits            7                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.ReadReq_accesses           24501880                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  5328.400499                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2255.904510                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               23546851                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency     5088777000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.038978                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               955029                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits             51059                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency   2039270000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.036894                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses          903970                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses          5711                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits              5711                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 24088.951664                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22495.719344                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits               4561444                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    4180324405                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.036650                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              173537                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits           127274                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   1040719464                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009770                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses          46263                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  2889.691936                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  28.426220                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs              6009                       # number of cycles access was blocked
+system.cpu.dcache.avg_refs                  29.593485                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs              7453                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs     17466927                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs     21536874                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            28095227                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  7297.350069                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  3081.864877                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                27008178                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency      7932577095                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.038692                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1087049                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits             136934                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   2928126048                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.033818                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           950115                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses            29236861                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  8213.167334                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  3241.299201                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                28108295                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      9269101405                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.038601                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1128566                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits             178333                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency   3079989464                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.032501                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           950233                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.851200                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           3486.513459                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses           28095227                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  7297.350069                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  3081.864877                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.852939                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           3493.638101                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses           29236861                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  8213.167334                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  3241.299201                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               27008178                       # number of overall hits
-system.cpu.dcache.overall_miss_latency     7932577095                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.038692                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1087049                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits            136934                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   2928126048                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.033818                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          950115                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits               28108295                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     9269101405                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.038601                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1128566                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits            178333                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency   3079989464                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.032501                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          950233                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 946019                       # number of replacements
-system.cpu.dcache.sampled_refs                 950115                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                 946137                       # number of replacements
+system.cpu.dcache.sampled_refs                 950233                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3486.513459                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 27008178                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            23888324000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   943195                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles        6646243                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts       108354440                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          27877036                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           74250519                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         2697135                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles         606870                       # Number of cycles decode is unblocking
+system.cpu.dcache.tagsinuse               3493.638101                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 28120706                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            19296981000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   943150                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       18515611                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred           9136                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved       4758893                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts       141080898                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          33469255                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           33017602                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         5612232                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts          30592                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles         856116                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -146,243 +158,243 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                    22369140                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  12683528                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      76804780                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                214312                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      109645002                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                18268                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                 1945739                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.199530                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           12683528                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           20717897                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.978019                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          112077803                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.986563                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.108841                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                    29845348                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                  15520576                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                      34753915                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                276813                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                      143294690                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                20423                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                 1615761                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.326178                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles           15520576                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches           25123244                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.566058                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples           91470816                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.578120                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.573721                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 35656347     31.81%     31.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 60887079     54.33%     86.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  7618220      6.80%     92.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   828250      0.74%     93.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4141725      3.70%     97.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2560072      2.28%     99.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   241812      0.22%     99.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                     9014      0.01%     99.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                   135284      0.12%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 56780865     62.08%     62.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  6426529      7.03%     69.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6459161      7.06%     76.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4449430      4.86%     81.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3594685      3.93%     84.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1897731      2.07%     87.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1934782      2.12%     89.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3238407      3.54%     92.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  6689226      7.31%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            112077803                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        75                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       47                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses           12683528                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36327.096774                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34505.200594                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               12682753                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       28153500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000061                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  775                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               102                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     23222000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000053                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             673                       # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total             91470816                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        87                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       78                       # number of floating regfile writes
+system.cpu.icache.ReadReq_accesses           15520576                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35610.047847                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34405.604720                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               15519740                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       29770000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000054                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                  836                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               158                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency     23327000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000044                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses             678                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               18845.101040                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               22890.471976                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            12683528                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36327.096774                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34505.200594                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                12682753                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        28153500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000061                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   775                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                102                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     23222000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000053                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              673                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses            15520576                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35610.047847                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34405.604720                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                15519740                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        29770000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000054                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                   836                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                158                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency     23327000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000044                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses              678                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.278329                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            570.018353                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses           12683528                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 36327.096774                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34505.200594                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.276985                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            567.265894                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses           15520576                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35610.047847                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34405.604720                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               12682753                       # number of overall hits
-system.cpu.icache.overall_miss_latency       28153500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000061                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  775                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               102                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     23222000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000053                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             673                       # number of overall MSHR misses
+system.cpu.icache.overall_hits               15519740                       # number of overall hits
+system.cpu.icache.overall_miss_latency       29770000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000054                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                  836                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               158                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency     23327000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000044                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses             678                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                      3                       # number of replacements
-system.cpu.icache.sampled_refs                    673                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                      2                       # number of replacements
+system.cpu.icache.sampled_refs                    678                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                570.018353                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 12682753                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                567.265894                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 15519740                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                           31501                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 19532471                       # Number of branches executed
-system.cpu.iew.EXEC:nop                         62748                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.868101                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     28649527                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                    5007239                       # Number of stores executed
+system.cpu.idleCycles                           29415                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                 20970115                       # Number of branches executed
+system.cpu.iew.EXEC:nop                         54598                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.133641                       # Inst execution rate
+system.cpu.iew.EXEC:refs                     30199659                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                    5140774                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  90073370                       # num instructions consuming a value
-system.cpu.iew.WB:count                      96561407                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.596775                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                 127211016                       # num instructions consuming a value
+system.cpu.iew.WB:count                     102056385                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.487951                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  53753580                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.861315                       # insts written-back per cycle
-system.cpu.iew.WB:sent                       96831306                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts              2055858                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                   89156                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              24681129                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts             553822                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           1090186                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts              5533282                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           103041042                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              23642288                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2270342                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts              97322249                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                   1607                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                  62072763                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.115368                       # insts written-back per cycle
+system.cpu.iew.WB:sent                      102572716                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts              1825852                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                  421320                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts              32016564                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts             690308                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts            299404                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts              6585994                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts           130352707                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              25058885                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2046100                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             103728443                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                 170905                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                2697135                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                 23177                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                  1567                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                5612232                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                206705                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked        17440                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads          113868                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses        30334                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked        21484                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads          353411                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses        19757                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation         1330                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads      2095636                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores       788438                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents           1330                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect        76110                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        1979748                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                246243554                       # number of integer regfile reads
-system.cpu.int_regfile_writes                76222698                       # number of integer regfile writes
-system.cpu.ipc                               0.813404                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.813404                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation         3168                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads            1                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads      9440772                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores      1839326                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents           3168                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       298332                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect        1527520                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                259522598                       # number of integer regfile reads
+system.cpu.int_regfile_writes                80481877                       # number of integer regfile writes
+system.cpu.ipc                               0.997260                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.997260                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        70280458     70.57%     70.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          10479      0.01%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            2      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt           11      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc           27      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            3      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       24261777     24.36%     94.94% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite       5039834      5.06%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu        74292294     70.24%     70.24% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult          10639      0.01%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            1      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt           21      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc           38      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            4      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     70.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead       26262906     24.83%     95.08% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite       5208640      4.92%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total         99592591                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                491330                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.004933                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total        105774543                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt                160185                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.001514                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu            430175     87.55%     87.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult               27      0.01%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     87.56% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead            26408      5.37%     92.93% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite           34720      7.07%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu             52262     32.63%     32.63% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult               27      0.02%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     32.64% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead            62957     39.30%     71.95% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite           44939     28.05%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    112077803                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.888602                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.089642                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples     91470816                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.156375                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.444584                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      47855391     42.70%     42.70% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      42755359     38.15%     80.85% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      14035968     12.52%     93.37% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       4551717      4.06%     97.43% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4        786660      0.70%     98.13% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5        736099      0.66%     98.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       1220793      1.09%     99.88% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        128276      0.11%     99.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8          7540      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0      39774696     43.48%     43.48% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      24298391     26.56%     70.05% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2      14242553     15.57%     85.62% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3       6365982      6.96%     92.58% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4       2257550      2.47%     95.05% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5       2688100      2.94%     97.98% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6       1607594      1.76%     99.74% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7        110764      0.12%     99.86% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8        125186      0.14%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    112077803                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.888353                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                      74                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                 144                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           66                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                 98                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses              100083847                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          311754559                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses     96561341                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         112732108                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  102424472                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                  99592591                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded              553822                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined         9752691                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued               388                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved           9100                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined     13565681                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total     91470816                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.156003                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      97                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                 190                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           87                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                166                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              105934631                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          303205662                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    102056298                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         169015166                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                  129602907                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                 105774543                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded              695202                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined        38714982                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued             25765                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved         140881                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined     72800988                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -404,106 +416,107 @@ system.cpu.itb.read_misses                          0                       # DT
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses           46574                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34284.629133                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31026.465938                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits               32027                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency    498738500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.312342                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             14547                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    451342000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.312342                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        14547                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            904214                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34295.295295                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.850051                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                903215                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      34261000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.001105                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 999                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               12                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency     30699500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001092                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            987                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          943195                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              943195                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_accesses           46263                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34215.214251                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31037.691726                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits               31724                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency    497455000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.314268                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             14539                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    451257000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.314268                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        14539                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses            904648                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34281.219272                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31102.589641                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                903631                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency      34864000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.001124                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                1017                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits               13                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency     31227000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001110                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses           1004                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          943150                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              943150                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                103.008184                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                102.932573                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             950788                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34285.314550                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31031.382773                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 935242                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      532999500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.016351                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                15546                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                12                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    482041500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.016338                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           15534                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_accesses             950911                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34219.529442                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31041.883806                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                 935355                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      532319000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.016359                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                15556                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                13                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency    482484000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.016345                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           15543                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.012324                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.246682                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0           403.843587                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8083.268197                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses            950788                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34285.314550                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31031.382773                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.012326                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.249116                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           403.905799                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          8163.029985                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses            950911                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34219.529442                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31041.883806                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                935242                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     532999500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.016351                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               15546                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               12                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    482041500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.016338                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          15534                       # number of overall MSHR misses
+system.cpu.l2cache.overall_hits                935355                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     532319000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.016359                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               15556                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits               13                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency    482484000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.016345                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          15543                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                   709                       # number of replacements
-system.cpu.l2cache.sampled_refs                 15518                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                   704                       # number of replacements
+system.cpu.l2cache.sampled_refs                 15528                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              8487.111783                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1598481                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              8566.935784                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1598337                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                      32                       # number of writebacks
-system.cpu.memDep0.conflictingLoads            436025                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           249497                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             24681129                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5533282                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               157552597                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1603309                       # number of misc regfile writes
-system.cpu.numCycles                        112109304                       # number of cpu cycles simulated
+system.cpu.memDep0.conflictingLoads           1440720                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1005315                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             32016564                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6585994                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               198555291                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1603310                       # number of misc regfile writes
+system.cpu.numCycles                         91500231                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles           294826                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       72061910                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents            4906                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          29931132                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents          31548                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups      277443671                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       106593764                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands     83924752                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           72730204                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         2697135                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles         723329                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          11862839                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups          474                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    277443197                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles      5701177                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts       592742                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts            1065555                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts       576556                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    212048419                       # The number of ROB reads
-system.cpu.rob.rob_writes                   208775892                       # The number of ROB writes
-system.cpu.timesIdled                            1292                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:BlockCycles          3003526                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps       72121263                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents         2932731                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          36158864                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        2288265                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents             58                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups      352780022                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts       136654080                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands    107391797                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           31135789                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         5612232                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles        6274602                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps          35270531                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups          655                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    352779367                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles      9285803                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts       702152                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           13506306                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts       702838                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    215605482                       # The number of ROB reads
+system.cpu.rob.rob_writes                   266316908                       # The number of ROB writes
+system.cpu.timesIdled                            1399                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             442                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
index a584d29ed..febb3dd2f 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -66,9 +66,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
index 34dd3ff53..4df99b9a8 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:24
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:10:13
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -28,4 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 54215549000 because target called exit()
+Exiting @ tick 54240666000 because target called exit()
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 0d4b35c47..60359959c 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 937948                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 362060                       # Number of bytes of host memory used
-host_seconds                                    97.24                       # Real time elapsed on the host
-host_tick_rate                              557562760                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1915165                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 378952                       # Number of bytes of host memory used
+host_seconds                                    47.65                       # Real time elapsed on the host
+host_tick_rate                             1138365446                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    91202735                       # Number of instructions simulated
-sim_seconds                                  0.054216                       # Number of seconds simulated
-sim_ticks                                 54215549000                       # Number of ticks simulated
+sim_insts                                    91252969                       # Number of instructions simulated
+sim_seconds                                  0.054241                       # Number of seconds simulated
+sim_ticks                                 54240666000                       # Number of ticks simulated
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -52,24 +52,24 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        108431099                       # number of cpu cycles simulated
+system.cpu.numCycles                        108481333                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  108431099                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                  108481333                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     15112201                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
 system.cpu.num_fp_insts                            48                       # number of float instructions
 system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                       97900                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                         91202735                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              72483223                       # Number of integer alu accesses
-system.cpu.num_int_insts                     72483223                       # number of integer instructions
-system.cpu.num_int_register_reads           234567931                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           72546720                       # number of times the integer registers were written
-system.cpu.num_load_insts                    22585492                       # Number of load instructions
-system.cpu.num_mem_refs                      27330336                       # number of memory refs
+system.cpu.num_insts                         91252969                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
+system.cpu.num_int_insts                     72525682                       # number of integer instructions
+system.cpu.num_int_register_reads           234656737                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           72596953                       # number of times the integer registers were written
+system.cpu.num_load_insts                    22573967                       # Number of load instructions
+system.cpu.num_mem_refs                      27318811                       # number of memory refs
 system.cpu.num_store_insts                    4744844                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             442                       # Number of system calls
 
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
index d7d6a4868..faf8a693c 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
@@ -166,9 +169,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
index b290f1d74..fff5a35b0 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:25
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 21:05:58
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -28,4 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 148086219000 because target called exit()
+Exiting @ tick 148086239000 because target called exit()
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 5c965f81e..33b349bfd 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,78 +1,82 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 419592                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 369772                       # Number of bytes of host memory used
-host_seconds                                   217.30                       # Real time elapsed on the host
-host_tick_rate                              681491064                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 675901                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 386672                       # Number of bytes of host memory used
+host_seconds                                   134.97                       # Real time elapsed on the host
+host_tick_rate                             1097177206                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    91176087                       # Number of instructions simulated
+sim_insts                                    91226321                       # Number of instructions simulated
 sim_seconds                                  0.148086                       # Number of seconds simulated
-sim_ticks                                148086219000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses           22564820                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14013.157105                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157105                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               21664622                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    12614616000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.039894                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               900198                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   9914022000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.039894                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          900198                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses           4738868                       # number of WriteReq accesses(hits+misses)
+sim_ticks                                148086239000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits             3887                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses           22549408                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               21649219                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    12614490000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.039921                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               900189                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   9913923000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.039921                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses          900189                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses          3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits              3887                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits               4692259                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits               4688372                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency    1263542000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.009835                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.009844                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses               46609                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_miss_latency   1123715000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009835                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009844                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses          46609                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  27.837649                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  27.825751                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            27303688                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 14657.853184                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11657.853184                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                26356881                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     13878158000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.034677                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                946807                       # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses            27284389                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 14657.859438                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                26337591                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     13878032000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.034701                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                946798                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  11037737000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.034677                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           946807                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  11037638000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.034701                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           946798                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.871309                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           3568.882850                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses           27303688                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 14657.853184                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11657.853184                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.871228                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           3568.549501                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses           27284389                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 14657.859438                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               26356881                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    13878158000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.034677                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               946807                       # number of overall misses
+system.cpu.dcache.overall_hits               26337591                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    13878032000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.034701                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               946798                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  11037737000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.034677                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          946807                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  11037638000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.034701                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          946798                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 942711                       # number of replacements
-system.cpu.dcache.sampled_refs                 946807                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                 942702                       # number of replacements
+system.cpu.dcache.sampled_refs                 946798                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3568.882850                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 26356881                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            54482100000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   942313                       # number of writebacks
+system.cpu.dcache.tagsinuse               3568.549501                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 26345365                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            54479156000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   942309                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -94,10 +98,10 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses          107819118                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses          107830780                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 54527.545910                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              107818519                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits              107830181                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       32662000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000006                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  599                       # number of ReadReq misses
@@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000006                       # ms
 system.cpu.icache.ReadReq_mshr_misses             599                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               179997.527546                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               180016.996661                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           107819118                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses           107830780                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 54527.545910                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               107818519                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits               107830181                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        32662000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000006                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   599                       # number of demand (read+write) misses
@@ -126,13 +130,13 @@ system.cpu.icache.demand_mshr_misses              599                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.249185                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            510.330850                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses          107819118                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.249187                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            510.335448                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses          107830780                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 54527.545910                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              107818519                       # number of overall hits
+system.cpu.icache.overall_hits              107830181                       # number of overall hits
 system.cpu.icache.overall_miss_latency       32662000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000006                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  599                       # number of overall misses
@@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                      2                       # number of replacements
 system.cpu.icache.sampled_refs                    599                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                510.330850                       # Cycle average of tags in use
-system.cpu.icache.total_refs                107818519                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                510.335448                       # Cycle average of tags in use
+system.cpu.icache.total_refs                107830181                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses             14548                       # nu
 system.cpu.l2cache.ReadExReq_mshr_miss_latency    581920000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.312129                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses        14548                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            900797                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses            900788                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                899937                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits                899928                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_miss_latency      44720000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.000955                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                 860                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency     34400000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.000955                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            860                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          942313                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              942313                       # number of Writeback hits
+system.cpu.l2cache.Writeback_accesses          942309                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              942309                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                103.596349                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                103.595504                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             947406                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses             947397                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 931998                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits                 931989                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_miss_latency      801216000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.016263                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate          0.016264                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                15408                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_miss_latency    616320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.016263                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.016264                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses           15408                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.occ_%::0                  0.009921                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.271910                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0           325.103802                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8909.939708                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses            947406                       # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::1                  0.271918                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           325.097811                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          8910.209882                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses            947397                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                931998                       # number of overall hits
+system.cpu.l2cache.overall_hits                931989                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency     801216000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.016263                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate         0.016264                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses               15408                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_miss_latency    616320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.016263                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.016264                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses          15408                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                   634                       # number of replacements
 system.cpu.l2cache.sampled_refs                 15392                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              9235.043509                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1594555                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              9235.307693                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1594542                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                      32                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        296172438                       # number of cpu cycles simulated
+system.cpu.numCycles                        296172478                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  296172438                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                  296172478                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     15112201                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
 system.cpu.num_fp_insts                            48                       # number of float instructions
 system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                       97900                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                         91176087                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              72483223                       # Number of integer alu accesses
-system.cpu.num_int_insts                     72483223                       # number of integer instructions
-system.cpu.num_int_register_reads           257112085                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           72558730                       # number of times the integer registers were written
-system.cpu.num_load_insts                    22585492                       # Number of load instructions
-system.cpu.num_mem_refs                      27330336                       # number of memory refs
+system.cpu.num_insts                         91226321                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
+system.cpu.num_int_insts                     72525682                       # number of integer instructions
+system.cpu.num_int_register_reads           257193253                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           72608963                       # number of times the integer registers were written
+system.cpu.num_load_insts                    22573967                       # Number of load instructions
+system.cpu.num_mem_refs                      27318811                       # number of memory refs
 system.cpu.num_store_insts                    4744844                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             442                       # Number of system calls
 
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
index 92faf41fb..a5aa41068 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -115,6 +115,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -413,6 +414,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -448,6 +450,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -493,9 +496,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
index 85a6ac5af..673c7ce2f 100755
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 21 2011 14:34:16
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 15:43:32
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 21:06:16
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -72,4 +72,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 365986074500 because target called exit()
+Exiting @ tick 345312086000 because target called exit()
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
index afae24f2b..a1a1cf171 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,130 +1,142 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  77433                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 260740                       # Number of bytes of host memory used
-host_seconds                                  7232.86                       # Real time elapsed on the host
-host_tick_rate                               50600448                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 137280                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 259116                       # Number of bytes of host memory used
+host_seconds                                  4176.43                       # Real time elapsed on the host
+host_tick_rate                               82681134                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   560059971                       # Number of instructions simulated
-sim_seconds                                  0.365986                       # Number of seconds simulated
-sim_ticks                                365986074500                       # Number of ticks simulated
+sim_insts                                   573342432                       # Number of instructions simulated
+sim_seconds                                  0.345312                       # Number of seconds simulated
+sim_ticks                                345312086000                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                140387936                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups             174401300                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           15511612                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          191766015                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                191766015                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches              110089780                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           3558142                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                147772005                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups             179850444                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect             2706777                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect           15769862                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted          177167417                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                222186718                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                 11015263                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches              116606359                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events           6384495                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    662070266                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.847952                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.257926                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples    625227574                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.919163                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.394949                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    343782937     51.93%     51.93% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    194895590     29.44%     81.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     65587700      9.91%     91.27% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     25120372      3.79%     95.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     18782135      2.84%     97.90% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      6815428      1.03%     98.93% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      2394801      0.36%     99.29% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      1133161      0.17%     99.46% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      3558142      0.54%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0    321936350     51.49%     51.49% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1    172149257     27.53%     79.02% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2     71132688     11.38%     90.40% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3     25332872      4.05%     94.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4     16298028      2.61%     97.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5      5238396      0.84%     97.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6      5475401      0.88%     98.77% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7      1280087      0.20%     98.98% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8      6384495      1.02%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    662070266                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 561403855                       # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total    625227574                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                 574686316                       # Number of instructions committed
 system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             464140463                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 128127024                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  184987501                       # Number of memory references committed
+system.cpu.commit.COM:function_calls          9757362                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             473702213                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                 126773184                       # Number of loads committed
+system.cpu.commit.COM:membars                 1488542                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                  184377289                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts          26429304                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts      561403855                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls          157189                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       399418051                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                   560059971                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             560059971                       # Number of Instructions Simulated
-system.cpu.cpi                               1.306953                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.306953                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses          149905369                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 10172.883940                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  6761.781933                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              148899998                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    10227522500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.006707                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1005371                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            179403                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   5585015500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.005510                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          825968                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          55727847                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 14757.173065                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13626.207417                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              54433003                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   19108237000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.023235                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1294844                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits           947408                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   4734235000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006235                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         347436                       # number of WriteReq MSHR misses
+system.cpu.commit.branchMispredicts          21484787                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts      574686316                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls         3877900                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts       412531053                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                   573342432                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             573342432                       # Number of Instructions Simulated
+system.cpu.cpi                               1.204558                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.204558                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses      2604377                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency  8985.294118                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits          2604343                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency       305500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000013                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses             34                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits           34                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.ReadReq_accesses          142611934                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 10444.092632                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7123.731625                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              141561974                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    10965879500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.007362                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              1049960                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            198181                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency   6067845000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.005973                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses          851779                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses       2232169                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits           2232169                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 14556.604118                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12575.325933                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              52898794                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   19513302500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.024715                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1340512                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          1004937                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   4219965000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006187                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         335575                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 173.284886                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                 167.850641                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           205633216                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 12753.485870                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  8794.286111                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               203333001                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     29335759500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.011186                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2300215                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            1126811                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  10319250500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.005706                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1173404                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses           196851240                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 12750.277769                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  8664.484223                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               194460768                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     30479182000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.012144                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2390472                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            1203118                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency  10287810000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.006032                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          1187354                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.992547                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4065.472807                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          205633216                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 12753.485870                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  8794.286111                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.990968                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4059.005774                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          196851240                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 12750.277769                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  8664.484223                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              203333001                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    29335759500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.011186                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2300215                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           1126811                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  10319250500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.005706                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1173404                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits              194460768                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    30479182000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.012144                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2390472                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           1203118                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency  10287810000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.006032                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         1187354                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1169307                       # number of replacements
-system.cpu.dcache.sampled_refs                1173403                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                1183253                       # number of replacements
+system.cpu.dcache.sampled_refs                1187349                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4065.472807                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                203333005                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             6053772000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  1049504                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       23915687                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts      1082602718                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         296214320                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          338871926                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        65446321                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles        3068332                       # Number of cycles decode is unblocking
+system.cpu.dcache.tagsinuse               4059.005774                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                199297291                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             7009642000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  1060964                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       99879126                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          76616                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved      33311544                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts      1125601371                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles         285750111                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles          233945838                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles        60722303                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts         217312                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        5652498                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -146,242 +158,242 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                   191766015                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 122748340                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     351971872                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               3710699                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      938893733                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles              4527385                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                26711690                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.261985                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          122748340                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches          140387936                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.282691                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          727516586                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.537241                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.455426                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                   222186718                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                 126406345                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                     243921736                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes               3067508                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                     1002303501                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles              5157741                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                21891737                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.321719                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles          126406345                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches          158787268                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.451301                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples          685949876                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.695461                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.705917                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                376259318     51.72%     51.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                167730540     23.06%     74.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 28515235      3.92%     78.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 34553707      4.75%     83.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 26720758      3.67%     87.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 10947410      1.50%     88.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 11409505      1.57%     90.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 11171933      1.54%     91.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 60208180      8.28%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                442039747     64.44%     64.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 19794967      2.89%     67.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 33809086      4.93%     72.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 38427852      5.60%     77.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 37318627      5.44%     83.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 18120316      2.64%     85.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 18761200      2.74%     88.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 13563249      1.98%     90.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 64114832      9.35%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            727516586                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            685949876                       # Number of instructions fetched each cycle (Total)
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses          122748340                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13369.913613                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  9679.346455                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              122731555                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      224414000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000137                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                16785                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               933                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    153437000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000129                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           15852                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses          126406345                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 14514.118554                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 10752.907416                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits              126392073                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency      207145500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000113                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                14272                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits              1030                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency    142390000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000105                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses           13242                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                7742.827266                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                9548.392612                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           122748340                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13369.913613                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  9679.346455                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               122731555                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       224414000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000137                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 16785                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                933                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    153437000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000129                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            15852                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses           126406345                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 14514.118554                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 10752.907416                       # average overall mshr miss latency
+system.cpu.icache.demand_hits               126392073                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency       207145500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000113                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                 14272                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits               1030                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency    142390000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000105                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses            13242                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.543111                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1112.290548                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses          122748340                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13369.913613                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  9679.346455                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.510807                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1046.133692                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses          126406345                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 14514.118554                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 10752.907416                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              122731555                       # number of overall hits
-system.cpu.icache.overall_miss_latency      224414000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000137                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                16785                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               933                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    153437000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000129                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           15852                       # number of overall MSHR misses
+system.cpu.icache.overall_hits              126392073                       # number of overall hits
+system.cpu.icache.overall_miss_latency      207145500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000113                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                14272                       # number of overall misses
+system.cpu.icache.overall_mshr_hits              1030                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency    142390000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000105                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses           13242                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  14002                       # number of replacements
-system.cpu.icache.sampled_refs                  15851                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                  11420                       # number of replacements
+system.cpu.icache.sampled_refs                  13237                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1112.290548                       # Cycle average of tags in use
-system.cpu.icache.total_refs                122731555                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1046.133692                       # Cycle average of tags in use
+system.cpu.icache.total_refs                126392073                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                         4455564                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                125457274                       # Number of branches executed
-system.cpu.iew.EXEC:nop                      13838185                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.981178                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    229700627                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   72018658                       # Number of stores executed
+system.cpu.idleCycles                         4674297                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                138497028                       # Number of branches executed
+system.cpu.iew.EXEC:nop                      12955862                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.047031                       # Inst execution rate
+system.cpu.iew.EXEC:refs                    218144468                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                   66082703                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 714382081                       # num instructions consuming a value
-system.cpu.iew.WB:count                     665966048                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.510315                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                 791991230                       # num instructions consuming a value
+system.cpu.iew.WB:count                     685951510                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.483503                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 364559924                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.909824                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      705629563                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts             29041716                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                 2636135                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             199993331                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts             162274                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts          12088796                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            140409395                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           960810723                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             157681969                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          32008551                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             718194992                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                 117672                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                 382930143                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.993234                       # insts written-back per cycle
+system.cpu.iew.WB:sent                      714914629                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts             25642135                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                 3016830                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             198100704                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts            2797901                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts           7211752                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts            114500942                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts           987209077                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts             152061765                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          22604731                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             723105102                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                 125136                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                  3801                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               65446321                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                180324                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                  5730                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles               60722303                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                194914                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads         4458450                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses         9743                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads         4520039                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses        10219                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation       347516                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads        11819                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads     71866306                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores     83548918                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         347516                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect     14571260                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       14470456                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads               1616277270                       # number of integer regfile reads
-system.cpu.int_regfile_writes               504274200                       # number of integer regfile writes
-system.cpu.ipc                               0.765138                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.765138                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation       426900                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads        14200                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads     71327515                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores     56896833                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents         426900                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect     10953146                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect       14688989                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               1644155544                       # number of integer regfile reads
+system.cpu.int_regfile_writes               528242138                       # number of integer regfile writes
+system.cpu.ipc                               0.830180                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.830180                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       504696330     67.27%     67.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult         349129      0.05%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd            80      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            3      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     67.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      162553860     21.67%     88.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      82604141     11.01%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu       515258626     69.10%     69.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult         385422      0.05%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd            76      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            3      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     69.15% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead      160083543     21.47%     90.62% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite      69982165      9.38%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        750203543                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              11563965                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.015414                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total        745709835                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt              10315393                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.013833                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu            153469      1.33%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          5982996     51.74%     53.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         5427500     46.93%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu           2085862     20.22%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     20.22% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead          5244548     50.84%     71.06% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite         2984983     28.94%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    727516586                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.031184                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.359043                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples    685949876                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.087120                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.369949                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     340760839     46.84%     46.84% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     195196887     26.83%     73.67% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     103112393     14.17%     87.84% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      43508042      5.98%     93.82% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      23307105      3.20%     97.03% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      12389030      1.70%     98.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       3383235      0.47%     99.19% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       4087676      0.56%     99.76% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8       1771379      0.24%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0     322453331     47.01%     47.01% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1     152222370     22.19%     69.20% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2     115563946     16.85%     86.05% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3      51318874      7.48%     93.53% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4      26753309      3.90%     97.43% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5       7611284      1.11%     98.54% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6       7427521      1.08%     99.62% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7       2025759      0.30%     99.92% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8        573482      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    727516586                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.024907                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                     100                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                 196                       # Number of floating instruction queue reads
+system.cpu.iq.ISSUE:issued_per_cycle::total    685949876                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.079762                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      96                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                 188                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                598                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses              761767408                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads         2247505915                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    665966032                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes        1323699335                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  946810264                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 750203543                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded              162274                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       376428693                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued           8018474                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved           5085                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    702572396                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.fp_inst_queue_writes                358                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              756025132                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         2190014235                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    685951494                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        1361390433                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                  969594427                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                 745709835                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded             4658788                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined       386770433                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued           2329486                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved         780888                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined    694137605                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -403,109 +415,109 @@ system.cpu.itb.read_misses                          0                       # DT
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          347863                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34247.596496                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.740070                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              228350                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   4093033000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.343563                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            119513                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   3705469500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.343563                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       119513                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            841391                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34185.632593                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.780138                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                726325                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    3933604000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.136757                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses              115066                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               30                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency   3568621500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.136721                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses         115036                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_hits                  1                       # number of UpgradeReq hits
-system.cpu.l2cache.Writeback_accesses         1049504                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             1049504                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_accesses          335898                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34251.024874                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.131537                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits              231251                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   3584267000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.311544                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            104647                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   3244594000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.311544                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       104647                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses            864685                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34190.230739                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.195188                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                736835                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    4371221000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.147857                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses              127850                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits               14                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency   3965242000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.147841                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses         127836                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses              3                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_hits                  3                       # number of UpgradeReq hits
+system.cpu.l2cache.Writeback_accesses         1060964                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             1060964                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  6.339320                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  6.548774                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            1189254                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34217.201881                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.097476                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 954675                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     8026637000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.197249                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               234579                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                30                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   7274091000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.197224                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          234549                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_accesses            1200583                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34217.594206                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31012.314879                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                 968086                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     7955488000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.193653                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               232497                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency   7209836000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.193642                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          232483                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.185910                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.449873                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          6091.890422                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         14741.450627                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses           1189254                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34217.201881                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.097476                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.235755                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.409558                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          7725.216525                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13420.386918                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses           1200583                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34217.594206                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31012.314879                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                954675                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    8026637000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.197249                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              234579                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               30                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   7274091000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.197224                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         234549                       # number of overall MSHR misses
+system.cpu.l2cache.overall_hits                968086                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    7955488000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.193653                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              232497                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits               14                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency   7209836000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.193642                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         232483                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                215449                       # number of replacements
-system.cpu.l2cache.sampled_refs                235636                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                213383                       # number of replacements
+system.cpu.l2cache.sampled_refs                233608                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             20833.341048                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1493772                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          262779341000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                  171632                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          58798533                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         76400324                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            199993331                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           140409395                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads              1169227072                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 344748                       # number of misc regfile writes
-system.cpu.numCycles                        731972150                       # number of cpu cycles simulated
+system.cpu.l2cache.tagsinuse             21145.603443                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1529846                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          251648343000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                  169621                       # number of writebacks
+system.cpu.memDep0.conflictingLoads          69633889                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         68589382                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            198100704                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           114500942                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads              1230715150                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 344749                       # number of misc regfile writes
+system.cpu.numCycles                        690624173                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles          7146790                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      435368498                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         5207540                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         311739226                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        9258079                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents             25                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     2640447492                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      1043812056                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    713532745                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          325976886                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        65446321                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       15480980                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         278164244                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups         1939                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   2640445553                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles      1726383                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts       233275                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           49072391                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts       185712                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                   1619326892                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1987147936                       # The number of ROB writes
-system.cpu.timesIdled                           95874                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:BlockCycles         13815420                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps      448650958                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents        11250412                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles         301168670                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents       11014301                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents             24                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups     2669060394                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts      1077315314                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands    784928020                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles          223928164                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles        60722303                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles       28708652                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps         336277040                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups         1236                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   2669059158                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles     57606667                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts      2819849                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           78103763                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts      2819793                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   1606053310                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2035197393                       # The number of ROB writes
+system.cpu.timesIdled                          113698                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
index 8b55eca4f..a151096ae 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -66,9 +66,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
index c27562976..b7bee7747 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:25
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:56:42
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -72,4 +72,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 285716811500 because target called exit()
+Exiting @ tick 290498972000 because target called exit()
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 0871fb1fa..ebf53733b 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1052675                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 232888                       # Number of bytes of host memory used
-host_seconds                                   533.31                       # Real time elapsed on the host
-host_tick_rate                              535740490                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1809145                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 249796                       # Number of bytes of host memory used
+host_seconds                                   315.60                       # Real time elapsed on the host
+host_tick_rate                              920461558                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   561403855                       # Number of instructions simulated
-sim_seconds                                  0.285717                       # Number of seconds simulated
-sim_ticks                                285716811500                       # Number of ticks simulated
+sim_insts                                   570968176                       # Number of instructions simulated
+sim_seconds                                  0.290499                       # Number of seconds simulated
+sim_ticks                                290498972000                       # Number of ticks simulated
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -52,24 +52,24 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        571433624                       # number of cpu cycles simulated
+system.cpu.numCycles                        580997945                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  571433624                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                  580997945                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     92286726                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_fp_insts                            16                       # number of float instructions
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    16003168                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        561403855                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             464140465                       # Number of integer alu accesses
-system.cpu.num_int_insts                    464140465                       # number of integer instructions
-system.cpu.num_int_register_reads          1370673061                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          415936275                       # number of times the integer registers were written
-system.cpu.num_load_insts                   128127024                       # Number of load instructions
-system.cpu.num_mem_refs                     184987503                       # number of memory refs
+system.cpu.num_insts                        570968176                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             470727703                       # Number of integer alu accesses
+system.cpu.num_int_insts                    470727703                       # number of integer instructions
+system.cpu.num_int_register_reads          1385336079                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          425457618                       # number of times the integer registers were written
+system.cpu.num_load_insts                   126029556                       # Number of load instructions
+system.cpu.num_mem_refs                     182890035                       # number of memory refs
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls
 
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
index 9596a7281..043ad11cc 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
@@ -166,9 +169,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
index db8a10df5..3a9b66fdf 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:00:20
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:33:09
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -72,4 +72,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 719872424000 because target called exit()
+Exiting @ tick 722234364000 because target called exit()
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
index 5187afa41..54e168a67 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,78 +1,82 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 427899                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 240600                       # Number of bytes of host memory used
-host_seconds                                  1307.48                       # Real time elapsed on the host
-host_tick_rate                              550579326                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 827470                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 257480                       # Number of bytes of host memory used
+host_seconds                                   687.68                       # Real time elapsed on the host
+host_tick_rate                             1050246633                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   559470527                       # Number of instructions simulated
-sim_seconds                                  0.719872                       # Number of seconds simulated
-sim_ticks                                719872424000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses          127326326                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 19806.811274                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16806.811274                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              126543330                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    15508654000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.006150                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               782996                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  13159666000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.006150                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          782996                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          55727847                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 28149.273084                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25149.273084                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              55371547                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   10029586000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.006394                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              356300                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   8960686000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006394                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         356300                       # number of WriteReq MSHR misses
+sim_insts                                   569034848                       # Number of instructions simulated
+sim_seconds                                  0.722234                       # Number of seconds simulated
+sim_ticks                                722234364000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses      1488541                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits          1488541                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses          123740317                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              122957659                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    15502704000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.006325                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               782658                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  13154730000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.006325                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses          782658                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses       1488541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits           1488541                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              53883046                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   10028942000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.006568                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              356260                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   8960162000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006568                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         356260                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 159.673059                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                 157.884753                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           183054173                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22415.807657                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19415.807657                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               181914877                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     25538240000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.006224                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1139296                       # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses           177979623                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 22417.457622                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               176840705                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     25531646000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.006399                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1138918                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  22120352000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.006224                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1139296                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  22114892000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.006399                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          1138918                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.992721                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4066.183353                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          183054173                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22415.807657                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19415.807657                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.992551                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4065.490059                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          177979623                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 22417.457622                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              181914877                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    25538240000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.006224                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1139296                       # number of overall misses
+system.cpu.dcache.overall_hits              176840705                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    25531646000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.006399                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1138918                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  22120352000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.006224                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1139296                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  22114892000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.006399                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         1138918                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1135200                       # number of replacements
-system.cpu.dcache.sampled_refs                1139296                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                1134822                       # number of replacements
+system.cpu.dcache.sampled_refs                1138918                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4066.183353                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                181914877                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            11578483000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  1025629                       # number of writebacks
+system.cpu.dcache.tagsinuse               4065.490059                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                179817787                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            11889987000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  1025440                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -94,10 +98,10 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses          512145761                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses          516611385                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 24743.338252                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              512134240                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits              516599864                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency      285068000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                11521                       # number of ReadReq misses
@@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000022                       # ms
 system.cpu.icache.ReadReq_mshr_misses           11521                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               44452.238521                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               44839.845847                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           512145761                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses           516611385                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 24743.338252                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               512134240                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits               516599864                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency       285068000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000022                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 11521                       # number of demand (read+write) misses
@@ -126,13 +130,13 @@ system.cpu.icache.demand_mshr_misses            11521                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.482234                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            987.615046                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses          512145761                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.480677                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            984.426148                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses          516611385                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 24743.338252                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              512134240                       # number of overall hits
+system.cpu.icache.overall_hits              516599864                       # number of overall hits
 system.cpu.icache.overall_miss_latency      285068000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                11521                       # number of overall misses
@@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   9788                       # number of replacements
 system.cpu.icache.sampled_refs                  11521                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                987.615046                       # Cycle average of tags in use
-system.cpu.icache.total_refs                512134240                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                984.426148                       # Cycle average of tags in use
+system.cpu.icache.total_refs                516599864                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -171,94 +175,94 @@ system.cpu.itb.read_misses                          0                       # DT
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          356300                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          356260                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              236267                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   6241716000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.336887                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            120033                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4801320000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.336887                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       120033                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            794517                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_hits              236229                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   6241612000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.336920                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            120031                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4801240000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.336920                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       120031                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses            794179                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                683315                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    5782504000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.139962                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses              111202                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   4448080000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.139962                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses         111202                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         1025629                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             1025629                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                683006                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    5780996000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.139985                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses              111173                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   4446920000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.139985                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses         111173                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         1025440                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             1025440                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  6.147006                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  6.145937                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            1150817                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses            1150439                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 919582                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    12024220000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.200931                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               231235                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 919235                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    12022608000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.200970                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               231204                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   9249400000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.200931                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          231235                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   9248160000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.200970                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          231204                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.178887                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.445562                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          5861.784368                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         14600.161549                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses           1150817                       # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::0                  0.178502                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.445374                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          5849.157602                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         14594.006011                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses           1150439                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                919582                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   12024220000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.200931                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              231235                       # number of overall misses
+system.cpu.l2cache.overall_hits                919235                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   12022608000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.200970                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              231204                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   9249400000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.200931                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         231235                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   9248160000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.200970                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         231204                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                212119                       # number of replacements
-system.cpu.l2cache.sampled_refs                232160                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                212089                       # number of replacements
+system.cpu.l2cache.sampled_refs                232128                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             20461.945917                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1427089                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          510281834000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                  172310                       # number of writebacks
+system.cpu.l2cache.tagsinuse             20443.163614                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1426644                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          513135223000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                  172302                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1439744848                       # number of cpu cycles simulated
+system.cpu.numCycles                       1444468728                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 1439744848                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                 1444468728                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     92286726                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_fp_insts                            16                       # number of float instructions
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    16003168                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        559470527                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             464140465                       # Number of integer alu accesses
-system.cpu.num_int_insts                    464140465                       # number of integer instructions
-system.cpu.num_int_register_reads          1497198689                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          415939738                       # number of times the integer registers were written
-system.cpu.num_load_insts                   128127024                       # Number of load instructions
-system.cpu.num_mem_refs                     184987503                       # number of memory refs
+system.cpu.num_insts                        569034848                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             470727703                       # Number of integer alu accesses
+system.cpu.num_int_insts                    470727703                       # number of integer instructions
+system.cpu.num_int_register_reads          1511252780                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          425461081                       # number of times the integer registers were written
+system.cpu.num_load_insts                   126029556                       # Number of load instructions
+system.cpu.num_mem_refs                     182890035                       # number of memory refs
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls
 
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
index 5e5332f9b..b78535a02 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -115,6 +115,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -413,6 +414,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -448,6 +450,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -493,7 +496,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
index f3be2b346..56d7b7504 100755
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 21 2011 14:34:16
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 14:41:06
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:19:35
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -17,5 +17,5 @@ Eon, Version 1.1
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
-OO-style eon Time= 0.210000
-Exiting @ tick 215422930500 because target called exit()
+OO-style eon Time= 0.170000
+Exiting @ tick 173737299500 because target called exit()
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
index de918dfb0..a23b70561 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,130 +1,142 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  59988                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 271504                       # Number of bytes of host memory used
-host_seconds                                  5747.46                       # Real time elapsed on the host
-host_tick_rate                               37481445                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 105768                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 263952                       # Number of bytes of host memory used
+host_seconds                                  3300.30                       # Real time elapsed on the host
+host_tick_rate                               52642890                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   344777343                       # Number of instructions simulated
-sim_seconds                                  0.215423                       # Number of seconds simulated
-sim_ticks                                215422930500                       # Number of ticks simulated
+sim_insts                                   349065960                       # Number of instructions simulated
+sim_seconds                                  0.173737                       # Number of seconds simulated
+sim_ticks                                173737299500                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 29670488                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              36719835                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            7622671                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           36869177                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 36869177                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               28188953                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           5177396                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                 20216884                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              26426271                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect               53555                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect            3385203                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           19876693                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 36665151                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  7335349                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches               30506630                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events           6423122                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    417225904                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.826358                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.412065                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples    340217087                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.026011                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.609311                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    233100746     55.87%     55.87% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    116424213     27.90%     83.77% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     32132757      7.70%     91.48% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     14133629      3.39%     94.86% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      7357055      1.76%     96.63% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      4244457      1.02%     97.64% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      2971889      0.71%     98.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      1683762      0.40%     98.76% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      5177396      1.24%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0    170345162     50.07%     50.07% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1     99509001     29.25%     79.32% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2     28782057      8.46%     87.78% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3     16235874      4.77%     92.55% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4      9859908      2.90%     95.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5      4137947      1.22%     96.66% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6      2696620      0.79%     97.46% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7      2227396      0.65%     98.11% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8      6423122      1.89%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    417225904                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 344777955                       # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total    340217087                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                 349066572                       # Number of instructions committed
 system.cpu.commit.COM:fp_insts              114216705                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             283262899                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  94652977                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  177028572                       # Number of memory references committed
+system.cpu.commit.COM:function_calls          6225112                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             287529355                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                  94648992                       # Number of loads committed
+system.cpu.commit.COM:membars                   11033                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                  177024829                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts           9986408                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts      344777955                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls         3533298                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        48561453                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                   344777343                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             344777343                       # Number of Instructions Simulated
-system.cpu.cpi                               1.249635                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.249635                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses           98212603                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 32812.379110                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30419.186047                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               98209501                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency      101784000                       # number of ReadReq miss cycles
+system.cpu.commit.branchMispredicts           3371287                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts      349066572                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls         3555471                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts        38687255                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                   349065960                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             349065960                       # Number of Instructions Simulated
+system.cpu.cpi                               0.995441                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.995441                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses        11396                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        38000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits            11394                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency        76000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000176                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.ReadReq_accesses           97345834                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 33073.410778                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30661.926872                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               97342735                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency      102494500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000032                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                 3102                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits              1382                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency     52321000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses                 3099                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits              1376                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency     52830500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000018                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses            1720                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          82063572                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 29748.238774                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35491.403509                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              82044977                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     553168500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000227                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               18595                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits            15745                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency    101150500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_misses            1723                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses         11142                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits             11142                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses          82052672                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 31425.125183                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35401.373723                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              82033500                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency     602482500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000234                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses               19172                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits            16333                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency    100504500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           2850                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           2839                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 11781.250000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               39442.992998                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles::no_targets 19863.636364                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs               39324.588119                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              16                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       188500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       218500                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           180276175                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30186.316081                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33582.385120                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               180254478                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       654952500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000120                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                 21697                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits              17127                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    153471500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_accesses           179398506                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 31654.483409                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33611.354669                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               179376235                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       704977000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.000124                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                 22271                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits              17709                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency    153335000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             4570                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             4562                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.755653                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           3095.155896                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          180276175                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30186.316081                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33582.385120                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.753400                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           3085.925842                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          179398506                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 31654.483409                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33611.354669                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              180254478                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      654952500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000120                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                21697                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits             17127                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    153471500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_hits              179376235                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      704977000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.000124                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                22271                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits             17709                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency    153335000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            4570                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            4562                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                   1402                       # number of replacements
-system.cpu.dcache.sampled_refs                   4570                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                   1404                       # number of replacements
+system.cpu.dcache.sampled_refs                   4562                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3095.155896                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                180254478                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               3085.925842                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                179398771                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                     1028                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles      135683876                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts       445047864                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         110691412                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          165193226                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        13510644                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles        5657389                       # Number of cycles decode is unblocking
+system.cpu.dcache.writebacks                     1024                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles      177195286                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          71850                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved       7266733                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts       418101627                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          89070591                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           70339326                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         7142428                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts         201892                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        3611883                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -146,243 +158,243 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                    36869177                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  45676128                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     181360333                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                631577                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      363476608                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                18583                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                 9990877                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.085574                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           45676128                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           29670488                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.843635                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          430736547                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.090672                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.994313                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                    36665151                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                  39333951                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                      76200894                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                219495                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                      327214024                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                19976                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                 3525022                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.105519                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles           39333951                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches           27552233                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        0.941692                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples          347359514                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.232140                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.649316                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                252892375     58.71%     58.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 95422079     22.15%     80.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 21830959      5.07%     85.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 14061343      3.26%     89.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 11029779      2.56%     91.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  8719423      2.02%     93.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4691835      1.09%     94.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4052981      0.94%     95.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 18035773      4.19%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                271714378     78.22%     78.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  9098002      2.62%     80.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  5614129      1.62%     82.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6550857      1.89%     84.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  5401109      1.55%     85.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4665359      1.34%     87.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3626849      1.04%     88.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4186087      1.21%     89.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 36502744     10.51%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            430736547                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                 185889152                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                130863264                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses           45676128                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 11498.066424                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  7998.605010                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               45658544                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      202182000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000385                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                17584                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               738                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    134744500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000369                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           16846                       # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total            347359514                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                 185260821                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                130652752                       # number of floating regfile writes
+system.cpu.icache.ReadReq_accesses           39333951                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 12067.997808                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  8366.912236                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               39317524                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency      198241000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000418                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                16427                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               817                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency    130607500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000397                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses           15610                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                2710.671100                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                2518.739526                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            45676128                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 11498.066424                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  7998.605010                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                45658544                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       202182000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000385                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 17584                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                738                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    134744500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000369                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            16846                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses            39333951                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 12067.997808                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  8366.912236                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                39317524                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency       198241000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000418                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                 16427                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                817                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency    130607500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000397                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses            15610                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.897245                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1837.557197                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses           45676128                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 11498.066424                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  7998.605010                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.894157                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1831.233820                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses           39333951                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 12067.997808                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  8366.912236                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               45658544                       # number of overall hits
-system.cpu.icache.overall_miss_latency      202182000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000385                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                17584                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               738                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    134744500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000369                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           16846                       # number of overall MSHR misses
+system.cpu.icache.overall_hits               39317524                       # number of overall hits
+system.cpu.icache.overall_miss_latency      198241000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000418                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                16427                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               817                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency    130607500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000397                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses           15610                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  14975                       # number of replacements
-system.cpu.icache.sampled_refs                  16844                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                  13743                       # number of replacements
+system.cpu.icache.sampled_refs                  15610                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1837.557197                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 45658544                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1831.233820                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 39317524                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          109315                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 29572151                       # Number of branches executed
-system.cpu.iew.EXEC:nop                        511948                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.857328                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    185716991                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   85614422                       # Number of stores executed
+system.cpu.idleCycles                          115086                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                 31830970                       # Number of branches executed
+system.cpu.iew.EXEC:nop                         56108                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.053222                       # Inst execution rate
+system.cpu.iew.EXEC:refs                    183288367                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                   84683782                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 264871547                       # num instructions consuming a value
-system.cpu.iew.WB:count                     365283823                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.549146                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                 326571947                       # num instructions consuming a value
+system.cpu.iew.WB:count                     364037870                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.499993                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 145453119                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.847829                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      366846883                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts             10421797                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                    4450                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             108215518                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            3540937                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts          11257763                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             93620838                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           393341940                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             100102569                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7587099                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             369376260                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                     69                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                 163283573                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.047668                       # insts written-back per cycle
+system.cpu.iew.WB:sent                      364350526                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts              3594029                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                  769955                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             107131506                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts            3647750                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts           5567384                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts             91507860                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts           387756246                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              98604585                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2702902                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             365967822                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                    137                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                     9                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               13510644                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                   176                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                    18                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                7142428                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                 44317                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked           37                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads          651720                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses          443                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked          109                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads         1040195                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses         1660                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation         6487                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads           33                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads     13562540                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores     11245243                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents           6487                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      2859143                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        7562654                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                856895426                       # number of integer regfile reads
-system.cpu.int_regfile_writes               187404557                       # number of integer regfile writes
-system.cpu.ipc                               0.800234                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.800234                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation       177809                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads        44277                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads     12482513                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores      9132023                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents         177809                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       383406                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect        3210623                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                849409468                       # number of integer regfile reads
+system.cpu.int_regfile_writes               186524631                       # number of integer regfile writes
+system.cpu.ipc                               1.004580                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.004580                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       129916529     34.46%     34.46% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult        2146058      0.57%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             3      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp            679      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              2      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     35.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd      6735975      1.79%     36.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     36.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp      8317099      2.21%     39.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt      3313873      0.88%     39.91% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv      1566398      0.42%     40.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc     20555034      5.45%     45.77% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult      7151488      1.90%     47.67% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc      7075439      1.88%     49.55% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt       175286      0.05%     49.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      102612475     27.22%     76.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      87397021     23.18%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu       127517311     34.59%     34.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult        2147275      0.58%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd             3      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     35.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd      6684179      1.81%     36.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     36.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp      8181294      2.22%     39.20% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt      3298042      0.89%     40.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv      1567223      0.43%     40.52% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc     20157898      5.47%     45.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult      7156749      1.94%     47.93% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc      7077602      1.92%     49.85% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt       175287      0.05%     49.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead       99210852     26.91%     76.81% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite      85497009     23.19%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        376963359                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               6999234                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.018567                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total        368670724                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt               6503476                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.017640                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu               202      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult             5040      0.07%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd           70      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt          715      0.01%      0.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            3      0.00%      0.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc       145523      2.08%      2.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult          588      0.01%      2.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc       183278      2.62%      4.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      4.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          4924135     70.35%     75.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         1739680     24.86%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu             17082      0.26%      0.26% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult             5040      0.08%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd           66      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt         1526      0.02%      0.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            3      0.00%      0.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc       257921      3.97%      4.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult          627      0.01%      4.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc       182979      2.81%      7.15% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      7.15% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead          4701020     72.28%     79.44% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite         1337212     20.56%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    430736547                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.875160                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.210569                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples    347359514                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.061352                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.398972                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     218916849     50.82%     50.82% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     123149552     28.59%     79.41% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      45929825     10.66%     90.08% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      20859984      4.84%     94.92% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      13764585      3.20%     98.12% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       5289881      1.23%     99.34% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       2150519      0.50%     99.84% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        439470      0.10%     99.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        235882      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0     164898974     47.47%     47.47% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      92888126     26.74%     74.21% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2      38718431     11.15%     85.36% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3      21127173      6.08%     91.44% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4      18826760      5.42%     96.86% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5       6953193      2.00%     98.86% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6       2902778      0.84%     99.70% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7        878088      0.25%     99.95% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8        165991      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    430736547                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.874938                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses               122762431                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads           242026966                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses    116081453                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes          130324765                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses              261200162                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          950433097                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    249202370                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         307537991                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  389289055                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 376963359                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             3540937                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        45027872                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            797564                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved           7639                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    100142647                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total    347359514                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.061000                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses               120434049                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads           238151015                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses    116197950                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes          135223001                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              254740151                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          853728758                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    247839920                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         290561942                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                  384041147                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                 368670724                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded             3658991                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined        38001894                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued            675335                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved         103520                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined     93798234                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -404,106 +416,107 @@ system.cpu.itb.read_misses                          0                       # DT
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses            2850                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34410.695376                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31218.319802                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_accesses            2839                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34387.668320                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.927711                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_hits                  17                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency     97485500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.994035                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              2833                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     88441500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994035                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         2833                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses             18566                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34300.665596                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.036271                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 14209                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     149448000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.234676                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                4357                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               56                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency    133950500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.231660                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           4301                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses            1028                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                1028                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_miss_latency     97042000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.994012                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses              2822                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     88136500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994012                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses         2822                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses             17333                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34339.384829                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31151.919476                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                 13009                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency     148483500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.249466                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                4324                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits               52                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency    133081000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.246466                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses           4272                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses            1024                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits                1024                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.731600                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.521086                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses              21416                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34344.019471                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.535184                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  14226                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      246933500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.335730                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 7190                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                56                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    222392000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.333115                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            7134                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_accesses              20172                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34358.452281                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31183.746828                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                  13026                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      245525500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.354253                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 7146                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                52                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency    221217500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.351676                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            7094                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.104167                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.011647                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          3413.355578                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           381.656201                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses             21416                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34344.019471                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.535184                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.103741                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.011357                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3399.382463                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           372.162474                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses             20172                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34358.452281                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31183.746828                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 14226                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     246933500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.335730                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                7190                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               56                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    222392000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.333115                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           7134                       # number of overall MSHR misses
+system.cpu.l2cache.overall_hits                 13026                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     245525500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.354253                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                7146                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits               52                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency    221217500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.351676                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           7094                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                    55                       # number of replacements
-system.cpu.l2cache.sampled_refs                  5231                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                    53                       # number of replacements
+system.cpu.l2cache.sampled_refs                  5193                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3795.011778                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   14289                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              3771.544937                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   13092                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          34606296                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         43565672                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            108215518                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            93620838                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads              1021297842                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               43097547                       # number of misc regfile writes
-system.cpu.numCycles                        430845862                       # number of cpu cycles simulated
+system.cpu.memDep0.conflictingLoads          57304786                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         64927444                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            107131506                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            91507860                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               972227372                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               43097542                       # number of misc regfile writes
+system.cpu.numCycles                        347474600                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles          2009946                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      340171955                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents            2410                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         122720761                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        4353275                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups     1678808180                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       427512132                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    413848551                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          159404950                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        13510644                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       15892137                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          73676593                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups    836456573                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    842351607                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles    117198109                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts     12788197                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           37692284                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts      3543781                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    805385393                       # The number of ROB reads
-system.cpu.rob.rob_writes                   800205802                       # The number of ROB writes
-system.cpu.timesIdled                            2213                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:BlockCycles          9320114                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps      344460442                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents         1304973                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          97580493                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents       14494347                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents              2                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups     1601896967                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts       403426158                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands    392194299                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           65706997                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         7142428                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles       28947021                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps          47733854                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups    827888222                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    774008745                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles    138662461                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts     12572275                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           80571383                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts      3693310                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    721545269                       # The number of ROB reads
+system.cpu.rob.rob_writes                   782665651                       # The number of ROB writes
+system.cpu.timesIdled                            2585                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             191                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
index a5b41f00b..392543608 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -66,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
index 934921226..ec0472b91 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:25
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:29:05
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -18,4 +18,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.210000
-Exiting @ tick 210200321500 because target called exit()
+Exiting @ tick 212344048000 because target called exit()
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
index f26b1f1eb..d8a1a1d08 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 829275                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 237784                       # Number of bytes of host memory used
-host_seconds                                   415.76                       # Real time elapsed on the host
-host_tick_rate                              505582613                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1495798                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 254688                       # Number of bytes of host memory used
+host_seconds                                   233.36                       # Real time elapsed on the host
+host_tick_rate                              909925289                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   344777955                       # Number of instructions simulated
-sim_seconds                                  0.210200                       # Number of seconds simulated
-sim_ticks                                210200321500                       # Number of ticks simulated
+sim_insts                                   349065408                       # Number of instructions simulated
+sim_seconds                                  0.212344                       # Number of seconds simulated
+sim_ticks                                212344048000                       # Number of ticks simulated
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -52,24 +52,24 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        420400644                       # number of cpu cycles simulated
+system.cpu.numCycles                        424688097                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  420400644                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                  424688097                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     16255902                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
 system.cpu.num_fp_insts                     114216705                       # number of float instructions
 system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    12435295                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        344777955                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             283262903                       # Number of integer alu accesses
-system.cpu.num_int_insts                    283262903                       # number of integer instructions
-system.cpu.num_int_register_reads          1207980255                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          211974282                       # number of times the integer registers were written
-system.cpu.num_load_insts                    94652977                       # Number of load instructions
-system.cpu.num_mem_refs                     177028576                       # number of memory refs
+system.cpu.num_insts                        349065408                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             287528428                       # Number of integer alu accesses
+system.cpu.num_int_insts                    287528428                       # number of integer instructions
+system.cpu.num_int_register_reads          1216522338                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          216261597                       # number of times the integer registers were written
+system.cpu.num_load_insts                    94648758                       # Number of load instructions
+system.cpu.num_mem_refs                     177024357                       # number of memory refs
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             191                       # Number of system calls
 
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
index 9c15d1771..8ca4edc2e 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
@@ -166,7 +169,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
index 1f52687a3..3a8c991e1 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:00:13
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:10:13
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -18,4 +18,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.520000
-Exiting @ tick 525825884000 because target called exit()
+Exiting @ tick 525854475000 because target called exit()
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
index b6636f892..5afa5e2b9 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,27 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 394687                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 245492                       # Number of bytes of host memory used
-host_seconds                                   872.59                       # Real time elapsed on the host
-host_tick_rate                              602604420                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 633525                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 262364                       # Number of bytes of host memory used
+host_seconds                                   550.39                       # Real time elapsed on the host
+host_tick_rate                              955417914                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   344399678                       # Number of instructions simulated
-sim_seconds                                  0.525826                       # Number of seconds simulated
-sim_ticks                                525825884000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses           94586725                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 49727.442439                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46727.442439                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               94585118                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       79912000                       # number of ReadReq miss cycles
+sim_insts                                   348687131                       # Number of instructions simulated
+sim_seconds                                  0.525854                       # Number of seconds simulated
+sim_ticks                                525854475000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses        10895                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits            10895                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses           94571611                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 49749.688667                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46749.688667                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               94570005                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency       79898000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000017                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                 1607                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     75091000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses                 1606                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     75080000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000017                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses            1607                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          82063572                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_mshr_misses            1606                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses         10895                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits             10895                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses          82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              82060700                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits              82049805                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency     160160000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000035                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                2872                       # number of WriteReq misses
@@ -30,47 +34,47 @@ system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # m
 system.cpu.dcache.WriteReq_mshr_misses           2872                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               39438.673365                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               39446.538633                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           176650297                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 53599.464166                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 50599.464166                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               176645818                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       240072000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses           176624288                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 53608.307280                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 50608.307280                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               176619810                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       240058000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  4479                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses                  4478                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    226635000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    226624000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             4479                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             4478                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.751814                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           3079.431639                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          176650297                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 53599.464166                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 50599.464166                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.751562                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           3078.396238                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          176624288                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 53608.307280                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              176645818                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      240072000                       # number of overall miss cycles
+system.cpu.dcache.overall_hits              176619810                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      240058000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 4479                       # number of overall misses
+system.cpu.dcache.overall_misses                 4478                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    226635000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    226624000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            4479                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            4478                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                   1332                       # number of replacements
-system.cpu.dcache.sampled_refs                   4479                       # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4478                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3079.431639                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                176645818                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               3078.396238                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                176641600                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      998                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
@@ -94,10 +98,10 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses          348627536                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses          348660359                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 21025.572005                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              348611933                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits              348644756                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency      328062000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000045                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                15603                       # number of ReadReq misses
@@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000045                       # ms
 system.cpu.icache.ReadReq_mshr_misses           15603                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               22342.622124                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               22344.725758                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           348627536                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses           348660359                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 21025.572005                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               348611933                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits               348644756                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency       328062000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000045                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 15603                       # number of demand (read+write) misses
@@ -126,13 +130,13 @@ system.cpu.icache.demand_mshr_misses            15603                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.862305                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1766.001397                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses          348627536                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.862297                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1765.984158                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses          348660359                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 21025.572005                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              348611933                       # number of overall hits
+system.cpu.icache.overall_hits              348644756                       # number of overall hits
 system.cpu.icache.overall_miss_latency      328062000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000045                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                15603                       # number of overall misses
@@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                  13796                       # number of replacements
 system.cpu.icache.sampled_refs                  15603                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1766.001397                       # Cycle average of tags in use
-system.cpu.icache.total_refs                348611933                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1765.984158                       # Cycle average of tags in use
+system.cpu.icache.total_refs                348644756                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses              2856                       # nu
 system.cpu.l2cache.ReadExReq_mshr_miss_latency    114240000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994429                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses         2856                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses             17210                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses             17209                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 13233                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits                 13232                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_miss_latency     206804000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.231087                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.231100                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                3977                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency    159080000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.231087                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.231100                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           3977                       # number of ReadReq MSHR misses
 system.cpu.l2cache.Writeback_accesses             998                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_hits                 998                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.725579                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.725374                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses              20082                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses              20081                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  13249                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits                  13248                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_miss_latency      355316000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.340255                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate          0.340272                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                 6833                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_miss_latency    273320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.340255                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.340272                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses            6833                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.095645                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.010426                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          3134.106018                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           341.623002                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses             20082                       # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::0                  0.095644                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.010425                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3134.059650                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           341.613272                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses             20081                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 13249                       # number of overall hits
+system.cpu.l2cache.overall_hits                 13248                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency     355316000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.340255                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate         0.340272                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                6833                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_miss_latency    273320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.340255                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.340272                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses           6833                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                    48                       # number of replacements
 system.cpu.l2cache.sampled_refs                  4883                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3475.729020                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   13309                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              3475.672922                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   13308                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1051651768                       # number of cpu cycles simulated
+system.cpu.numCycles                       1051708950                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 1051651768                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                 1051708950                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     16255901                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
 system.cpu.num_fp_insts                     114216705                       # number of float instructions
 system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    12435295                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        344399678                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             283262902                       # Number of integer alu accesses
-system.cpu.num_int_insts                    283262902                       # number of integer instructions
-system.cpu.num_int_register_reads          1344047799                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          212263713                       # number of times the integer registers were written
-system.cpu.num_load_insts                    94652977                       # Number of load instructions
-system.cpu.num_mem_refs                     177028576                       # number of memory refs
+system.cpu.num_insts                        348687131                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             287528427                       # Number of integer alu accesses
+system.cpu.num_int_insts                    287528427                       # number of integer instructions
+system.cpu.num_int_register_reads          1352596558                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          216551028                       # number of times the integer registers were written
+system.cpu.num_load_insts                    94648758                       # Number of load instructions
+system.cpu.num_mem_refs                     177024357                       # number of memory refs
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             191                       # Number of system calls
 
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 3820d828c..08bc6d208 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -115,6 +115,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -413,6 +414,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -448,6 +450,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -493,7 +496,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
index f9727ee45..742d795a3 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 21 2011 14:34:16
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 15:06:31
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:10:23
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -1390,4 +1390,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 1106986295500 because target called exit()
+Exiting @ tick 888395700000 because target called exit()
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 5b889551e..ebe1b4a06 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,130 +1,142 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  80651                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 263088                       # Number of bytes of host memory used
-host_seconds                                 22860.92                       # Real time elapsed on the host
-host_tick_rate                               48422649                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  93209                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 261176                       # Number of bytes of host memory used
+host_seconds                                 20227.01                       # Real time elapsed on the host
+host_tick_rate                               43921255                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1843755906                       # Number of instructions simulated
-sim_seconds                                  1.106986                       # Number of seconds simulated
-sim_ticks                                1106986295500                       # Number of ticks simulated
+sim_insts                                  1885343196                       # Number of instructions simulated
+sim_seconds                                  0.888396                       # Number of seconds simulated
+sim_ticks                                888395700000                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                334577290                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups             553224059                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           46883846                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          562377080                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                562377080                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches              258172659                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          41405243                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                320049862                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups             448194519                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect             4209077                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect           36587037                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted          430263617                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                576330823                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                 59151677                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches              291323462                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events          52629133                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   2026424997                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.909862                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.566343                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples   1586798560                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.188150                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.801160                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0   1126460027     55.59%     55.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    528416767     26.08%     81.66% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2    168171926      8.30%     89.96% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     70727286      3.49%     93.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     47338473      2.34%     95.79% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     23657956      1.17%     96.96% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     13792404      0.68%     97.64% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      6454915      0.32%     97.96% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     41405243      2.04%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0    733168598     46.20%     46.20% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1    461552384     29.09%     75.29% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2    183176106     11.54%     86.84% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3     69760651      4.40%     91.23% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4     39275971      2.48%     93.71% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5     21329022      1.34%     95.05% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6     17961260      1.13%     96.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7      7945435      0.50%     96.68% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8     52629133      3.32%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   2026424997                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                1843766922                       # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total   1586798560                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                1885354212                       # Number of instructions committed
 system.cpu.commit.COM:fp_insts               52289415                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts            1619025870                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 631405848                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  908401145                       # Number of memory references committed
+system.cpu.commit.COM:function_calls         41577833                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts            1660589620                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                 631390751                       # Number of loads committed
+system.cpu.commit.COM:membars                    9986                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                  908389617                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts          84212929                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts     1843766922                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls          188261                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts      1168824477                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                  1843755906                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1843755906                       # Number of Instructions Simulated
-system.cpu.cpi                               1.200795                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.200795                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses          714254563                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 34305.782527                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34068.836467                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              712322726                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    66273180000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.002705                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1931837                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            467831                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency  49876981000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002050                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1464006                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         276945664                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35173.008313                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32580.155094                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             276142350                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   28254970000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.002901                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              803314                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits           730842                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   2361149000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000262                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          72472                       # number of WriteReq MSHR misses
+system.cpu.commit.branchMispredicts          42140724                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts     1885354212                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls          211801                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts      1156399971                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                  1885343196                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1885343196                       # Number of Instructions Simulated
+system.cpu.cpi                               0.942423                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.942423                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses        16519                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        36000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits            16516                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency       108000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000182                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.ReadReq_accesses          722622865                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 34341.472519                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34097.365081                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              720694089                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    66237008000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.002669                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              1928776                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            466378                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency  49863918500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.002024                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         1462398                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses         13554                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits             13554                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses         276935679                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 35036.584459                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32455.691504                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             276128738                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   28272456500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.002914                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              806941                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits           734201                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   2360827000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000263                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses          72740                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 10666.666667                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 643.332595                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles::no_targets        13500                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                 649.359320                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               3                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        32000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        40500                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           991200227                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 34560.486788                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33998.618919                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               988465076                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     94528150000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.002759                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2735151                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            1198673                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  52238130000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.001550                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1536478                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses           999558544                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 34546.506272                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34019.577067                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               996822827                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     94509464500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.002737                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2735717                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            1200579                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency  52224745500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.001536                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          1535138                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999786                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4095.125005                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          991200227                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 34560.486788                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33998.618919                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.999736                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4094.919644                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          999558544                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 34546.506272                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34019.577067                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              988465076                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    94528150000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.002759                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2735151                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           1198673                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  52238130000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.001550                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1536478                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits              996822827                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    94509464500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.002737                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2735717                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           1200579                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency  52224745500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.001536                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         1535138                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1532380                       # number of replacements
-system.cpu.dcache.sampled_refs                1536476                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                1531037                       # number of replacements
+system.cpu.dcache.sampled_refs                1535133                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.125005                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                988465092                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              341948000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   106863                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles      223702819                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts      3748475941                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         853302516                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          949015542                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles       187283447                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles         404118                       # Number of cycles decode is unblocking
+system.cpu.dcache.tagsinuse               4094.919644                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                996852921                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              338455000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   107062                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles      151107419                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          10897                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved      90820701                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts      3444690201                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles         769283467                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles          663881028                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles       162526897                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts          20592                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        2526644                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -146,150 +158,150 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                   562377080                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 400588374                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                    1002800662                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes              11586077                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                     2972268197                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                34317                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                86966870                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.254013                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          400588374                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches          334577290                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.342505                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples         2213708442                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.777306                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.798612                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                   576330823                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                 375416464                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                     685697881                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes              13774150                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                     2674548145                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                41436                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                45967312                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.324366                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles          375416464                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches          379201539                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.505269                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples         1749325455                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.017320                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.964953                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1213776792     54.83%     54.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                388415260     17.55%     72.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 93122307      4.21%     76.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 48895921      2.21%     78.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 60943546      2.75%     81.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 76981670      3.48%     85.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 16173405      0.73%     85.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 35829919      1.62%     87.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                279569622     12.63%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1063664133     60.80%     60.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 45709797      2.61%     63.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                107764294      6.16%     69.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 64274521      3.67%     73.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 89788894      5.13%     78.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 63164111      3.61%     82.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 32677214      1.87%     83.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 54411477      3.11%     86.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                227871014     13.03%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           2213708442                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                  66048246                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 52282096                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses          400588374                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  8967.427082                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  5871.293987                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              400557689                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      275165500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000077                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                30685                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits              1813                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    169516000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000072                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           28872                       # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total           1749325455                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                  71543998                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 49528427                       # number of floating regfile writes
+system.cpu.icache.ReadReq_accesses          375416464                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  9589.174687                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  6216.542791                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits              375392982                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency      225173000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000063                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                23482                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               475                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency    143024000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000061                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses           23007                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               13875.010877                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               16320.014868                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           400588374                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  8967.427082                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  5871.293987                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               400557689                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       275165500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000077                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 30685                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits               1813                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    169516000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000072                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            28872                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses           375416464                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  9589.174687                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  6216.542791                       # average overall mshr miss latency
+system.cpu.icache.demand_hits               375392982                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency       225173000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000063                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                 23482                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                475                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency    143024000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000061                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses            23007                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.814790                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1668.688980                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses          400588374                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  8967.427082                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  5871.293987                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.752121                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1540.344515                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses          375416464                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  9589.174687                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  6216.542791                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              400557689                       # number of overall hits
-system.cpu.icache.overall_miss_latency      275165500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000077                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                30685                       # number of overall misses
-system.cpu.icache.overall_mshr_hits              1813                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    169516000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000072                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           28872                       # number of overall MSHR misses
+system.cpu.icache.overall_hits              375392982                       # number of overall hits
+system.cpu.icache.overall_miss_latency      225173000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000063                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                23482                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               475                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency    143024000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000061                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses           23007                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  27162                       # number of replacements
-system.cpu.icache.sampled_refs                  28869                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                  21420                       # number of replacements
+system.cpu.icache.sampled_refs                  23002                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1668.688980                       # Cycle average of tags in use
-system.cpu.icache.total_refs                400557689                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1540.344515                       # Cycle average of tags in use
+system.cpu.icache.total_refs                375392982                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          264150                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                328211891                       # Number of branches executed
-system.cpu.iew.EXEC:nop                        104784                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.050105                       # Inst execution rate
-system.cpu.iew.EXEC:refs                   1122138306                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  367853547                       # Number of stores executed
+system.cpu.idleCycles                        27465946                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                359805156                       # Number of branches executed
+system.cpu.iew.EXEC:nop                         99005                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.327116                       # Inst execution rate
+system.cpu.iew.EXEC:refs                   1136161492                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                  370067841                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                2149736970                       # num instructions consuming a value
-system.cpu.iew.WB:count                    2244737126                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.548413                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                2411359497                       # num instructions consuming a value
+system.cpu.iew.WB:count                    2310892149                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.529668                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1178943946                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.013896                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     2266943895                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts             93876953                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                 4821399                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             976823889                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            9835077                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts          65011197                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            487070109                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts          3012606198                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             754284759                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts         120224771                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts            2324903771                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                 971459                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                1277221062                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.300598                       # insts written-back per cycle
+system.cpu.iew.WB:sent                     2315816685                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts             45692986                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                17451585                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             932904384                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts             231723                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts          12876854                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts            478323402                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts          3041768804                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts             766093651                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          62095934                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts            2358008462                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                1124743                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                   242                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles              187283447                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles               1560865                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                   275                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles              162526897                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles               2446641                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread.0.cacheBlocked           14                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads        12454380                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses         4593                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads        31009134                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses      1377501                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation      2755264                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads         1382                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads    345418040                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores    210074812                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents        2755264                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect     45729465                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       48147488                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads               5403649891                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1668305360                       # number of integer regfile writes
-system.cpu.ipc                               0.832782                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.832782                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation      4866291                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads            5                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads    301513632                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores    201324536                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents        4866291                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect      7718452                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect       37974534                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               5503137315                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1718781055                       # number of integer regfile writes
+system.cpu.ipc                               1.061094                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.061094                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu      1195859034     48.91%     48.91% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult       11168379      0.46%     49.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     49.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     49.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     49.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     49.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     49.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     49.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     49.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd          16846      0.00%     49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu      1183656160     48.91%     48.91% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult       11225256      0.46%     49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd           8912      0.00%     49.37% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     49.37% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     49.37% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     49.37% # Type of FU issued
@@ -300,89 +312,89 @@ system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     49.37% #
 system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     49.37% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     49.37% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     49.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd      1375289      0.06%     49.42% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     49.42% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp      6876473      0.28%     49.70% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt      5501179      0.22%     49.93% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     49.93% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc     23390230      0.96%     50.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     50.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     50.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     50.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      793077280     32.43%     83.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     407863832     16.68%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd      1375289      0.06%     49.43% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     49.43% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp      6876473      0.28%     49.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt      5501174      0.23%     49.94% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     49.94% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc     23385813      0.97%     50.91% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     50.91% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     50.91% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     50.91% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead      791490934     32.70%     83.61% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite     396584385     16.39%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       2445128542                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              60724253                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.024835                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total       2420104396                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt              57562117                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.023785                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu               336      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult            24113      0.04%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead         44167441     72.73%     72.77% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite        16532363     27.23%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu             17939      0.03%      0.03% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult            24113      0.04%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead         45310366     78.72%     78.79% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite        12209699     21.21%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   2213708442                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.104540                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.422226                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples   1749325455                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.383450                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.501844                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0    1044209874     47.17%     47.17% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     536089548     24.22%     71.39% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     282659967     12.77%     84.16% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     162995448      7.36%     91.52% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4     122130271      5.52%     97.04% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      40278652      1.82%     98.86% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6      15378668      0.69%     99.55% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       7181748      0.32%     99.87% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8       2784266      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0     679087816     38.82%     38.82% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1     375608779     21.47%     60.29% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2     324177593     18.53%     78.82% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3     189762671     10.85%     89.67% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4     109320419      6.25%     95.92% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5      45946515      2.63%     98.55% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6      20912326      1.20%     99.74% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7       1710477      0.10%     99.84% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8       2798859      0.16%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   2213708442                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.104408                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                64689412                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads           126628637                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses     56420382                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes          101846831                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses             2441163383                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads         7046405646                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses   2188316744                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes        4055199620                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                 3002666337                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                2445128542                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             9835077                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined      1141792420                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued           8344504                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved        9646816                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined   2082844826                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total   1749325455                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.362064                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                63302900                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads           122479905                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses     59166670                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes           79315867                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses             2414363613                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         6524640046                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses   2251725479                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        4122242728                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                 3041425729                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                2420104396                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded              244070                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined      1156073456                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued             23587                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved          32269                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined   1931732931                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -404,114 +416,115 @@ system.cpu.itb.read_misses                          0                       # DT
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses           72470                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.335527                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.225657                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                6383                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   2279891500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.911922                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             66087                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2048778000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.911922                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        66087                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           1492876                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34237.383587                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.264277                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 77656                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   48453430000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.947982                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1415220                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               39                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency  43870985000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.947956                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1415181                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses              2                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses           72735                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.554826                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.104688                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits                6653                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   2279733500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.908531                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             66082                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2048615000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908531                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        66082                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses           1485400                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34238.677361                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.325576                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                 70955                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   48428726000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.952232                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1414445                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits               27                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency  43847418500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.952214                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1414418                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses              5                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses                2                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        62000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses            2                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          106863                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              106863                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits                  2                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_miss_rate      0.600000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses                3                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency        93000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.600000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses            3                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          107062                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              107062                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.056843                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.052436                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            1565346                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34249.025692                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.307169                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  84039                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    50733321500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.946313                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1481307                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                39                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  45919763000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.946288                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1481268                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_accesses            1558135                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34250.276760                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.360351                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                  77608                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    50708459500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.950192                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              1480527                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                27                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency  45896033500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.950174                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         1480500                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.884785                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.091201                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         28992.645122                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          2988.461105                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses           1565346                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34249.025692                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.307169                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.884303                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.091380                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         28976.831350                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          2994.327644                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses           1558135                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34250.276760                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.360351                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 84039                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   50733321500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.946313                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1481307                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               39                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  45919763000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.946288                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1481268                       # number of overall MSHR misses
+system.cpu.l2cache.overall_hits                 77608                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   50708459500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.950192                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             1480527                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits               27                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency  45896033500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.950174                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        1480500                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               1479999                       # number of replacements
-system.cpu.l2cache.sampled_refs               1512721                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               1479411                       # number of replacements
+system.cpu.l2cache.sampled_refs               1512131                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             31981.106227                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   85987                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             31971.158994                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   79290                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   66099                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          48375882                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        167873780                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            976823889                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           487070109                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads              4207984132                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               14227476                       # number of misc regfile writes
-system.cpu.numCycles                       2213972592                       # number of cpu cycles simulated
+system.cpu.memDep0.conflictingLoads         103195431                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        198192590                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            932904384                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           478323402                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads              3956756575                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               14227477                       # number of misc regfile writes
+system.cpu.numCycles                       1776791401                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         17658494                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps     1482327508                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         4825678                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         919120367                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        8406320                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents              1                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     9255846830                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      3353421825                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   2685986513                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          880460594                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles       187283447                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       23975324                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps        1203659002                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups    485863672                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   8769983158                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles    185210216                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts     19466962                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts          226114383                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts     13965391                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                   4997592808                       # The number of ROB reads
-system.cpu.rob.rob_writes                  6212468368                       # The number of ROB writes
-system.cpu.timesIdled                           87017                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:BlockCycles         26318091                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps     1523914797                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents        14245310                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles         796885476                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        9677436                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents              2                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups     9044956904                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts      3344057735                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands   2666278058                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles          638477320                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles       162526897                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles       33719663                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps        1142363258                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups    419453355                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   8625503549                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles     91398008                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts      8495416                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           83627358                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts       245009                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   4575905265                       # The number of ROB reads
+system.cpu.rob.rob_writes                  6246035428                       # The number of ROB writes
+system.cpu.timesIdled                         1346500                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls            1411                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 97cb6c6e4..161aadfee 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -66,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
index e6fdba858..467c19c32 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:24
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:44:47
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1390,4 +1390,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 924828408500 because target called exit()
+Exiting @ tick 945613131000 because target called exit()
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index 807917422..b4eaa4e1c 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 966272                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 234680                       # Number of bytes of host memory used
-host_seconds                                  1908.12                       # Real time elapsed on the host
-host_tick_rate                              484679459                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1687648                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 251592                       # Number of bytes of host memory used
+host_seconds                                  1117.14                       # Real time elapsed on the host
+host_tick_rate                              846460115                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1843766922                       # Number of instructions simulated
-sim_seconds                                  0.924828                       # Number of seconds simulated
-sim_ticks                                924828408500                       # Number of ticks simulated
+sim_insts                                  1885336367                       # Number of instructions simulated
+sim_seconds                                  0.945613                       # Number of seconds simulated
+sim_ticks                                945613131000                       # Number of ticks simulated
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -52,24 +52,24 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1849656818                       # number of cpu cycles simulated
+system.cpu.numCycles                       1891226263                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 1849656818                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                 1891226263                       # Number of busy cycles
+system.cpu.num_conditional_control_insts    223597262                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
 system.cpu.num_fp_insts                      52289415                       # number of float instructions
 system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    84508263                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                       1843766922                       # Number of instructions executed
-system.cpu.num_int_alu_accesses            1619025871                       # Number of integer alu accesses
-system.cpu.num_int_insts                   1619025871                       # number of integer instructions
-system.cpu.num_int_register_reads          4830749754                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1365217022                       # number of times the integer registers were written
-system.cpu.num_load_insts                   631405848                       # Number of load instructions
-system.cpu.num_mem_refs                     908401146                       # number of memory refs
+system.cpu.num_insts                       1885336367                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1660575345                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1660575345                       # number of integer instructions
+system.cpu.num_int_register_reads          4913858688                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1405410845                       # number of times the integer registers were written
+system.cpu.num_load_insts                   631387182                       # Number of load instructions
+system.cpu.num_mem_refs                     908382480                       # number of memory refs
 system.cpu.num_store_insts                  276995298                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            1411                       # Number of system calls
 
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index dfd8de545..734b01f7e 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
@@ -166,7 +169,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
index b556adbf3..871cc997a 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:25
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:10:25
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1390,4 +1390,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 2369896178000 because target called exit()
+Exiting @ tick 2369901960000 because target called exit()
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 1e3225702..ae9492554 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,27 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 494422                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 242392                       # Number of bytes of host memory used
-host_seconds                                  3706.70                       # Real time elapsed on the host
-host_tick_rate                              639353926                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 678497                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 259312                       # Number of bytes of host memory used
+host_seconds                                  2762.35                       # Real time elapsed on the host
+host_tick_rate                              857930242                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1832675505                       # Number of instructions simulated
-sim_seconds                                  2.369896                       # Number of seconds simulated
-sim_ticks                                2369896178000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses          620364065                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 54567.414542                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51567.414542                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              618902904                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    79731778000                       # number of ReadReq miss cycles
+sim_insts                                  1874244950                       # Number of instructions simulated
+sim_seconds                                  2.369902                       # Number of seconds simulated
+sim_ticks                                2369901960000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses         9985                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits             9985                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses          620335414                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              618874541                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    79725982000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.002355                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1461161                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  75348295000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses              1460873                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  75343363000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.002355                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1461161                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         276945663                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_mshr_misses         1460873                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses          9985                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits              9985                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses         276935678                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             276872883                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits             276862898                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency    3794826000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000263                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses               72780                       # number of WriteReq misses
@@ -30,48 +34,48 @@ system.cpu.dcache.WriteReq_mshr_miss_rate     0.000263                       # m
 system.cpu.dcache.WriteReq_mshr_misses          72780                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 583.970170                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                 584.067849                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           897309728                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54452.292494                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51452.292494                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               895775787                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     83526604000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses           897271092                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 54458.738711                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               895737439                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     83520808000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.001709                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1533941                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses               1533653                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  78924781000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  78919849000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.001709                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1533941                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses          1533653                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999748                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4094.966269                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          897309728                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54452.292494                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51452.292494                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.999746                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4094.960333                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          897271092                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 54458.738711                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              895775787                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    83526604000                       # number of overall miss cycles
+system.cpu.dcache.overall_hits              895737439                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    83520808000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.001709                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1533941                       # number of overall misses
+system.cpu.dcache.overall_misses              1533653                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  78924781000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  78919849000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.001709                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1533941                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses         1533653                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1529845                       # number of replacements
-system.cpu.dcache.sampled_refs                1533941                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                1529557                       # number of replacements
+system.cpu.dcache.sampled_refs                1533653                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.966269                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                895775787                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              993944000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tagsinuse               4094.960333                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                895757409                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              997882000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   107259                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
@@ -94,10 +98,10 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses         1390241555                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses         1390271511                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 18786.850477                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits             1390221752                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits             1390251708                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency      372036000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                19803                       # number of ReadReq misses
@@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000014                       # ms
 system.cpu.icache.ReadReq_mshr_misses           19803                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               70202.583043                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               70204.095743                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses          1390241555                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses          1390271511                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 18786.850477                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
-system.cpu.icache.demand_hits              1390221752                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits              1390251708                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency       372036000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000014                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 19803                       # number of demand (read+write) misses
@@ -127,12 +131,12 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.occ_%::0                   0.679846                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1392.325384                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses         1390241555                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0           1392.324437                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses         1390271511                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 18786.850477                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits             1390221752                       # number of overall hits
+system.cpu.icache.overall_hits             1390251708                       # number of overall hits
 system.cpu.icache.overall_miss_latency      372036000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000014                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                19803                       # number of overall misses
@@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                  18364                       # number of replacements
 system.cpu.icache.sampled_refs                  19803                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1392.325384                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1390221752                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1392.324437                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1390251708                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses             66093                       # nu
 system.cpu.l2cache.ReadExReq_mshr_miss_latency   2643720000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908120                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses        66093                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           1480964                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses           1480676                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 67385                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   73506108000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.954499                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1413579                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  56543160000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.954499                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1413579                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits                 67139                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   73503924000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.954657                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1413537                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  56541480000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.954657                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1413537                       # number of ReadReq MSHR misses
 system.cpu.l2cache.Writeback_accesses          107259                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_hits              107259                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.050081                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.049920                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            1553744                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses            1553456                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  74072                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    76942944000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.952327                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1479672                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                  73826                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    76940760000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.952476                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              1479630                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  59186880000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.952327                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1479672                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency  59185200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.952476                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         1479630                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.881760                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.092816                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         28893.501877                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          3041.393075                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses           1553744                       # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::0                  0.881757                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.092817                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         28893.420796                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          3041.423322                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses           1553456                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 74072                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   76942944000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.952327                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1479672                       # number of overall misses
+system.cpu.l2cache.overall_hits                 73826                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   76940760000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.952476                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             1479630                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  59186880000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.952327                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1479672                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency  59185200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.952476                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        1479630                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               1478797                       # number of replacements
-system.cpu.l2cache.sampled_refs               1511517                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               1478755                       # number of replacements
+system.cpu.l2cache.sampled_refs               1511475                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             31934.894953                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   75699                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             31934.844118                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   75453                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   66099                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       4739792356                       # number of cpu cycles simulated
+system.cpu.numCycles                       4739803920                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 4739792356                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                 4739803920                       # Number of busy cycles
+system.cpu.num_conditional_control_insts    223597262                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
 system.cpu.num_fp_insts                      52289415                       # number of float instructions
 system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    84508263                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                       1832675505                       # Number of instructions executed
-system.cpu.num_int_alu_accesses            1619025871                       # Number of integer alu accesses
-system.cpu.num_int_insts                   1619025871                       # number of integer instructions
-system.cpu.num_int_register_reads          5455211671                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1365288731                       # number of times the integer registers were written
-system.cpu.num_load_insts                   631405848                       # Number of load instructions
-system.cpu.num_mem_refs                     908401146                       # number of memory refs
+system.cpu.num_insts                       1874244950                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1660575345                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1660575345                       # number of integer instructions
+system.cpu.num_int_register_reads          5538311924                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1405482554                       # number of times the integer registers were written
+system.cpu.num_load_insts                   631387182                       # Number of load instructions
+system.cpu.num_mem_refs                     908382480                       # number of memory refs
 system.cpu.num_store_insts                  276995298                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            1411                       # Number of system calls
 
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
index 2381c9471..3fb22d702 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -115,6 +115,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -413,6 +414,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -448,6 +450,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -493,7 +496,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
index cc72d4e35..4992cad53 100755
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 21 2011 14:34:16
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 14:37:23
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:10:13
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 59259968500 because target called exit()
+Exiting @ tick 42429858000 because target called exit()
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 0492b80a2..3695b79a3 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,130 +1,142 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  56888                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 265416                       # Number of bytes of host memory used
-host_seconds                                  1737.33                       # Real time elapsed on the host
-host_tick_rate                               34109858                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 115309                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 263676                       # Number of bytes of host memory used
+host_seconds                                   872.72                       # Real time elapsed on the host
+host_tick_rate                               48617676                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    98832525                       # Number of instructions simulated
-sim_seconds                                  0.059260                       # Number of seconds simulated
-sim_ticks                                 59259968500                       # Number of ticks simulated
+sim_insts                                   100632835                       # Number of instructions simulated
+sim_seconds                                  0.042430                       # Number of seconds simulated
+sim_ticks                                 42429858000                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 10631378                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              17355234                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect             914560                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           17451384                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 17451384                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               12133384                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           1268932                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                  9648133                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              15114739                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect              120896                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect             708230                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           11837178                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 18100814                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  1938552                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches               13645712                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events           1956948                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    114018356                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.866861                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.400758                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples     81664789                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.232335                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.714285                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     59417509     52.11%     52.11% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     36575314     32.08%     84.19% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      7815755      6.85%     91.05% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      3335760      2.93%     93.97% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      3218603      2.82%     96.79% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      1142107      1.00%     97.80% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       823062      0.72%     98.52% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       421314      0.37%     98.89% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      1268932      1.11%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0     35836252     43.88%     43.88% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1     24456690     29.95%     73.83% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2      7408660      9.07%     82.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3      5445972      6.67%     89.57% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4      4443469      5.44%     95.01% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5      1356942      1.66%     96.67% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6       506701      0.62%     97.29% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7       253155      0.31%     97.60% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8      1956948      2.40%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    114018356                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                  98838077                       # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total     81664789                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                 100638387                       # Number of instructions committed
 system.cpu.commit.COM:fp_insts                     56                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts              89710266                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  27315295                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   47871033                       # Number of memory references committed
+system.cpu.commit.COM:function_calls          1679850                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts              91477547                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                  27308299                       # Number of loads committed
+system.cpu.commit.COM:membars                   15920                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                   47865227                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts           2496729                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts       98838077                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls          667791                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        18231502                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                    98832525                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              98832525                       # Number of Instructions Simulated
-system.cpu.cpi                               1.199200                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.199200                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses           28495395                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 22616.985978                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18828.121969                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               28388707                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     2412961000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.003744                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               106688                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits             49985                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   1067611000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001990                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses           56703                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          19865820                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32612.833902                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34110.141072                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              18320717                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   50390187500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.077777                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1545103                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1438349                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   3641394000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005374                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         106754                       # number of WriteReq MSHR misses
+system.cpu.commit.branchMispredicts            703198                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts      100638387                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls          700820                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts        14515398                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                   100632835                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             100632835                       # Number of Instructions Simulated
+system.cpu.cpi                               0.843261                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.843261                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses        18610                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 13134.615385                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits            18584                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency       341500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.001397                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses             26                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits           26                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.ReadReq_accesses           27269611                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 22490.604159                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18794.207345                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               27168396                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency     2276386500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.003712                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               101215                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits             46784                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency   1022987500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001996                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses           54431                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses         17109                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits             17109                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 32466.100488                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34204.996866                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              18297917                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   50386868500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.078186                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1551984                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          1445097                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   3656069500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005385                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         106887                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        21500                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 285.786132                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles::no_targets        17500                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                 282.067538                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        21500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        17500                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            48361215                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 31967.209229                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 28808.830457                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                46709424                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     52803148500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.034155                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1651791                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            1488334                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   4709005000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.003380                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           163457                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses            47119512                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 31855.363450                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 29005.176112                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                45466313                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     52663255000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.035085                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1653199                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            1491881                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency   4679057000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.003424                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           161318                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995663                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4078.236312                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses           48361215                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 31967.209229                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 28808.830457                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.995259                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4076.580163                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses           47119512                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 31855.363450                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 29005.176112                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               46709424                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    52803148500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.034155                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1651791                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           1488334                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   4709005000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.003380                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          163457                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits               45466313                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    52663255000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.035085                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1653199                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           1491881                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency   4679057000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.003424                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          161318                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 159346                       # number of replacements
-system.cpu.dcache.sampled_refs                 163442                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                 157220                       # number of replacements
+system.cpu.dcache.sampled_refs                 161316                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4078.236312                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 46709457                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              393981000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   124385                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       14942635                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts       127014816                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          27511316                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           70998383                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         3514410                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles         566021                       # Number of cycles decode is unblocking
+system.cpu.dcache.tagsinuse               4076.580163                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 45502007                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              331251000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   123262                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       33824964                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          92972                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved       3728578                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts       120838990                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          25532965                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           21535228                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         2196298                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts         331340                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles         771631                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -146,243 +158,243 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                    17451384                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  12122691                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      73872078                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                 96174                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                       95885018                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                33989                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                 2507758                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.147244                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           12122691                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           10631378                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.809020                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          117532765                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.108179                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.634526                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                    18100814                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                  11605237                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                      22692685                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                153016                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                       89098054                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                32223                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                  835942                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.213303                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles           11605237                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches           11586685                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.049945                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples           83861086                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.470767                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.783294                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 43865579     37.32%     37.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 53998302     45.94%     83.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9118939      7.76%     91.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  3358983      2.86%     93.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1352835      1.15%     95.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   476061      0.41%     95.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1116300      0.95%     96.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   521407      0.44%     96.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  3724359      3.17%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 61184703     72.96%     72.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2309063      2.75%     75.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2572532      3.07%     78.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2218385      2.65%     81.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1638972      1.95%     83.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1774046      2.12%     85.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   996638      1.19%     86.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1509113      1.80%     88.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9657634     11.52%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            117532765                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       40                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses           12122691                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 12759.444122                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  9477.015634                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               12098549                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      308038500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.001991                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                24142                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               539                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    223686000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.001947                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           23603                       # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total             83861086                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                       348                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      308                       # number of floating regfile writes
+system.cpu.icache.ReadReq_accesses           11605237                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 12815.490689                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  9320.206177                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               11579783                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency      326205500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.002193                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                25454                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               912                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency    228736500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.002115                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses           24542                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                 512.911184                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                 471.854570                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            12122691                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 12759.444122                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  9477.015634                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                12098549                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       308038500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.001991                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 24142                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                539                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    223686000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.001947                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            23603                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses            11605237                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 12815.490689                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  9320.206177                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                11579783                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency       326205500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.002193                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                 25454                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                912                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency    228736500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.002115                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses            24542                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.878284                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1798.726219                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses           12122691                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 12759.444122                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  9477.015634                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.876963                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1796.020608                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses           11605237                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 12815.490689                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  9320.206177                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               12098549                       # number of overall hits
-system.cpu.icache.overall_miss_latency      308038500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.001991                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                24142                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               539                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    223686000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.001947                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           23603                       # number of overall MSHR misses
+system.cpu.icache.overall_hits               11579783                       # number of overall hits
+system.cpu.icache.overall_miss_latency      326205500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.002193                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                25454                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               912                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency    228736500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.002115                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses           24542                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  21558                       # number of replacements
-system.cpu.icache.sampled_refs                  23588                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                  22507                       # number of replacements
+system.cpu.icache.sampled_refs                  24541                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1798.726219                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 12098549                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1796.020608                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 11579783                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          987173                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 13347127                       # Number of branches executed
-system.cpu.iew.EXEC:nop                        107693                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.902867                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     50902907                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   21266903                       # Number of stores executed
+system.cpu.idleCycles                          998631                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                 14720525                       # Number of branches executed
+system.cpu.iew.EXEC:nop                         89802                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.245286                       # Inst execution rate
+system.cpu.iew.EXEC:refs                     49064418                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                   20899088                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  83917558                       # num instructions consuming a value
-system.cpu.iew.WB:count                     104895459                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.516831                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                 110564194                       # num instructions consuming a value
+system.cpu.iew.WB:count                     105075118                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.489698                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  43371156                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.885045                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      106112224                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts              2628306                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                  987032                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              32508348                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            1016199                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           2305298                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             23389031                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           117101013                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              29636004                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2065127                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             107007708                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                   2101                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                  54143071                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.238221                       # insts written-back per cycle
+system.cpu.iew.WB:sent                      105316682                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts               772856                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                 1030923                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts              29917156                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts             748831                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts            540612                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts             22494076                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts           115228257                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              28165330                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            744036                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             105674596                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                  10554                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                   908                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                3514410                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                 39551                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                  9453                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                2196298                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                 59055                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread.0.cacheBlocked            5                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads          247077                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses         2317                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads          693039                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses         2022                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation        39532                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads            7                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads      5193052                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores      2833293                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents          39532                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      1768078                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect         860228                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                255733219                       # number of integer regfile reads
-system.cpu.int_regfile_writes                78479500                       # number of integer regfile writes
-system.cpu.ipc                               0.833889                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.833889                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation        44278                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads           42                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads      2608845                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores      1937136                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents          44278                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       252630                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect         520226                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                252581804                       # number of integer regfile reads
+system.cpu.int_regfile_writes                78295108                       # number of integer regfile writes
+system.cpu.ipc                               1.185873                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.185873                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        57280423     52.52%     52.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          80354      0.07%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd           124      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              1      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            7      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     52.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       30140240     27.63%     80.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      21571686     19.78%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu        56936434     53.50%     53.50% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult          90757      0.09%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd            60      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd              6      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            7      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     53.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead       28415464     26.70%     80.29% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite      20975911     19.71%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        109072835                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               1323141                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.012131                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total        106418639                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt               1769080                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.016624                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu              1305      0.10%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          1094337     82.71%     82.81% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          227499     17.19%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu             82343      4.65%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      4.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead          1571781     88.85%     93.50% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite          114956      6.50%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    117532765                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.928021                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.124128                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples     83861086                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.268987                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.445189                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      53487199     45.51%     45.51% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      35551116     30.25%     75.76% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      18289887     15.56%     91.32% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       5815919      4.95%     96.27% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       2890149      2.46%     98.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       1119018      0.95%     99.68% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6        322627      0.27%     99.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7         52060      0.04%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8          4790      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0      32249828     38.46%     38.46% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      23882071     28.48%     66.93% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2      13427667     16.01%     82.95% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3       6314911      7.53%     90.48% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4       4996611      5.96%     96.43% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5       1765354      2.11%     98.54% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6        709016      0.85%     99.39% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7        455833      0.54%     99.93% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8         59795      0.07%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    117532765                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.920291                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                     187                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                 370                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           59                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                568                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses              110395789                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          337069521                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    104895400                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         134025371                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  115977121                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 109072835                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             1016199                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        16994478                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued             68315                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved         348408                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined     30228049                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total     83861086                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.254054                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                     126                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                 248                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           98                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                372                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              108187593                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          298548100                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    105075020                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         129476414                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                  114372601                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                 106418639                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded              765854                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined        14297482                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued             80911                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved          65034                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined     24667303                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -404,117 +416,114 @@ system.cpu.itb.read_misses                          0                       # DT
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          106739                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34385.177402                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31198.626723                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                4429                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   3517947500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.958506                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            102310                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   3191931500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.958506                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       102310                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses             80290                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34268.464842                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31112.930905                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 46997                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1140900000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.414659                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               33293                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               78                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1033416000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.413688                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          33215                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses             15                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency         3450                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31300                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_hits                  5                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_miss_latency        34500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate      0.666667                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses               10                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       313000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.666667                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses           10                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          124385                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              124385                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_accesses          106886                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34447.118852                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31261.705881                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits                4288                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   3534205500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.959882                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            102598                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   3207388500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.959882                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       102598                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses             78971                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34178.924225                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31045.290979                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                 46678                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1103740000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.408922                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               32293                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits               57                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1000776000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.408200                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          32236                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          123262                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              123262                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.522459                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.512422                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             187029                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34356.522348                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31177.624055                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  51426                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     4658847500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.725037                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               135603                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                78                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   4225347500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.724620                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          135525                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_accesses             185857                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34382.912870                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31209.965587                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                  50966                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     4637945500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.725778                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               134891                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                57                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency   4208164500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.725472                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          134834                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.075665                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.490596                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          2479.385320                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16075.863563                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses            187029                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34356.522348                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31177.624055                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.069881                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.489057                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2289.872639                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16025.414403                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses            185857                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34382.912870                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31209.965587                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 51426                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    4658847500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.725037                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              135603                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               78                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   4225347500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.724620                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         135525                       # number of overall MSHR misses
+system.cpu.l2cache.overall_hits                 50966                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    4637945500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.725778                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              134891                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits               57                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency   4208164500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.725472                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         134834                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                115260                       # number of replacements
-system.cpu.l2cache.sampled_refs                134133                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                114591                       # number of replacements
+system.cpu.l2cache.sampled_refs                133433                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18555.248883                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   70079                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             18315.287042                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   68374                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   88459                       # number of writebacks
-system.cpu.memDep0.conflictingLoads           7990320                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         10924699                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             32508348                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            23389031                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               153116664                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1948149                       # number of misc regfile writes
-system.cpu.numCycles                        118519938                       # number of cpu cycles simulated
+system.cpu.l2cache.writebacks                   88457                       # number of writebacks
+system.cpu.memDep0.conflictingLoads          22231521                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         18598246                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             29917156                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            22494076                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               145950656                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1948148                       # number of misc regfile writes
+system.cpu.numCycles                         84859717                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles          1866182                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       74745628                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents            1883                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          30389111                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents         833533                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents              4                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      333388241                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       124050583                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands     93358664                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           68672664                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         3514410                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        1591236                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          18613033                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups        83717                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    333304524                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles     11499162                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts       818368                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts            3724501                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts       819368                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    229793704                       # The number of ROB reads
-system.cpu.rob.rob_writes                   237655161                       # The number of ROB writes
-system.cpu.timesIdled                           60746                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:BlockCycles          3837556                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps       76545937                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents          321924                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          27362593                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        4158532                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents              1                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups      316348591                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts       118493995                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands     91447203                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           20319316                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         2196298                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles        5609683                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps          14901230                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups        85544                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    316263047                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles     24535640                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts       768991                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           14793505                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts       769620                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    194836327                       # The number of ROB reads
+system.cpu.rob.rob_writes                   232505480                       # The number of ROB writes
+system.cpu.timesIdled                           60947                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
index d284ed163..8908b70ed 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -66,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
index 4cf2e23b7..e76d85acc 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:25
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:12:03
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 53034982000 because target called exit()
+Exiting @ tick 53932162000 because target called exit()
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index a170aadf3..a0efd159d 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 986864                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 237100                       # Number of bytes of host memory used
-host_seconds                                   100.15                       # Real time elapsed on the host
-host_tick_rate                              529534290                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1751644                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 253996                       # Number of bytes of host memory used
+host_seconds                                    57.45                       # Real time elapsed on the host
+host_tick_rate                              938757926                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    98838077                       # Number of instructions simulated
-sim_seconds                                  0.053035                       # Number of seconds simulated
-sim_ticks                                 53034982000                       # Number of ticks simulated
+sim_insts                                   100632437                       # Number of instructions simulated
+sim_seconds                                  0.053932                       # Number of seconds simulated
+sim_ticks                                 53932162000                       # Number of ticks simulated
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -52,24 +52,24 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        106069965                       # number of cpu cycles simulated
+system.cpu.numCycles                        107864325                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  106069965                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                  107864325                       # Number of busy cycles
+system.cpu.num_conditional_control_insts      8896554                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
 system.cpu.num_fp_insts                            56                       # number of float instructions
 system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     3336597                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                         98838077                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              89710267                       # Number of integer alu accesses
-system.cpu.num_int_insts                     89710267                       # number of integer instructions
-system.cpu.num_int_register_reads           258410605                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           73280343                       # number of times the integer registers were written
-system.cpu.num_load_insts                    27315295                       # Number of load instructions
-system.cpu.num_mem_refs                      47871034                       # number of memory refs
+system.cpu.num_insts                        100632437                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              91472788                       # Number of integer alu accesses
+system.cpu.num_int_insts                     91472788                       # number of integer instructions
+system.cpu.num_int_register_reads           261951567                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           75074702                       # number of times the integer registers were written
+system.cpu.num_load_insts                    27307109                       # Number of load instructions
+system.cpu.num_mem_refs                      47862848                       # number of memory refs
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
 
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
index 0e5c2c18c..be517e6da 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
@@ -166,7 +169,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index 54e01817e..1c30be5f8 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:25
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:26:17
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 133078695000 because target called exit()
+Exiting @ tick 133117442000 because target called exit()
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index b20318b2f..310405f1b 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,78 +1,82 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 430473                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 244816                       # Number of bytes of host memory used
-host_seconds                                   227.65                       # Real time elapsed on the host
-host_tick_rate                              584574230                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 759848                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 261720                       # Number of bytes of host memory used
+host_seconds                                   131.33                       # Real time elapsed on the host
+host_tick_rate                             1013599729                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    97997303                       # Number of instructions simulated
-sim_seconds                                  0.133079                       # Number of seconds simulated
-sim_ticks                                133078695000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses           27164439                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35146.149639                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32146.149639                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               27111418                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     1863484000                       # number of ReadReq miss cycles
+sim_insts                                    99791663                       # Number of instructions simulated
+sim_seconds                                  0.133117                       # Number of seconds simulated
+sim_ticks                                133117442000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses        15919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits            15919                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses           27140334                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               27087368                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency     1862630000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.001952                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                53021                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1704421000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses                52966                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1703732000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.001952                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses           53021                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          19865820                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 54270.699030                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51270.699030                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              19758786                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    5808810000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.005388                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              107034                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   5487708000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005388                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         107034                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses           52966                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses         15919                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits             15919                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              19742869                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    5808782000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.005392                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              107032                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   5487686000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005392                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         107032                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 292.838112                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                 292.891630                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            47030259                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 47935.359720                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 44935.359720                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                46870204                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency      7672294000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.003403                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                160055                       # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses            46990235                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 47946.924337                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                46830237                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      7671412000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.003405                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                159998                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   7192129000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.003403                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           160055                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency   7191418000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.003405                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           159998                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995347                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4076.942972                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses           47030259                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 47935.359720                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 44935.359720                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.995345                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4076.934010                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses           46990235                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 47946.924337                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               46870204                       # number of overall hits
-system.cpu.dcache.overall_miss_latency     7672294000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.003403                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               160055                       # number of overall misses
+system.cpu.dcache.overall_hits               46830237                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     7671412000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.003405                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               159998                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   7192129000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.003403                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          160055                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency   7191418000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.003405                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          159998                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 155959                       # number of replacements
-system.cpu.dcache.sampled_refs                 160055                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                 155902                       # number of replacements
+system.cpu.dcache.sampled_refs                 159998                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4076.942972                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 46870204                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             1079223000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   122819                       # number of writebacks
+system.cpu.dcache.tagsinuse               4076.934010                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 46862075                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             1079641000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   122808                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -94,10 +98,10 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses           78097320                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses           78145078                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 24211.233340                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               78078412                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits               78126170                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency      457786000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000242                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                18908                       # number of ReadReq misses
@@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000242                       # ms
 system.cpu.icache.ReadReq_mshr_misses           18908                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                4129.385022                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                4131.910831                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            78097320                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses            78145078                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 24211.233340                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                78078412                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits                78126170                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency       457786000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000242                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 18908                       # number of demand (read+write) misses
@@ -126,13 +130,13 @@ system.cpu.icache.demand_mshr_misses            18908                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.847769                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1736.230096                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses           78097320                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.847746                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1736.182852                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses           78145078                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 24211.233340                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               78078412                       # number of overall hits
+system.cpu.icache.overall_hits               78126170                       # number of overall hits
 system.cpu.icache.overall_miss_latency      457786000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000242                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                18908                       # number of overall misses
@@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                  16890                       # number of replacements
 system.cpu.icache.sampled_refs                  18908                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1736.230096                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 78078412                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1736.182852                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 78126170                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -171,94 +175,94 @@ system.cpu.itb.read_misses                          0                       # DT
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          107034                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          107032                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                4407                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits                4405                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_miss_latency   5336604000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.958826                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.958844                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses            102627                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency   4105080000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.958826                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.958844                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses       102627                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses             71929                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses             71874                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 40637                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1627184000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.435040                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               31292                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1251680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.435040                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          31292                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          122819                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              122819                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                 40584                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1627080000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.435345                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               31290                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1251600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.435345                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          31290                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          122808                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              122808                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.466930                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.466454                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             178963                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses             178906                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  45044                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     6963788000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.748306                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               133919                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                  44989                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     6963684000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.748533                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               133917                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   5356760000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.748306                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          133919                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   5356680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.748533                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          133917                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.066136                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.489058                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          2167.134157                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16025.466133                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses            178963                       # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::0                  0.066099                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.489066                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2165.921088                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16025.699940                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses            178906                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 45044                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    6963788000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.748306                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              133919                       # number of overall misses
+system.cpu.l2cache.overall_hits                 44989                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    6963684000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.748533                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              133917                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   5356760000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.748306                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         133919                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   5356680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.748533                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         133917                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                113661                       # number of replacements
-system.cpu.l2cache.sampled_refs                132491                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                113660                       # number of replacements
+system.cpu.l2cache.sampled_refs                132489                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18192.600290                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   61864                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             18191.621028                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   61800                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   88450                       # number of writebacks
+system.cpu.l2cache.writebacks                   88449                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        266157390                       # number of cpu cycles simulated
+system.cpu.numCycles                        266234884                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  266157390                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                  266234884                       # Number of busy cycles
+system.cpu.num_conditional_control_insts      8896554                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
 system.cpu.num_fp_insts                            56                       # number of float instructions
 system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     3336597                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                         97997303                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              89710267                       # Number of integer alu accesses
-system.cpu.num_int_insts                     89710267                       # number of integer instructions
-system.cpu.num_int_register_reads           285424208                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           73333595                       # number of times the integer registers were written
-system.cpu.num_load_insts                    27315295                       # Number of load instructions
-system.cpu.num_mem_refs                      47871034                       # number of memory refs
+system.cpu.num_insts                         99791663                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              91472788                       # Number of integer alu accesses
+system.cpu.num_int_insts                     91472788                       # number of integer instructions
+system.cpu.num_int_register_reads           288972903                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           75127954                       # number of times the integer registers were written
+system.cpu.num_load_insts                    27307109                       # Number of load instructions
+system.cpu.num_mem_refs                      47862848                       # number of memory refs
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
 
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 731b0df43..279a7d642 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -115,6 +115,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -413,6 +414,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -448,6 +450,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -493,7 +496,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
index 49878baf7..6921d0bca 100755
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 21 2011 14:34:16
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 14:34:24
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:24:58
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
@@ -29,4 +29,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 741617860500 because target called exit()
+Exiting @ tick 683557152000 because target called exit()
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 19a103b3c..e886e17b6 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,130 +1,142 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  95203                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 256912                       # Number of bytes of host memory used
-host_seconds                                 17955.42                       # Real time elapsed on the host
-host_tick_rate                               41303275                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 125996                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 255276                       # Number of bytes of host memory used
+host_seconds                                 13675.60                       # Real time elapsed on the host
+host_tick_rate                               49983689                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1709408664                       # Number of instructions simulated
-sim_seconds                                  0.741618                       # Number of seconds simulated
-sim_ticks                                741617860500                       # Number of ticks simulated
+sim_insts                                  1723073909                       # Number of instructions simulated
+sim_seconds                                  0.683557                       # Number of seconds simulated
+sim_ticks                                683557152000                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                251301725                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups             290055524                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           20139557                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          310557354                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                310557354                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches              203576342                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          41094487                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                234099742                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups             270988691                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                 420                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect           18127020                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted          253531298                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                308386285                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                 18030825                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches              213462255                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events          50936466                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   1326705477                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.288461                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.905257                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples   1236667650                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.393320                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     2.013912                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    628813054     47.40%     47.40% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    321601613     24.24%     71.64% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2    154175798     11.62%     83.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     85373201      6.43%     89.69% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     35866236      2.70%     92.40% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     27097363      2.04%     94.44% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     13157860      0.99%     95.43% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7     19525865      1.47%     96.90% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     41094487      3.10%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0    558967899     45.20%     45.20% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1    311836050     25.22%     70.42% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2    140294902     11.34%     81.76% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3     77547164      6.27%     88.03% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4     37361268      3.02%     91.05% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5     31181150      2.52%     93.57% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6     14635226      1.18%     94.76% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7     13907525      1.12%     95.88% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8     50936466      4.12%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   1326705477                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                1709408682                       # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total   1236667650                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                1723073927                       # Number of instructions committed
 system.cpu.commit.COM:fp_insts                     36                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts            1523276792                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 485926830                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  660773875                       # Number of memory references committed
+system.cpu.commit.COM:function_calls         13665177                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts            1536941901                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                 485926783                       # Number of loads committed
+system.cpu.commit.COM:membars                      62                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                  660773841                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts          30574219                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts     1709408682                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls             333                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       722443769                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                  1709408664                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1709408664                       # Number of Instructions Simulated
-system.cpu.cpi                               0.867689                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.867689                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses          536310912                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14847.958953                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11472.623282                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              528392695                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency   117569361000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.014764                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              7918217                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            262533                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency  87830778500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.014275                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         7655684                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         172586108                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 23573.653690                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20855.792552                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             168355229                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   99737276351                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.024515                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             4230879                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          2338748                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency  39461891617                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.010963                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        1892131                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  3127.531526                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 19937.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  72.974594                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs             25122                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               8                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs     78569847                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       159500                       # number of cycles access was blocked
+system.cpu.commit.branchMispredicts          18126668                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts     1723073927                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls             469                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts       561262265                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                  1723073909                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1723073909                       # Number of Instructions Simulated
+system.cpu.cpi                               0.793416                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.793416                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses           89                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 38333.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits               86                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency       115000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.033708                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.ReadReq_accesses          507538299                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14918.210159                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11490.115727                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              499588577                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency   118595623500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.015663                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              7949722                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            299488                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency  87902074000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.015073                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         7650234                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses            74                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits                74                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 23458.776949                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20845.524839                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             168361233                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   99108969278                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.024479                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             4224814                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          2332947                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency  39436960540                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.010962                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses        1891867                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  3129.028905                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 19277.777778                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                  70.000304                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs             25082                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               9                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs     78482303                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       173500                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           708897020                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 17886.650772                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 13332.125739                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               696747924                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    217306637351                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.017138                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses              12149096                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            2601281                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 127292670117                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.013469                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          9547815                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses           680124346                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 17881.962218                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 13344.968214                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               667949810                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency    217704592778                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.017900                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses              12174536                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            2632435                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 127339034540                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.014030                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          9542101                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997303                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4084.953054                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          708897020                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 17886.650772                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 13332.125739                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.997946                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4087.586245                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          680124346                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 17881.962218                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 13344.968214                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              696747924                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   217306637351                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.017138                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses             12149096                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           2601281                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 127292670117                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.013469                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         9547815                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits              667949810                       # number of overall hits
+system.cpu.dcache.overall_miss_latency   217704592778                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.017900                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses             12174536                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           2632435                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 127339034540                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.014030                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         9542101                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                9543719                       # number of replacements
-system.cpu.dcache.sampled_refs                9547815                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                9538005                       # number of replacements
+system.cpu.dcache.sampled_refs                9542101                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4084.953054                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                696747924                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             7250729000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  3122334                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles      116148050                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts      2638178862                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         655478683                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          543495866                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles       108887211                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles       11582877                       # Number of cycles decode is unblocking
+system.cpu.dcache.tagsinuse               4087.586245                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                667949970                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             5054603000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  3121989                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles      147560850                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred            636                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved      47355692                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts      2426461717                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles         611352233                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles          463432927                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles        80642265                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts           2276                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles       14321639                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -146,243 +158,243 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                   310557354                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 305363576                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     575148381                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               5854767                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                     2356063229                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles               488598                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                33050006                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.209378                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          305363576                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches          251301725                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.588462                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples         1435592687                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.884283                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.825499                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                   308386285                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                 291049356                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                     486495532                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes               5722216                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                     2234143439                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                  272                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                20492527                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.225575                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles          291049356                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches          252130567                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.634204                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples         1317309914                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.875583                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.855181                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                861509887     60.01%     60.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 76125416      5.30%     65.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 84428440      5.88%     71.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 62504000      4.35%     75.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 54555625      3.80%     79.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 66078288      4.60%     83.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 49716683      3.46%     87.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 19740436      1.38%     88.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                160933912     11.21%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                830814434     63.07%     63.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 33726973      2.56%     65.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 60219137      4.57%     70.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 62511674      4.75%     74.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 52124887      3.96%     78.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 58187439      4.42%     83.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 53878376      4.09%     87.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 20459280      1.55%     88.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                145387714     11.04%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1435592687                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        64                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       62                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses          305363576                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 34138.773389                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34223.489933                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              305362614                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       32841500                       # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total           1317309914                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        43                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       35                       # number of floating regfile writes
+system.cpu.icache.ReadReq_accesses          291049356                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 34505.208333                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34374.125874                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits              291048396                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       33125000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  962                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               217                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     25496500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses                  960                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               245                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency     24577500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000002                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             745                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses             715                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               409882.703356                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               407060.693706                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           305363576                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 34138.773389                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34223.489933                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               305362614                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        32841500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses           291049356                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 34505.208333                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34374.125874                       # average overall mshr miss latency
+system.cpu.icache.demand_hits               291048396                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        33125000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   962                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                217                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     25496500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses                   960                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                245                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency     24577500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000002                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              745                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses              715                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.297532                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            609.346021                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses          305363576                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 34138.773389                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34223.489933                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.282759                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            579.089793                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses          291049356                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 34505.208333                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34374.125874                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              305362614                       # number of overall hits
-system.cpu.icache.overall_miss_latency       32841500                       # number of overall miss cycles
+system.cpu.icache.overall_hits              291048396                       # number of overall hits
+system.cpu.icache.overall_miss_latency       33125000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  962                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               217                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     25496500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses                  960                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               245                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency     24577500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             745                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses             715                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                     10                       # number of replacements
-system.cpu.icache.sampled_refs                    745                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                      8                       # number of replacements
+system.cpu.icache.sampled_refs                    715                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                609.346021                       # Cycle average of tags in use
-system.cpu.icache.total_refs                305362614                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                579.089793                       # Cycle average of tags in use
+system.cpu.icache.total_refs                291048396                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                        47643035                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                234627924                       # Number of branches executed
-system.cpu.iew.EXEC:nop                       4671909                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.375387                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    783939674                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  215608294                       # Number of stores executed
+system.cpu.idleCycles                        49804391                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                234697761                       # Number of branches executed
+system.cpu.iew.EXEC:nop                           547                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.436470                       # Inst execution rate
+system.cpu.iew.EXEC:refs                    750034372                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                  187740498                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                2287060354                       # num instructions consuming a value
-system.cpu.iew.WB:count                    2005204740                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.549071                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                2269897341                       # num instructions consuming a value
+system.cpu.iew.WB:count                    1942898831                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.550573                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1255759101                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.351912                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     2013818862                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts             32077179                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                18912819                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             660681336                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                423                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts          10498008                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            320240164                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts          2431733440                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             568331380                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          53845340                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts            2040022874                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                1107254                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                1249744182                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.421168                       # insts written-back per cycle
+system.cpu.iew.WB:sent                     1949681228                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts             19483021                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                24433414                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             645564584                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts                589                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts           5964223                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts            233715447                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts          2284224586                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts             562293874                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          22044144                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts            1963818585                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                 950332                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 78756                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles              108887211                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles               1884872                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                 75248                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles               80642265                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles               2065851                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked       185254                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads        28251686                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses       475798                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked       185250                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads        50987012                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses       396924                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation      2910400                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads    174754505                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores    145393119                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents        2910400                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect     13800164                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       18277015                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads               5213407852                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1582208082                       # number of integer regfile writes
-system.cpu.ipc                               1.152486                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.152486                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation      2672523                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads            1                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads    159637800                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores     58868389                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents        2672523                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect      3281489                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect       16201532                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads               5066759971                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1546862528                       # number of integer regfile writes
+system.cpu.ipc                               1.260373                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.260373                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu      1275319810     60.91%     60.91% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult        1250756      0.06%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             2      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt           20      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            3      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc           17      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     60.97% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      577902067     27.60%     88.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     239395539     11.43%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu      1224165403     61.64%     61.64% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult        1261545      0.06%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd             2      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            6      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            1      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            7      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     61.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead      570988512     28.75%     90.46% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite     189447253      9.54%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       2093868214                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              35323579                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.016870                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total       1985862729                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt              19986735                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.010065                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             38144      0.11%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                1      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead         25553394     72.34%     72.45% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         9732040     27.55%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu            275137      1.38%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead         19210300     96.12%     97.49% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite          501298      2.51%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   1435592687                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.458539                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.617960                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples   1317309914                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.507514                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.580852                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     542472821     37.79%     37.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     332842678     23.19%     60.97% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     233352202     16.25%     77.23% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     155519573     10.83%     88.06% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      81101345      5.65%     93.71% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      48382072      3.37%     97.08% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6      32454212      2.26%     99.34% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       9020871      0.63%     99.97% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        446913      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0     464070867     35.23%     35.23% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1     308173295     23.39%     58.62% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2     229356697     17.41%     76.03% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3     153235086     11.63%     87.67% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4      89874952      6.82%     94.49% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5      46390462      3.52%     98.01% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6      16857883      1.28%     99.29% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7       8134010      0.62%     99.91% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8       1216662      0.09%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   1435592687                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.411689                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                      99                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                 193                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           76                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                250                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses             2129191694                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads         5686973961                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses   2005204664                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes        3140550876                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                 2427061108                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                2093868214                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                 423                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       710783267                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued          28321460                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved             90                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined   1287397497                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total   1317309914                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.452595                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      77                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                 148                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           51                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                110                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses             2005849387                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads         5310203358                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses   1942898780                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        2844721675                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                 2284223375                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                1985862729                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded                 664                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined       557961709                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued           1181399                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved            195                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined   1018791198                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -404,107 +416,107 @@ system.cpu.itb.read_misses                          0                       # DT
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses         1892135                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34468.560268                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31327.409096                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              979500                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  31457214500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.482331                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            912635                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  28590490000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.482331                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       912635                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           7656425                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34342.856557                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31123.713689                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               5633283                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   69480475500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.264241                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             2023142                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               11                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency  62967350000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.264240                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        2023131                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         3122334                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             3122334                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  3959.932754                       # average number of cycles each access was blocked
+system.cpu.l2cache.ReadExReq_accesses         1891872                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34461.042777                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.781802                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits              979846                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency  31429367000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.482076                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            912026                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  28570839500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.482076                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       912026                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses           7650944                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34297.265152                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31122.429712                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits               5630539                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   69294366000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.264073                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             2020405                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits                9                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency  62879632500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.264071                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        2020396                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         3121989                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             3121989                       # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  3894.751535                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.651251                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs             3569                       # number of cycles access was blocked
+system.cpu.l2cache.avg_refs                  2.653371                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs             3582                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs     14133000                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs     13951000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            9548560                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34381.933641                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31187.036024                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                6612783                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency   100937690000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.307458                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              2935777                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                11                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  91557840000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.307456                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         2935766                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_accesses            9542816                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34348.202225                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.986192                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                6610385                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency   100723733000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.307292                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              2932431                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                 9                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency  91450472000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.307291                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         2932422                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.492711                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.322099                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         16145.140731                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10554.551428                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses           9548560                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34381.933641                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31187.036024                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.491178                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.327642                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         16094.912992                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         10736.176193                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses           9542816                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34348.202225                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.986192                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               6612783                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency  100937690000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.307458                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             2935777                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               11                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  91557840000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.307456                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        2935766                       # number of overall MSHR misses
+system.cpu.l2cache.overall_hits               6610385                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency  100723733000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.307292                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             2932431                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits                9                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency  91450472000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.307291                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        2932422                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               2923336                       # number of replacements
-system.cpu.l2cache.sampled_refs               2950658                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               2920032                       # number of replacements
+system.cpu.l2cache.sampled_refs               2947354                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             26699.692159                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 7822936                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          156475358000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                 1217176                       # number of writebacks
-system.cpu.memDep0.conflictingLoads         104356221                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         93983481                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            660681336                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           320240164                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads              3120702507                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                    895                       # number of misc regfile writes
-system.cpu.numCycles                       1483235722                       # number of cpu cycles simulated
+system.cpu.l2cache.tagsinuse             26831.089185                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7820423                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          144225858000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                 1216371                       # number of writebacks
+system.cpu.memDep0.conflictingLoads         145182889                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        105876264                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            645564584                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           233715447                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads              2966427922                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                    896                       # number of misc regfile writes
+system.cpu.numCycles                       1367114305                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         54941029                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps     1347252520                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents        13387428                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         685531408                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents       44918840                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents          10136                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     7132306649                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      2561579932                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   1946061364                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          524157862                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles       108887211                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       62065425                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         598808841                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups          996                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   7132305653                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles         9752                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts          450                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts          114534338                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts          447                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                   3717462842                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4972618229                       # The number of ROB writes
-system.cpu.timesIdled                         1594989                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:BlockCycles         68709037                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps     1360917764                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents        18606012                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles         637141872                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents       55034011                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents          10097                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups     6548789867                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts      2371291968                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands   1861474045                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles          450935240                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles        80642265                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles       79866570                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps         500556278                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups          429                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups   6548789438                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles        14930                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts          647                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts          148781529                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts          642                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                   3470066777                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4649325132                       # The number of ROB writes
+system.cpu.timesIdled                         1578606                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index 8d90d74d0..17d22d770 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -66,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
index 1ce869a83..1571face8 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:58:23
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:10:25
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -29,4 +29,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 854705615000 because target called exit()
+Exiting @ tick 861538205000 because target called exit()
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index 8d3a8d25e..bb05b8971 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1030645                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 229520                       # Number of bytes of host memory used
-host_seconds                                  1658.58                       # Real time elapsed on the host
-host_tick_rate                              515323054                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1831754                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 246412                       # Number of bytes of host memory used
+host_seconds                                   940.67                       # Real time elapsed on the host
+host_tick_rate                              915878288                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1709408682                       # Number of instructions simulated
-sim_seconds                                  0.854706                       # Number of seconds simulated
-sim_ticks                                854705615000                       # Number of ticks simulated
+sim_insts                                  1723073862                       # Number of instructions simulated
+sim_seconds                                  0.861538                       # Number of seconds simulated
+sim_ticks                                861538205000                       # Number of ticks simulated
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -52,24 +52,24 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1709411231                       # number of cpu cycles simulated
+system.cpu.numCycles                       1723076411                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 1709411231                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                 1723076411                       # Number of busy cycles
+system.cpu.num_conditional_control_insts    177497944                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
 system.cpu.num_fp_insts                            36                       # number of float instructions
 system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    27330236                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                       1709408682                       # Number of instructions executed
-system.cpu.num_int_alu_accesses            1523276793                       # Number of integer alu accesses
-system.cpu.num_int_insts                   1523276793                       # number of integer instructions
-system.cpu.num_int_register_reads          4636623941                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1316065665                       # number of times the integer registers were written
-system.cpu.num_load_insts                   485926830                       # Number of load instructions
-system.cpu.num_mem_refs                     660773876                       # number of memory refs
+system.cpu.num_insts                       1723073862                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1536941850                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1536941850                       # number of integer instructions
+system.cpu.num_int_register_reads          4663954117                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1329730844                       # number of times the integer registers were written
+system.cpu.num_load_insts                   485926770                       # Number of load instructions
+system.cpu.num_mem_refs                     660773816                       # number of memory refs
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
 
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 3f9e59a85..8dc825ce6 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
@@ -166,7 +169,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
index ba8cd6dca..ffc182a84 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:25
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:27:01
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -29,4 +29,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2431420115000 because target called exit()
+Exiting @ tick 2431419954000 because target called exit()
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 923e9c734..f32aabd92 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,27 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 495941                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 237232                       # Number of bytes of host memory used
-host_seconds                                  3435.10                       # Real time elapsed on the host
-host_tick_rate                              707817123                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 781303                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 254132                       # Number of bytes of host memory used
+host_seconds                                  2197.96                       # Real time elapsed on the host
+host_tick_rate                             1106217790                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1703605163                       # Number of instructions simulated
+sim_insts                                  1717270343                       # Number of instructions simulated
 sim_seconds                                  2.431420                       # Number of seconds simulated
-sim_ticks                                2431420115000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses          482384248                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24514.094748                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.094748                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              475158152                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency   177141202000                       # number of ReadReq miss cycles
+sim_ticks                                2431419954000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits               61                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses          482384127                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 24514.084594                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.084594                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              475158040                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency   177140908000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.014980                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              7226096                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 155462914000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses              7226087                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 155462647000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.014980                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         7226096                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         172586108                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_mshr_misses         7226087                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses            61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits                61                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             170696959                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits             170696898                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency   63824222000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.010946                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses             1889149                       # number of WriteReq misses
@@ -30,49 +34,49 @@ system.cpu.dcache.WriteReq_mshr_miss_rate     0.010946                       # m
 system.cpu.dcache.WriteReq_mshr_misses        1889149                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  70.854389                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  70.854453                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           654970356                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 26435.430315                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23435.430315                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               645855111                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    240965424000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses           654970174                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 26435.424162                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               645854938                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency    240965130000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.013917                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               9115245                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses               9115236                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 213619689000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 213619422000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.013917                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          9115245                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses          9115236                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997003                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4083.724785                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          654970356                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 26435.430315                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23435.430315                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.997002                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4083.719979                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          654970174                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 26435.424162                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              645855111                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   240965424000                       # number of overall miss cycles
+system.cpu.dcache.overall_hits              645854938                       # number of overall hits
+system.cpu.dcache.overall_miss_latency   240965130000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.013917                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              9115245                       # number of overall misses
+system.cpu.dcache.overall_misses              9115236                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 213619689000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 213619422000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.013917                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         9115245                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses         9115236                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                9111149                       # number of replacements
-system.cpu.dcache.sampled_refs                9115245                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                9111140                       # number of replacements
+system.cpu.dcache.sampled_refs                9115236                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4083.724785                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                645855111                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            25922969000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  3061986                       # number of writebacks
+system.cpu.dcache.tagsinuse               4083.719979                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                645855060                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            25923025000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  3061985                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -94,10 +98,10 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses         1544565415                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses         1544565599                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 54551.724138                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits             1544564777                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits             1544564961                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       34804000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  638                       # number of ReadReq misses
@@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # ms
 system.cpu.icache.ReadReq_mshr_misses             638                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               2420947.926332                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               2420948.214734                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses          1544565415                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses          1544565599                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 54551.724138                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
-system.cpu.icache.demand_hits              1544564777                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits              1544564961                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        34804000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   638                       # number of demand (read+write) misses
@@ -127,12 +131,12 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.occ_%::0                   0.251403                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            514.872908                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses         1544565415                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0            514.872896                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses         1544565599                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 54551.724138                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits             1544564777                       # number of overall hits
+system.cpu.icache.overall_hits             1544564961                       # number of overall hits
 system.cpu.icache.overall_miss_latency       34804000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  638                       # number of overall misses
@@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                      7                       # number of replacements
 system.cpu.icache.sampled_refs                    638                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                514.872908                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1544564777                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                514.872896                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1544564961                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses            889908                       # nu
 system.cpu.l2cache.ReadExReq_mshr_miss_latency  35596320000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.471063                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses       889908                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           7226734                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses           7226725                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               5417169                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   94097380000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.250399                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1809565                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  72382600000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250399                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1809565                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         3061986                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             3061986                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits               5417164                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   94097172000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.250398                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1809561                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  72382440000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250398                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1809561                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         3061985                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             3061985                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.788539                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.788542                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            9115883                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses            9115874                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                6416410                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency   140372596000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.296129                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              2699473                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                6416405                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency   140372388000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.296128                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              2699469                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 107978920000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.296129                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         2699473                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 107978760000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.296128                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         2699469                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.458608                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.338955                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         15027.674424                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         11106.876723                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses           9115883                       # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::0                  0.458607                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.338956                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         15027.621217                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         11106.896016                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses           9115874                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               6416410                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency  140372596000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.296129                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             2699473                       # number of overall misses
+system.cpu.l2cache.overall_hits               6416405                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency  140372388000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.296128                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             2699469                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 107978920000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.296129                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        2699473                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 107978760000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.296128                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        2699469                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               2687070                       # number of replacements
-system.cpu.l2cache.sampled_refs               2714388                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               2687066                       # number of replacements
+system.cpu.l2cache.sampled_refs               2714383                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             26134.551147                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 7569176                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          538044067000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                 1171981                       # number of writebacks
+system.cpu.l2cache.tagsinuse             26134.517233                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7569171                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          538044123000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                 1171980                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       4862840230                       # number of cpu cycles simulated
+system.cpu.numCycles                       4862839908                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 4862840230                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                 4862839908                       # Number of busy cycles
+system.cpu.num_conditional_control_insts    177497944                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
 system.cpu.num_fp_insts                            36                       # number of float instructions
 system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    27330236                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                       1703605163                       # Number of instructions executed
-system.cpu.num_int_alu_accesses            1523276793                       # Number of integer alu accesses
-system.cpu.num_int_insts                   1523276793                       # number of integer instructions
-system.cpu.num_int_register_reads          5115465619                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1316065727                       # number of times the integer registers were written
-system.cpu.num_load_insts                   485926830                       # Number of load instructions
-system.cpu.num_mem_refs                     660773876                       # number of memory refs
+system.cpu.num_insts                       1717270343                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1536941850                       # Number of integer alu accesses
+system.cpu.num_int_insts                   1536941850                       # number of integer instructions
+system.cpu.num_int_register_reads          5142795796                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1329730906                       # number of times the integer registers were written
+system.cpu.num_load_insts                   485926770                       # Number of load instructions
+system.cpu.num_mem_refs                     660773816                       # number of memory refs
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
 
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
index f95eb4d89..4743a86c6 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -115,6 +115,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -413,6 +414,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -448,6 +450,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -493,7 +496,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
index a363bde41..0bb69c5ff 100755
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 21 2011 14:34:16
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 15:12:03
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:28:39
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -28,4 +26,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 149819214000 because target called exit()
+122 123 124 Exiting @ tick 129013619500 because target called exit()
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 28cd85165..9ba32bb5a 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,130 +1,142 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  52926                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 260544                       # Number of bytes of host memory used
-host_seconds                                  3491.51                       # Real time elapsed on the host
-host_tick_rate                               42909528                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  73857                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 259036                       # Number of bytes of host memory used
+host_seconds                                  2527.09                       # Real time elapsed on the host
+host_tick_rate                               51052260                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   184792363                       # Number of instructions simulated
-sim_seconds                                  0.149819                       # Number of seconds simulated
-sim_ticks                                149819214000                       # Number of ticks simulated
+sim_insts                                   186644197                       # Number of instructions simulated
+sim_seconds                                  0.129014                       # Number of seconds simulated
+sim_ticks                                129013619500                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 51777441                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              55728820                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           12604932                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           57019635                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 57019635                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               39499925                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events            586569                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                 82595843                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              87704416                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect               35994                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect            9565909                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           85970608                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                110694771                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  4976778                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches               39816389                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events           1145946                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    285162046                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.648076                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     0.934649                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples    230008327                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.811530                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.187276                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    151201890     53.02%     53.02% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    102481075     35.94%     88.96% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     22788718      7.99%     96.95% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      3864443      1.36%     98.31% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      2118451      0.74%     99.05% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      1126210      0.39%     99.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       605325      0.21%     99.66% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       389365      0.14%     99.79% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8       586569      0.21%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0    121269072     52.72%     52.72% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1     61996527     26.95%     79.68% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2     32262930     14.03%     93.70% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3      7261751      3.16%     96.86% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4      3043345      1.32%     98.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5      1671954      0.73%     98.91% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6       847387      0.37%     99.28% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7       509415      0.22%     99.50% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8      1145946      0.50%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    285162046                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 184806751                       # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total    230008327                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                 186658585                       # Number of instructions committed
 system.cpu.commit.COM:fp_insts                1730659                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             146860811                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  29554611                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   42081439                       # Number of memory references committed
+system.cpu.commit.COM:function_calls          1835949                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts             148665286                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                  29539429                       # Number of loads committed
+system.cpu.commit.COM:membars                   22408                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                   42068801                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts          12955566                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts      184806751                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls         1569953                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        36913868                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                   184792363                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             184792363                       # Number of Instructions Simulated
-system.cpu.cpi                               1.621487                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.621487                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses           32436973                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 31572.057898                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32361.072902                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               32435384                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       50168000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000049                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                 1589                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits               862                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency     23526500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000022                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             727                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          12273971                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 25388.039035                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35046.660567                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              12266388                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     192517500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000618                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                7583                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits             6490                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency     38306000                       # number of WriteReq MSHR miss cycles
+system.cpu.commit.branchMispredicts           9469517                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts      186658585                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls         1617312                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts       187111758                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                   186644197                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             186644197                       # Number of Instructions Simulated
+system.cpu.cpi                               1.382455                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.382455                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses        26640                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        32000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits            26638                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency        64000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000075                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.ReadReq_accesses           36653125                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 33700.747283                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32158.536585                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               36651653                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency       49607500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.000040                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                 1472                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits               734                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency     23733000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000020                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses             738                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses         24951                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits             24951                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses          12251566                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 31103.241534                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35107.404022                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              12243977                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency     236042500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000619                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                7589                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits             6495                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency     38407500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1093                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1094                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets         9000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               24561.413187                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs               26717.914301                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         9000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            44710944                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 26459.387266                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33973.901099                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                44701772                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       242685500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000205                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  9172                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits               7352                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency     61832500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000041                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             1820                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses            48904691                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 31525.217967                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33919.486900                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                48895630                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       285650000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.000185                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                  9061                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits               7229                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency     62140500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.000037                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses             1832                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.337576                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           1382.712770                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses           44710944                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 26459.387266                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33973.901099                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.340757                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           1395.741753                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses           48904691                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 31525.217967                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33919.486900                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               44701772                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      242685500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000205                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 9172                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits              7352                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency     61832500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000041                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            1820                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits               48895630                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      285650000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.000185                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                 9061                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits              7229                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency     62140500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.000037                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses            1832                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                     46                       # number of replacements
-system.cpu.dcache.sampled_refs                   1820                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                     44                       # number of replacements
+system.cpu.dcache.sampled_refs                   1832                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1382.712770                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 44701772                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1395.741753                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 48947219                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                       17                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       21645694                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts       264148336                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          61114397                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          200863123                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        14403927                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles        1538831                       # Number of cycles decode is unblocking
+system.cpu.dcache.writebacks                       16                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       41216121                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred         162173                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved      17947429                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts       450164827                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          82659496                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles          104979793                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles        27951688                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts         694943                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        1152916                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -146,243 +158,243 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                    57019635                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  24416320                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     213842486                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               1112165                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      254182972                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                47096                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                13195878                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.190295                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           24416320                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           51777441                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.848299                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          299565972                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.927730                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.045167                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                   110694771                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                  38575932                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                     111755859                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes               1956934                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                      439020162                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                55086                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                 9825072                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.429004                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles           38575932                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches           87572621                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.701449                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples          257960014                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.834639                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.572532                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 86216390     28.78%     28.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                186583671     62.28%     91.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 11093729      3.70%     94.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  7887786      2.63%     97.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1768857      0.59%     97.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2263080      0.76%     98.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1007503      0.34%     99.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   913678      0.31%     99.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  1831278      0.61%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                146405140     56.75%     56.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4345583      1.68%     58.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 33012115     12.80%     71.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 15727198      6.10%     77.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  9968006      3.86%     81.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 16602538      6.44%     87.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  8446634      3.27%     90.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  5474811      2.12%     93.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 17977989      6.97%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            299565972                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                   2799107                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2446180                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses           24416320                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 25130.564219                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21980.432060                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               24412793                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       88635500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000144                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 3527                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               333                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     70205500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000131                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses            3194                       # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total            257960014                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                   2918455                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2533041                       # number of floating regfile writes
+system.cpu.icache.ReadReq_accesses           38575932                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 23829.127878                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 20456.359460                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               38571850                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       97270500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000106                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                 4082                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               599                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency     71249500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000090                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses            3483                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                7643.329054                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               11074.318117                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            24416320                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 25130.564219                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21980.432060                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                24412793                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        88635500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000144                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  3527                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                333                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     70205500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000131                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses             3194                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses            38575932                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 23829.127878                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 20456.359460                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                38571850                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        97270500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000106                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                  4082                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                599                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency     71249500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000090                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses             3483                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.617996                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1265.656561                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses           24416320                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 25130.564219                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 21980.432060                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.621830                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1273.508184                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses           38575932                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 23829.127878                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 20456.359460                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               24412793                       # number of overall hits
-system.cpu.icache.overall_miss_latency       88635500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000144                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 3527                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               333                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     70205500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000131                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses            3194                       # number of overall MSHR misses
+system.cpu.icache.overall_hits               38571850                       # number of overall hits
+system.cpu.icache.overall_miss_latency       97270500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000106                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                 4082                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               599                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency     71249500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000090                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses            3483                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                   1539                       # number of replacements
-system.cpu.icache.sampled_refs                   3194                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                   1827                       # number of replacements
+system.cpu.icache.sampled_refs                   3483                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1265.656561                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 24412793                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1273.508184                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 38571850                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                           72457                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 40333139                       # Number of branches executed
-system.cpu.iew.EXEC:nop                        106308                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.675299                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     46706723                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   12922741                       # Number of stores executed
+system.cpu.idleCycles                           67226                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                 52962106                       # Number of branches executed
+system.cpu.iew.EXEC:nop                         84051                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     0.929014                       # Inst execution rate
+system.cpu.iew.EXEC:refs                     51175949                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                   13319638                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 166977314                       # num instructions consuming a value
-system.cpu.iew.WB:count                     199432136                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.694920                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                 285530591                       # num instructions consuming a value
+system.cpu.iew.WB:count                     236209276                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.493714                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 116035928                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.665576                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      200401741                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts             13076652                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                    1256                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              37075609                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            1668755                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts          11833619                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             14988549                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           221729626                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              33783982                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10729958                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             202345530                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                      7                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                 140970333                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.915443                       # insts written-back per cycle
+system.cpu.iew.WB:sent                      237475950                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts             10889279                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                   87073                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts              51734063                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts            2217181                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts           4617225                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts             19417784                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts           373778120                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              37856311                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7515922                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             239710842                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                  16182                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               14403927                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                   103                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                 11289                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles               27951688                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                 27726                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked            1                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads          638748                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses         2434                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads          619448                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses         1421                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation       295230                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads      7520997                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores      2461721                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         295230                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      1407484                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       11669168                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                457778046                       # number of integer regfile reads
-system.cpu.int_regfile_writes               195349960                       # number of integer regfile writes
-system.cpu.ipc                               0.616718                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.616718                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation       246556                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads           13                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads     22194633                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores      6888412                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents         246556                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect      2322193                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect        8567086                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                532811061                       # number of integer regfile reads
+system.cpu.int_regfile_writes               228488130                       # number of integer regfile writes
+system.cpu.ipc                               0.723351                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.723351                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       163185983     76.59%     76.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult         907348      0.43%     77.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     77.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     77.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     77.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     77.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     77.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     77.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     77.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd          16007      0.01%     77.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     77.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     77.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     77.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     77.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     77.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     77.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     77.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     77.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     77.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     77.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd        33154      0.02%     77.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     77.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp       157340      0.07%     77.11% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt       265597      0.12%     77.23% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv        74720      0.04%     77.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc       439795      0.21%     77.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult       197622      0.09%     77.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc        71713      0.03%     77.60% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt          318      0.00%     77.60% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       34601052     16.24%     93.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      13124839      6.16%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu       192005801     77.66%     77.66% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult         909911      0.37%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd           7519      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     78.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd        33371      0.01%     78.05% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     78.05% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp       158227      0.06%     78.11% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt       303942      0.12%     78.24% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv        75061      0.03%     78.27% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc       513450      0.21%     78.47% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult       198615      0.08%     78.55% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc        72348      0.03%     78.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt          326      0.00%     78.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead       39354306     15.92%     94.50% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite      13593887      5.50%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        213075488                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               1172568                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.005503                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total        247226764                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt               1255415                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.005078                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu                 3      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead           789273     67.31%     67.31% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          383292     32.69%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu             17638      1.40%      1.40% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult             5653      0.45%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      1.86% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead          1032005     82.20%     84.06% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite          200119     15.94%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    299565972                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.711281                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     0.810682                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples    257960014                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.958392                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.149844                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     130442943     43.54%     43.54% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     140707808     46.97%     90.51% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      18780101      6.27%     96.78% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       5513171      1.84%     98.62% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       2752255      0.92%     99.54% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       1032616      0.34%     99.89% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6        286376      0.10%     99.98% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7         28007      0.01%     99.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8         22695      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0     118566541     45.96%     45.96% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      70125037     27.18%     73.15% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2      44762596     17.35%     90.50% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3      14438137      5.60%     96.10% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4       6886623      2.67%     98.77% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5       2484508      0.96%     99.73% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6        597059      0.23%     99.96% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7         85366      0.03%     99.99% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8         14147      0.01%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    299565972                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.711109                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                 1965612                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads             3923910                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1824312                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes            2255873                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses              212282444                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          723212864                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    197607824                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         240197118                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  219954563                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 213075488                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             1668755                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        20589653                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            247258                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved          98802                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined     37700924                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total    257960014                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     0.958142                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                 1985429                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads             3952184                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1885790                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes            3082571                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses              246496750                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          750098950                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses    234323486                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes         555603223                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                  371452773                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                 247226764                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded             2241296                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined       184786827                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued            382177                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved         623984                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined    306361873                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -404,106 +416,106 @@ system.cpu.itb.read_misses                          0                       # DT
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses            1093                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.133641                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31130.875576                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_accesses            1094                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34292.357274                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31035.911602                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_hits                   8                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency     37175500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.992681                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              1085                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     33777000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.992681                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         1085                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses              3921                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34264.419330                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.500393                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                  1355                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      87922500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.654425                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                2566                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               20                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency     79133500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.649324                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           2546                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses              17                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                  17                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_miss_latency     37241500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.992687                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses              1086                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     33705000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.992687                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses         1086                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses              4221                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34284.967067                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31071.317225                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                  1640                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency      88489500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.611466                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                2581                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits               15                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency     79729000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.607913                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses           2566                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses              16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits                  16                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.530333                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.637141                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses               5014                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34264.037250                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31096.254475                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   1363                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      125098000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.728161                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 3651                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                20                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    112910500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.724172                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            3631                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_accesses               5315                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34287.155713                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31060.788609                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                   1648                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      125731000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.689934                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 3667                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                15                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency    113434000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.687112                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            3652                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.055506                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000152                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          1818.805056                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             4.996217                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses              5014                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34264.037250                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31096.254475                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.056054                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.000092                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1836.784505                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             3.029906                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses              5315                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34287.155713                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31060.788609                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  1363                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     125098000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.728161                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                3651                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               20                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    112910500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.724172                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           3631                       # number of overall MSHR misses
+system.cpu.l2cache.overall_hits                  1648                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     125731000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.689934                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                3667                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits               15                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency    113434000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.687112                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           3652                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  2555                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  2574                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              1823.801274                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    1355                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              1839.814411                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1640                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.memDep0.conflictingLoads           3889323                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2640936                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             37075609                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            14988549                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               328971277                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                4891827                       # number of misc regfile writes
-system.cpu.numCycles                        299638429                       # number of cpu cycles simulated
+system.cpu.memDep0.conflictingLoads          20836418                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         10554028                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             51734063                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            19417784                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads               525439504                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                4891826                       # number of misc regfile writes
+system.cpu.numCycles                        258027240                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles             3074                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      178683528                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents            2322                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          73277569                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents          19202                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups      601039980                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       249997488                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    249829289                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          190277920                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        14403927                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        1750037                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          71145759                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups     14827185                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    586212795                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles     19853445                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts      2086015                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts            2928694                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts      1863087                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    506290895                       # The number of ROB reads
-system.cpu.rob.rob_writes                   457856720                       # The number of ROB writes
-system.cpu.timesIdled                            1374                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:BlockCycles          2330030                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps      180535361                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents          944198                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          91504327                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        3682942                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups      971479303                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts       419602585                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands    423243474                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           97150161                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles        27951688                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles        7290618                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps         242708110                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups     16446952                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups    955032351                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles     31733190                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts      2646445                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           27810547                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts      2436395                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    602627523                       # The number of ROB reads
+system.cpu.rob.rob_writes                   775494029                       # The number of ROB writes
+system.cpu.timesIdled                            1399                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 283406dc2..b4f12af94 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -66,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
index c50fadfb0..46b5d4995 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:35
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 21:03:59
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
-Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav
-Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -28,4 +26,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 102180734000 because target called exit()
+122 123 124 Exiting @ tick 103106771000 because target called exit()
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 4a204d0cd..a560430fc 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1012006                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 232796                       # Number of bytes of host memory used
-host_seconds                                   184.60                       # Real time elapsed on the host
-host_tick_rate                              553516772                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1749088                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 249684                       # Number of bytes of host memory used
+host_seconds                                   107.87                       # Real time elapsed on the host
+host_tick_rate                              955856938                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   186818826                       # Number of instructions simulated
-sim_seconds                                  0.102181                       # Number of seconds simulated
-sim_ticks                                102180734000                       # Number of ticks simulated
+sim_insts                                   188670900                       # Number of instructions simulated
+sim_seconds                                  0.103107                       # Number of seconds simulated
+sim_ticks                                103106771000                       # Number of ticks simulated
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -52,24 +52,24 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        204361469                       # number of cpu cycles simulated
+system.cpu.numCycles                        206213543                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  204361469                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                  206213543                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     31909249                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
 system.cpu.num_fp_insts                       1752310                       # number of float instructions
 system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     3663001                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        186818826                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             148453796                       # Number of integer alu accesses
-system.cpu.num_int_insts                    148453796                       # number of integer instructions
-system.cpu.num_int_register_reads           440904784                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          179338779                       # number of times the integer registers were written
-system.cpu.num_load_insts                    29867211                       # Number of load instructions
-system.cpu.num_mem_refs                      42511846                       # number of memory refs
+system.cpu.num_insts                        188670900                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             150261055                       # Number of integer alu accesses
+system.cpu.num_int_insts                    150261055                       # number of integer instructions
+system.cpu.num_int_register_reads           444541710                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          181190852                       # number of times the integer registers were written
+system.cpu.num_load_insts                    29849485                       # Number of load instructions
+system.cpu.num_mem_refs                      42494120                       # number of memory refs
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
 
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
index d150b1761..21861df0c 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
@@ -166,7 +169,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
index 5cb7e11c7..40c466e50 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:24
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 21:02:08
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
-Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -28,4 +26,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 232027671000 because target called exit()
+122 123 124 Exiting @ tick 232077154000 because target called exit()
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 715b30669..630ae5fa6 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,27 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 504285                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 240500                       # Number of bytes of host memory used
-host_seconds                                   369.50                       # Real time elapsed on the host
-host_tick_rate                              627947562                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 793653                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 257372                       # Number of bytes of host memory used
+host_seconds                                   237.11                       # Real time elapsed on the host
+host_tick_rate                              978757790                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   186333855                       # Number of instructions simulated
-sim_seconds                                  0.232028                       # Number of seconds simulated
-sim_ticks                                232027671000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses           29640180                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 52469.565217                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49469.565217                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               29639490                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       36204000                       # number of ReadReq miss cycles
+sim_insts                                   188185929                       # Number of instructions simulated
+sim_seconds                                  0.232077                       # Number of seconds simulated
+sim_ticks                                232077154000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits            22407                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses           29600047                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 52525.399129                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49525.399129                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               29599358                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency       36190000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000023                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  690                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     34134000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses                  689                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     34123000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000023                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             690                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          12386694                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_mshr_misses             689                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses         22407                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits             22407                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              12385594                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits              12363187                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency      61264000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000089                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                1100                       # number of WriteReq misses
@@ -30,47 +34,47 @@ system.cpu.dcache.WriteReq_mshr_miss_rate     0.000089                       # m
 system.cpu.dcache.WriteReq_mshr_misses           1100                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               23477.700559                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               23480.916154                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            42026874                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54451.396648                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51451.396648                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                42025084                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency        97468000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses            41964334                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 54474.007826                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                41962545                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency        97454000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000043                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  1790                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses                  1789                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency     92098000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     92087000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000043                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             1790                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             1789                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.333155                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           1364.601667                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses           42026874                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54451.396648                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51451.396648                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.332911                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           1363.604315                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses           41964334                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 54474.007826                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               42025084                       # number of overall hits
-system.cpu.dcache.overall_miss_latency       97468000                       # number of overall miss cycles
+system.cpu.dcache.overall_hits               41962545                       # number of overall hits
+system.cpu.dcache.overall_miss_latency       97454000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000043                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 1790                       # number of overall misses
+system.cpu.dcache.overall_misses                 1789                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency     92098000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     92087000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000043                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            1790                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            1789                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                     40                       # number of replacements
-system.cpu.dcache.sampled_refs                   1790                       # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1789                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1364.601667                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 42025084                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1363.604315                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 42007359                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                       16                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
@@ -94,10 +98,10 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses          189792839                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses          189860061                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 37801.376598                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              189789788                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits              189857010                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency      115332000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000016                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                 3051                       # number of ReadReq misses
@@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000016                       # ms
 system.cpu.icache.ReadReq_mshr_misses            3051                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               62205.764667                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               62227.797443                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           189792839                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses           189860061                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 37801.376598                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               189789788                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits               189857010                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency       115332000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000016                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                  3051                       # number of demand (read+write) misses
@@ -126,13 +130,13 @@ system.cpu.icache.demand_mshr_misses             3051                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.560536                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1147.977892                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses          189792839                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.560538                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1147.981155                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses          189860061                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 37801.376598                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              189789788                       # number of overall hits
+system.cpu.icache.overall_hits              189857010                       # number of overall hits
 system.cpu.icache.overall_miss_latency      115332000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000016                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                 3051                       # number of overall misses
@@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   1506                       # number of replacements
 system.cpu.icache.sampled_refs                   3051                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1147.977892                       # Cycle average of tags in use
-system.cpu.icache.total_refs                189789788                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1147.981155                       # Cycle average of tags in use
+system.cpu.icache.total_refs                189857010                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses              1092                       # nu
 system.cpu.l2cache.ReadExReq_mshr_miss_latency     43680000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.992727                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses         1092                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses              3741                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses              3740                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                  1380                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits                  1379                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_miss_latency     122772000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.631115                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.631283                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                2361                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency     94440000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.631115                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.631283                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           2361                       # number of ReadReq MSHR misses
 system.cpu.l2cache.Writeback_accesses              16                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_hits                  16                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.582524                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.582102                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses               4841                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses               4840                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   1388                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits                   1387                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_miss_latency      179556000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.713282                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate          0.713430                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                 3453                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_miss_latency    138120000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.713282                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.713430                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses            3453                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.occ_%::0                  0.051044                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_%::1                  0.000093                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          1672.604511                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             3.037968                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses              4841                       # number of overall (read+write) accesses
+system.cpu.l2cache.occ_blocks::0          1672.609981                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             3.038048                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses              4840                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  1388                       # number of overall hits
+system.cpu.l2cache.overall_hits                  1387                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency     179556000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.713282                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate         0.713430                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                3453                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_miss_latency    138120000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.713282                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.713430                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses           3453                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                  2369                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              1675.642479                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    1380                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              1675.648030                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1379                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        464055342                       # number of cpu cycles simulated
+system.cpu.numCycles                        464154308                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                  464055342                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                  464154308                       # Number of busy cycles
+system.cpu.num_conditional_control_insts     31909249                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
 system.cpu.num_fp_insts                       1752310                       # number of float instructions
 system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     3663001                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                        186333855                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             148453796                       # Number of integer alu accesses
-system.cpu.num_int_insts                    148453796                       # number of integer instructions
-system.cpu.num_int_register_reads           470866018                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          179570637                       # number of times the integer registers were written
-system.cpu.num_load_insts                    29867211                       # Number of load instructions
-system.cpu.num_mem_refs                      42511846                       # number of memory refs
+system.cpu.num_insts                        188185929                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             150261055                       # Number of integer alu accesses
+system.cpu.num_int_insts                    150261055                       # number of integer instructions
+system.cpu.num_int_register_reads           474507625                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          181422710                       # number of times the integer registers were written
+system.cpu.num_load_insts                    29849485                       # Number of load instructions
+system.cpu.num_mem_refs                      42494120                       # number of memory refs
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
index 8bf9c7da1..6bf13d8ce 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -115,6 +115,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -413,6 +414,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -448,6 +450,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
index 1af21cc60..769c3535d 100755
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 23 2011 14:37:21
-M5 revision bc7f8168ee84 7973 default ext/update_regressions.patch qtip tip
-M5 started Feb 23 2011 14:37:24
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:10:13
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 10283500 because target called exit()
+Exiting @ tick 10855000 because target called exit()
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
index b4704e4ff..8fe241344 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,130 +1,142 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                   6235                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 252896                       # Number of bytes of host memory used
-host_seconds                                     0.90                       # Real time elapsed on the host
-host_tick_rate                               11404126                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   4296                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 251256                       # Number of bytes of host memory used
+host_seconds                                     1.34                       # Real time elapsed on the host
+host_tick_rate                                8125103                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        5620                       # Number of instructions simulated
-sim_seconds                                  0.000010                       # Number of seconds simulated
-sim_ticks                                    10283500                       # Number of ticks simulated
+sim_insts                                        5739                       # Number of instructions simulated
+sim_seconds                                  0.000011                       # Number of seconds simulated
+sim_ticks                                    10855000                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                      790                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups                  2145                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect                348                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted               2190                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                     2190                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                    840                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events                69                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                      646                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups                  1753                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                  59                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect                388                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted               1655                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                     2162                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                      243                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches                    927                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events                59                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples        10507                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.534882                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.283154                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples        11145                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.514939                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.233206                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0         8067     76.78%     76.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1         1134     10.79%     87.57% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2          524      4.99%     92.56% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3          313      2.98%     95.54% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4          174      1.66%     97.19% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5          143      1.36%     98.55% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6           45      0.43%     98.98% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7           38      0.36%     99.34% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8           69      0.66%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0         8562     76.82%     76.82% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1         1244     11.16%     87.99% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2          554      4.97%     92.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3          326      2.93%     95.88% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4          181      1.62%     97.51% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5          133      1.19%     98.70% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6           54      0.48%     99.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7           32      0.29%     99.47% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8           59      0.53%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total        10507                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                      5620                       # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total        11145                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                      5739                       # Number of instructions committed
 system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  4889                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                      1207                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                       2145                       # Number of memory references committed
+system.cpu.commit.COM:function_calls               82                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts                  4985                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                      1201                       # Number of loads committed
+system.cpu.commit.COM:membars                      12                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                       2139                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts               526                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts           5620                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls               1                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts            6008                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                        5620                       # Number of Instructions Simulated
-system.cpu.committedInsts_total                  5620                       # Number of Instructions Simulated
-system.cpu.cpi                               3.659786                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.659786                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses               1812                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 31853.260870                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 29433.628319                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits                   1628                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        5861000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.101545                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  184                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits                71                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency      3326000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.062362                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             113                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses               924                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35561.461794                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36109.756098                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits                   623                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      10704000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.325758                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                 301                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits              260                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency      1480500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.044372                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses             41                       # number of WriteReq MSHR misses
+system.cpu.commit.branchMispredicts               318                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts           5739                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls              24                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts            4681                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                        5739                       # Number of Instructions Simulated
+system.cpu.committedInsts_total                  5739                       # Number of Instructions Simulated
+system.cpu.cpi                               3.783063                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.783063                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        38250                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits                9                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency        76500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.181818                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.ReadReq_accesses               1862                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 32845.679012                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 29990.825688                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits                   1700                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency        5321000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.087003                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                  162                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits                53                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency      3269000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.058539                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses             109                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses            11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits                11                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses               913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 35254.295533                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35797.619048                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits                   622                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency      10259000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.318729                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                 291                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits              249                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency      1503500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.046002                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses             42                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  14.616883                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  15.509934                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses                2736                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 34154.639175                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 31211.038961                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    2251                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency        16565000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.177266                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                   485                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                331                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      4806500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.056287                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses              154                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses                2775                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 34392.935982                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 31605.960265                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                    2322                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency        15580000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.163243                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                   453                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits                302                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency      4772500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.054414                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses              151                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.022805                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0             93.407309                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses               2736                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 34154.639175                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 31211.038961                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.022190                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0             90.890102                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses               2775                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 34392.935982                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 31605.960265                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   2251                       # number of overall hits
-system.cpu.dcache.overall_miss_latency       16565000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.177266                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                  485                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits               331                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      4806500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.056287                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses             154                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits                   2322                       # number of overall hits
+system.cpu.dcache.overall_miss_latency       15580000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.163243                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                  453                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits               302                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency      4772500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.054414                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses             151                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.sampled_refs                    154                       # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs                    151                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 93.407309                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2251                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 90.890102                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2342                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles            735                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts           14966                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles              7256                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles               2466                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles            1138                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles             49                       # Number of cycles decode is unblocking
+system.cpu.decode.DECODE:BlockedCycles           1262                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred            156                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved           341                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts           12417                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles              7526                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles               2297                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles             804                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts            556                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles             59                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -146,242 +158,242 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                        2190                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                      1676                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                          2616                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                   324                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                          12629                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                   22                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                     562                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.106476                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles               1676                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches                790                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.614012                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples              11644                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.344040                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.759565                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                        2162                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                      1609                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                          2418                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                   235                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                          11261                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                   34                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                     506                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.099581                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles               1609                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches                889                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        0.518677                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples              11948                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.172497                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.587798                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9028     77.53%     77.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      206      1.77%     79.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      151      1.30%     80.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      211      1.81%     82.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      193      1.66%     84.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      242      2.08%     86.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      137      1.18%     87.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      103      0.88%     88.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1373     11.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9530     79.76%     79.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      215      1.80%     81.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      150      1.26%     82.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      199      1.67%     84.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      194      1.62%     86.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      272      2.28%     88.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      117      0.98%     89.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      109      0.91%     90.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1162      9.73%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                11644                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total                11948                       # Number of instructions fetched each cycle (Total)
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses               1676                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 34634.271100                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 33596.573209                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits                   1285                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       13542000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.233294                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  391                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits                70                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     10784500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.191527                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             321                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses               1609                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 34710.914454                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 33335.069444                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits                   1270                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       11767000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.210690                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                  339                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits                51                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency      9600500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.178993                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses             288                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                   4.003115                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   4.409722                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses                1676                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 34634.271100                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 33596.573209                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                    1285                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        13542000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.233294                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   391                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                 70                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     10784500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.191527                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              321                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses                1609                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 34710.914454                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 33335.069444                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                    1270                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        11767000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.210690                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                   339                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                 51                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency      9600500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.178993                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses              288                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.079640                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            163.103725                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses               1676                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 34634.271100                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 33596.573209                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.071695                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            146.831980                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses               1609                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 34710.914454                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 33335.069444                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                   1285                       # number of overall hits
-system.cpu.icache.overall_miss_latency       13542000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.233294                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  391                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                70                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     10784500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.191527                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             321                       # number of overall MSHR misses
+system.cpu.icache.overall_hits                   1270                       # number of overall hits
+system.cpu.icache.overall_miss_latency       11767000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.210690                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                  339                       # number of overall misses
+system.cpu.icache.overall_mshr_hits                51                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency      9600500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.178993                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses             288                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                      5                       # number of replacements
-system.cpu.icache.sampled_refs                    321                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                      2                       # number of replacements
+system.cpu.icache.sampled_refs                    288                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                163.103725                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1285                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                146.831980                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1270                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                            8924                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                     1306                       # Number of branches executed
-system.cpu.iew.EXEC:nop                            20                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.417493                       # Inst execution rate
-system.cpu.iew.EXEC:refs                         3129                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                       1169                       # Number of stores executed
+system.cpu.idleCycles                            9763                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                     1290                       # Number of branches executed
+system.cpu.iew.EXEC:nop                            18                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     0.381972                       # Inst execution rate
+system.cpu.iew.EXEC:refs                         3149                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                       1151                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                      7925                       # num instructions consuming a value
-system.cpu.iew.WB:count                          7989                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.467886                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                      7351                       # num instructions consuming a value
+system.cpu.iew.WB:count                          7821                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.493674                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                      3708                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.388419                       # insts written-back per cycle
-system.cpu.iew.WB:sent                           8268                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts                  620                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                     230                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts                  2545                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                  2                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts               596                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts                 1654                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts               11895                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts                  1960                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               474                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts                  8587                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                     20                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                      3629                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.360232                       # insts written-back per cycle
+system.cpu.iew.WB:sent                           8026                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts                  368                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                     195                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts                  2420                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts                 13                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts               106                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts                 1527                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts               10583                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts                  1998                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               333                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts                  8293                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                   1138                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                    28                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles                    804                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                    15                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads              59                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads              51                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation           34                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads            2                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads         1338                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores          716                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents             34                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect          587                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect             33                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                    19241                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    5711                       # number of integer regfile writes
-system.cpu.ipc                               0.273240                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.273240                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation           30                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads         1219                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores          589                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents             30                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect          273                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect             95                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                    18798                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    5617                       # number of integer regfile writes
+system.cpu.ipc                               0.264336                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.264336                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu            5694     62.84%     62.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              5      0.06%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     62.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            3      0.03%     62.93% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     62.93% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     62.93% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     62.93% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead           2133     23.54%     86.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite          1226     13.53%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu            5295     61.38%     61.38% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult              6      0.07%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     61.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            3      0.03%     61.49% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     61.49% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     61.49% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     61.49% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead           2134     24.74%     86.23% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite          1188     13.77%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total             9061                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                   181                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.019976                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total             8626                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt                   186                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.021563                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu                 4      2.21%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      2.21% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead              109     60.22%     62.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite              68     37.57%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu                 6      3.23%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      3.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead              120     64.52%     67.74% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite              60     32.26%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples        11644                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.778169                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.459347                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples        11948                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.721962                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.365135                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0          8032     68.98%     68.98% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1          1346     11.56%     80.54% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2           757      6.50%     87.04% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3           566      4.86%     91.90% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4           475      4.08%     95.98% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5           283      2.43%     98.41% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6           122      1.05%     99.46% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7            48      0.41%     99.87% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8            15      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0          8312     69.57%     69.57% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1          1403     11.74%     81.31% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2           852      7.13%     88.44% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3           582      4.87%     93.31% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4           409      3.42%     96.74% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5           241      2.02%     98.75% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6           119      1.00%     99.75% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7            22      0.18%     99.93% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8             8      0.07%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total        11644                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.440539                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                  54                       # Number of floating instruction queue reads
+system.cpu.iq.ISSUE:issued_per_cycle::total        11948                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     0.397310                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                 58                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses                   9220                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads              29952                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses         7973                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes             17769                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                      11873                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                      9061                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                   2                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined            5926                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued                59                       # Number of squashed instructions issued
+system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses                   8792                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads              29375                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses         7805                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes             14943                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                      10540                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                      8626                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded                  25                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined            4372                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued                25                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved              1                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined        10171                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined         6854                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -403,101 +415,101 @@ system.cpu.itb.read_misses                          0                       # DT
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses              41                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34487.804878                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31365.853659                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency      1414000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses              42                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.761905                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31285.714286                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency      1445000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses                41                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      1286000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses                42                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency      1314000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses           41                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses               434                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34312.182741                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31166.666667                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                    40                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      13519000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.907834                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 394                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               10                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency     11968000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.884793                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            384                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses           42                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses               397                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34355.153203                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31244.318182                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                    38                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency      12333500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.904282                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                 359                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits                7                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency     10998000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.886650                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses            352                       # number of ReadReq MSHR misses
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.104167                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.107955                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                475                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34328.735632                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.882353                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                     40                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       14933000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.915789                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                  435                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency     13254000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.894737                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses             425                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_accesses                439                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34360.349127                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31248.730964                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                     38                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency       13778500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.913440                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                  401                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                 7                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency     12312000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.897494                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses             394                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.006174                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0           202.304778                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses               475                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34328.735632                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.882353                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.005712                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           187.177998                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses               439                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34360.349127                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31248.730964                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                    40                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      14933000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.915789                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                 435                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               10                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency     13254000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.894737                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses            425                       # number of overall MSHR misses
+system.cpu.l2cache.overall_hits                    38                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency      13778500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.913440                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                 401                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits                7                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency     12312000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.897494                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses            394                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                   384                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   352                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               202.304778                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                      40                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse               187.177998                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                      38                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.memDep0.conflictingLoads                12                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               11                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads                 2545                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1654                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                   15406                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                      3                       # number of misc regfile writes
-system.cpu.numCycles                            20568                       # number of cpu cycles simulated
+system.cpu.memDep0.conflictingLoads                 7                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                3                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads                 2420                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1527                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                   14141                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      4                       # number of misc regfile writes
+system.cpu.numCycles                            21711                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles              346                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps           4006                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents              46                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles              7474                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents            123                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups          37531                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts           13957                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands        10098                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles               2298                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles            1138                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles            185                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps              6089                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups          816                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        36715                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles          203                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts            4                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts                537                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts            1                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                        21909                       # The number of ROB reads
-system.cpu.rob.rob_writes                       24423                       # The number of ROB writes
-system.cpu.timesIdled                             183                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:BlockCycles              323                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps           4124                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents              29                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles              7791                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents            132                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups          30367                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts           11639                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands         8331                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles               2090                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles             804                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles            195                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps              4204                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups          390                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups        29977                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles          745                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts           16                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts                568                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts           14                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                        21349                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21656                       # The number of ROB writes
+system.cpu.timesIdled                             201                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
index 327106c53..e51c73913 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -66,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
index 301661eda..9914f72a8 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:25
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 21:03:49
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 2816000 because target called exit()
+Exiting @ tick 2875500 because target called exit()
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 25bd032b8..95e8b4e85 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 100802                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 225720                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                               50271986                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 642377                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 242352                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                              312928501                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        5620                       # Number of instructions simulated
+sim_insts                                        5739                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
-sim_ticks                                     2816000                       # Number of ticks simulated
+sim_ticks                                     2875500                       # Number of ticks simulated
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -52,24 +52,24 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                             5633                       # number of cpu cycles simulated
+system.cpu.numCycles                             5752                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                       5633                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                       5752                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          775                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_fp_insts                            16                       # number of float instructions
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                         185                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                             5620                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  4889                       # Number of integer alu accesses
-system.cpu.num_int_insts                         4889                       # number of integer instructions
-system.cpu.num_int_register_reads               14091                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3689                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1207                       # Number of load instructions
-system.cpu.num_mem_refs                          2145                       # number of memory refs
+system.cpu.num_insts                             5739                       # Number of instructions executed
+system.cpu.num_int_alu_accesses                  4985                       # Number of integer alu accesses
+system.cpu.num_int_insts                         4985                       # number of integer instructions
+system.cpu.num_int_register_reads               14295                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3802                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1201                       # Number of load instructions
+system.cpu.num_mem_refs                          2139                       # number of memory refs
 system.cpu.num_store_insts                        938                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
index d0bdfed8e..ef085e35a 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
@@ -166,7 +169,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
index de21768b5..567715f28 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:58:13
-M5 executing on burrito
+M5 compiled Mar 11 2011 20:10:09
+M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
+M5 started Mar 11 2011 20:10:13
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 26346000 because target called exit()
+Exiting @ tick 26361000 because target called exit()
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
index 438991f53..c331a990a 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -1,76 +1,80 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 265936                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 233432                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1242220035                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   4300                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 250076                       # Number of bytes of host memory used
+host_seconds                                     1.32                       # Real time elapsed on the host
+host_tick_rate                               19945674                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        5563                       # Number of instructions simulated
+sim_insts                                        5682                       # Number of instructions simulated
 sim_seconds                                  0.000026                       # Number of seconds simulated
-sim_ticks                                    26346000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses               1164                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 48787.878788                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 45787.878788                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits                   1065                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        4830000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.085052                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                   99                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      4533000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.085052                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses              99                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses               924                       # number of WriteReq accesses(hits+misses)
+sim_ticks                                    26361000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits               11                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses               1147                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits                   1049                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency        4816000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.085440                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                   98                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency      4522000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.085440                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses              98                       # number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses            11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits                11                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses               913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits                   881                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits                   870                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency       2408000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.046537                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.047097                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                  43                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_miss_latency      2279000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.046537                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.047097                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses             43                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  13.704225                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  13.765957                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses                2088                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50971.830986                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47971.830986                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    1946                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         7238000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.068008                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                   142                       # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses                2060                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 51234.042553                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                    1919                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency         7224000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.068447                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                   141                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      6812000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.068008                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses              142                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency      6801000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.068447                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses              141                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.020405                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0             83.579331                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses               2088                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 50971.830986                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 47971.830986                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.020249                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0             82.937979                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses               2060                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 51234.042553                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   1946                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        7238000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.068008                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                  142                       # number of overall misses
+system.cpu.dcache.overall_hits                   1919                       # number of overall hits
+system.cpu.dcache.overall_miss_latency        7224000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.068447                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                  141                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      6812000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.068008                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses             142                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency      6801000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.068447                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses             141                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.sampled_refs                    142                       # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs                    141                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 83.579331                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1946                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 82.937979                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1941                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
@@ -94,59 +98,59 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses               4580                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses               4614                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 53211.618257                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits                   4339                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits                   4373                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       12824000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.052620                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate          0.052232                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  241                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_miss_latency     12101000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.052620                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate     0.052232                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             241                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  18.004149                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  18.145228                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses                4580                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses                4614                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 53211.618257                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                    4339                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits                    4373                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        12824000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.052620                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate           0.052232                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   241                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency     12101000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.052620                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate      0.052232                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              241                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.055892                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            114.467059                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses               4580                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.055921                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            114.525744                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses               4614                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 53211.618257                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                   4339                       # number of overall hits
+system.cpu.icache.overall_hits                   4373                       # number of overall hits
 system.cpu.icache.overall_miss_latency       12824000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.052620                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate          0.052232                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  241                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency     12101000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.052620                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate     0.052232                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             241                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.replacements                      1                       # number of replacements
 system.cpu.icache.sampled_refs                    241                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                114.467059                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     4339                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                114.525744                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     4373                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -180,80 +184,80 @@ system.cpu.l2cache.ReadExReq_misses                43                       # nu
 system.cpu.l2cache.ReadExReq_mshr_miss_latency      1720000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses           43                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses               340                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses               339                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                    33                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits                    32                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_miss_latency      15964000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.902941                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.905605                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                 307                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency     12280000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.902941                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.905605                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            307                       # number of ReadReq MSHR misses
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.107492                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.104235                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                383                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses                382                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                     33                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits                     32                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_miss_latency       18200000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.913838                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate          0.916230                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  350                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_miss_latency     14000000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.913838                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.916230                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             350                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.004696                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0           153.883328                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses               383                       # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::0                  0.004698                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           153.954484                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses               382                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                    33                       # number of overall hits
+system.cpu.l2cache.overall_hits                    32                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency      18200000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.913838                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate         0.916230                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 350                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_miss_latency     14000000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.913838                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.916230                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses            350                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   307                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               153.883328                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                      33                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse               153.954484                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                      32                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            52692                       # number of cpu cycles simulated
+system.cpu.numCycles                            52722                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      52692                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_busy_cycles                      52722                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          775                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_fp_insts                            16                       # number of float instructions
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                         185                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                             5563                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  4889                       # Number of integer alu accesses
-system.cpu.num_int_insts                         4889                       # number of integer instructions
-system.cpu.num_int_register_reads               15212                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3689                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1207                       # Number of load instructions
-system.cpu.num_mem_refs                          2145                       # number of memory refs
+system.cpu.num_insts                             5682                       # Number of instructions executed
+system.cpu.num_int_alu_accesses                  4985                       # Number of integer alu accesses
+system.cpu.num_int_insts                         4985                       # number of integer instructions
+system.cpu.num_int_register_reads               15421                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3802                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1201                       # Number of load instructions
+system.cpu.num_mem_refs                          2139                       # number of memory refs
 system.cpu.num_store_insts                        938                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 859778cbe..9699a97a6 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -78,6 +78,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -122,6 +123,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -173,7 +175,7 @@ latency_var=0
 null=false
 range=134217728:268435455
 zero=false
-port=system.membus.port[2]
+port=system.membus.port[1]
 
 [system.intrctrl]
 type=IntrControl
@@ -196,6 +198,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=false
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -227,6 +230,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
@@ -261,7 +265,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.diskmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -287,7 +291,7 @@ latency_var=0
 null=false
 range=0:134217727
 zero=true
-port=system.membus.port[1]
+port=system.membus.port[2]
 
 [system.realview]
 type=RealView
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index cffb99aaf..725f5e8b2 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 21 2011 14:33:02
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 14:33:10
+M5 compiled Mar  8 2011 18:03:23
+M5 revision bc33117f65cf 8095 default qtip tip ext/m5threads_regs_stats_2.patch
+M5 started Mar  8 2011 18:03:32
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
+command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 26073617500 because m5_exit instruction encountered
+Exiting @ tick 26404802500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 2d67e997e..ee0ac0aeb 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,63 +1,63 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1506664                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 378044                       # Number of bytes of host memory used
-host_seconds                                    34.14                       # Real time elapsed on the host
-host_tick_rate                              763738517                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1902387                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 375352                       # Number of bytes of host memory used
+host_seconds                                    27.39                       # Real time elapsed on the host
+host_tick_rate                              964164912                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    51436382                       # Number of instructions simulated
-sim_seconds                                  0.026074                       # Number of seconds simulated
-sim_ticks                                 26073617500                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0       100454                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       100454                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::0         95292                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        95292                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.051387                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0         5162                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total         5162                       # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::0         7830681                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      7830681                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0             7594158                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7594158                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0       0.030205                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0            236523                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        236523                       # number of ReadReq misses
-system.cpu.dcache.StoreCondReq_accesses::0       100453                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       100453                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0         100453                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       100453                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0        6676067                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6676067                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0            6503881                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6503881                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0      0.025792                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0           172186                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       172186                       # number of WriteReq misses
+sim_insts                                    52098748                       # Number of instructions simulated
+sim_seconds                                  0.026405                       # Number of seconds simulated
+sim_ticks                                 26404802500                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses::0       100461                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       100461                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits::0         95295                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        95295                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.051423                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0         5166                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         5166                       # number of LoadLockedReq misses
+system.cpu.dcache.ReadReq_accesses::0         7831304                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      7831304                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::0             7594731                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7594731                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate::0       0.030209                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0            236573                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        236573                       # number of ReadReq misses
+system.cpu.dcache.StoreCondReq_accesses::0       100460                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       100460                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::0         100460                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       100460                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::0        6676835                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6676835                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_hits::0            6504601                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6504601                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate::0      0.025796                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0           172234                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       172234                       # number of WriteReq misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  34.695419                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  34.689734                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::0         14506748                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0         14508139                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     14506748                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     14508139                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0             14098039                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::0             14099332                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         14098039                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         14099332                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0        0.028174                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::0        0.028178                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0             408709                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0             408807                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         408709                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         408807                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
@@ -67,26 +67,26 @@ system.cpu.dcache.demand_mshr_misses                0                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999480                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0            511.733850                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0        14506748                       # number of overall (read+write) accesses
+system.cpu.dcache.occ_%::0                   0.999487                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0            511.737179                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0        14508139                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     14506748                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     14508139                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0            14098039                       # number of overall hits
+system.cpu.dcache.overall_hits::0            14099332                       # number of overall hits
 system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        14098039                       # number of overall hits
+system.cpu.dcache.overall_hits::total        14099332                       # number of overall hits
 system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0       0.028174                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0       0.028178                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0            408709                       # number of overall misses
+system.cpu.dcache.overall_misses::0            408807                       # number of overall misses
 system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total        408709                       # number of overall misses
+system.cpu.dcache.overall_misses::total        408807                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
@@ -95,66 +95,66 @@ system.cpu.dcache.overall_mshr_miss_rate::total     no_value
 system.cpu.dcache.overall_mshr_misses               0                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 411520                       # number of replacements
-system.cpu.dcache.sampled_refs                 412032                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                 411625                       # number of replacements
+system.cpu.dcache.sampled_refs                 412137                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                511.733850                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14295623                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               21760000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   381867                       # number of writebacks
-system.cpu.dtb.accesses                      15531286                       # DTB accesses
+system.cpu.dcache.tagsinuse                511.737179                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14296923                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               21760500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   381907                       # number of writebacks
+system.cpu.dtb.accesses                      15532701                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                     2267                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                     2238                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid               33670                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                          15525735                       # DTB hits
+system.cpu.dtb.hits                          15527171                       # DTB hits
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                            5551                       # DTB misses
+system.cpu.dtb.misses                            5530                       # DTB misses
 system.cpu.dtb.perms_faults                       255                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                    775                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                  8743013                       # DTB read accesses
-system.cpu.dtb.read_hits                      8738461                       # DTB read hits
-system.cpu.dtb.read_misses                       4552                       # DTB read misses
-system.cpu.dtb.write_accesses                 6788273                       # DTB write accesses
-system.cpu.dtb.write_hits                     6787274                       # DTB write hits
-system.cpu.dtb.write_misses                       999                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::0        41564629                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     41564629                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::0            41131432                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        41131432                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate::0       0.010422                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0            433197                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        433197                       # number of ReadReq misses
+system.cpu.dtb.prefetch_faults                    767                       # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses                  8743653                       # DTB read accesses
+system.cpu.dtb.read_hits                      8739120                       # DTB read hits
+system.cpu.dtb.read_misses                       4533                       # DTB read misses
+system.cpu.dtb.write_accesses                 6789048                       # DTB write accesses
+system.cpu.dtb.write_hits                     6788051                       # DTB write hits
+system.cpu.dtb.write_misses                       997                       # DTB write misses
+system.cpu.icache.ReadReq_accesses::0        41565893                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     41565893                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_hits::0            41132493                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        41132493                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_rate::0       0.010427                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0            433400                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        433400                       # number of ReadReq misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  94.948781                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  94.906756                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::0         41564629                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::0         41565893                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     41564629                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     41565893                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::0             41131432                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::0             41132493                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         41131432                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         41132493                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0        0.010422                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::0        0.010427                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::0             433197                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::0             433400                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         433197                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         433400                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
@@ -164,26 +164,26 @@ system.cpu.icache.demand_mshr_misses                0                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.930040                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            476.180679                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0        41564629                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.930522                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            476.427149                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses::0        41565893                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     41564629                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     41565893                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0            41131432                       # number of overall hits
+system.cpu.icache.overall_hits::0            41132493                       # number of overall hits
 system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total        41131432                       # number of overall hits
+system.cpu.icache.overall_hits::total        41132493                       # number of overall hits
 system.cpu.icache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0       0.010422                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::0       0.010427                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::0            433197                       # number of overall misses
+system.cpu.icache.overall_misses::0            433400                       # number of overall misses
 system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total        433197                       # number of overall misses
+system.cpu.icache.overall_misses::total        433400                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
@@ -192,15 +192,15 @@ system.cpu.icache.overall_mshr_miss_rate::total     no_value
 system.cpu.icache.overall_mshr_misses               0                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                 432684                       # number of replacements
-system.cpu.icache.sampled_refs                 433196                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                 432887                       # number of replacements
+system.cpu.icache.sampled_refs                 433399                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                476.180679                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 41131432                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle             4544230000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                    33708                       # number of writebacks
+system.cpu.icache.tagsinuse                476.427149                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 41132493                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle             4575196500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                    33681                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                      41565756                       # DTB accesses
+system.cpu.itb.accesses                      41567020                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.itb.flush_entries                     1478                       # Number of entries that have been flushed from TLB
@@ -208,11 +208,11 @@ system.cpu.itb.flush_tlb                            2                       # Nu
 system.cpu.itb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid               33670                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                          41562934                       # DTB hits
-system.cpu.itb.inst_accesses                 41565756                       # ITB inst accesses
-system.cpu.itb.inst_hits                     41562934                       # ITB inst hits
-system.cpu.itb.inst_misses                       2822                       # ITB inst misses
-system.cpu.itb.misses                            2822                       # DTB misses
+system.cpu.itb.hits                          41564192                       # DTB hits
+system.cpu.itb.inst_accesses                 41567020                       # ITB inst accesses
+system.cpu.itb.inst_hits                     41564192                       # ITB inst hits
+system.cpu.itb.inst_misses                       2828                       # ITB inst misses
+system.cpu.itb.misses                            2828                       # DTB misses
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
@@ -224,25 +224,25 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                         52147236                       # number of cpu cycles simulated
+system.cpu.numCycles                         52809606                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                   52147236                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                   6059                       # Number of float alu accesses
-system.cpu.num_fp_insts                          6059                       # number of float instructions
-system.cpu.num_fp_register_reads                 4227                       # number of times the floating registers were read
+system.cpu.num_busy_cycles                   52809606                       # Number of busy cycles
+system.cpu.num_conditional_control_insts      6951306                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                   6058                       # Number of float alu accesses
+system.cpu.num_fp_insts                          6058                       # number of float instructions
+system.cpu.num_fp_register_reads                 4226                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                1834                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     1111841                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                         51436382                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              41848094                       # Number of integer alu accesses
-system.cpu.num_int_insts                     41848094                       # number of integer instructions
-system.cpu.num_int_register_reads           129780130                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           34330061                       # number of times the integer registers were written
-system.cpu.num_load_insts                     9213901                       # Number of load instructions
-system.cpu.num_mem_refs                      16300106                       # number of memory refs
-system.cpu.num_store_insts                    7086205                       # Number of store instructions
+system.cpu.num_insts                         52098748                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              42510432                       # Number of integer alu accesses
+system.cpu.num_int_insts                     42510432                       # number of integer instructions
+system.cpu.num_int_register_reads           131106249                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           34920214                       # number of times the integer registers were written
+system.cpu.num_load_insts                     9214448                       # Number of load instructions
+system.cpu.num_mem_refs                      16301436                       # number of memory refs
+system.cpu.num_store_insts                    7086988                       # Number of store instructions
 system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
@@ -310,61 +310,61 @@ system.iocache.tagsinuse                            0                       # Cy
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                           0                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               170347                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           170347                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0                    60613                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                60613                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0            0.644179                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 109734                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             109734                       # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0                 672769                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                   6110                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             678879                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0                     651602                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                       6087                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 657689                       # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0              0.031463                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.003764                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.035227                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                    21167                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       23                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                21190                       # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0                1839                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1839                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               170398                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           170398                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_hits::0                    60546                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                60546                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_rate::0            0.644679                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 109852                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             109852                       # number of ReadExReq misses
+system.l2c.ReadReq_accesses::0                 673040                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                   6142                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             679182                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits::0                     651887                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                       6117                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 658004                       # number of ReadReq hits
+system.l2c.ReadReq_miss_rate::0              0.031429                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.004070                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.035499                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                    21153                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                       25                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                21178                       # number of ReadReq misses
+system.l2c.UpgradeReq_accesses::0                1836                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1836                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_hits::0                      17                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  17                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_rate::0           0.990756                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                  1822                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1822                       # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0               415575                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           415575                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   415575                       # number of Writeback hits
-system.l2c.Writeback_hits::total               415575                       # number of Writeback hits
+system.l2c.UpgradeReq_miss_rate::0           0.990741                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                  1819                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1819                       # number of UpgradeReq misses
+system.l2c.Writeback_accesses::0               415588                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           415588                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   415588                       # number of Writeback hits
+system.l2c.Writeback_hits::total               415588                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          6.741439                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          6.751328                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                  843116                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                    6110                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              849226                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::0                  843438                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                    6142                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              849580                       # number of demand (read+write) accesses
 system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total            0                       # average overall miss latency
 system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.demand_hits::0                      712215                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                        6087                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  718302                       # number of demand (read+write) hits
+system.l2c.demand_hits::0                      712433                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                        6117                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  718550                       # number of demand (read+write) hits
 system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.155259                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.003764                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.159023                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    130901                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        23                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                130924                       # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0               0.155323                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.004070                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.159393                       # miss rate for demand accesses
+system.l2c.demand_misses::0                    131005                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                        25                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                131030                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
@@ -374,28 +374,28 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.076407                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.476934                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                  5007.401793                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 31256.365097                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                 843116                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                   6110                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             849226                       # number of overall (read+write) accesses
+system.l2c.occ_%::0                          0.076956                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.477052                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                  5043.356614                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 31264.101168                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                 843438                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                   6142                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             849580                       # number of overall (read+write) accesses
 system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total            0                       # average overall miss latency
 system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                     712215                       # number of overall hits
-system.l2c.overall_hits::1                       6087                       # number of overall hits
-system.l2c.overall_hits::total                 718302                       # number of overall hits
+system.l2c.overall_hits::0                     712433                       # number of overall hits
+system.l2c.overall_hits::1                       6117                       # number of overall hits
+system.l2c.overall_hits::total                 718550                       # number of overall hits
 system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.155259                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.003764                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.159023                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   130901                       # number of overall misses
-system.l2c.overall_misses::1                       23                       # number of overall misses
-system.l2c.overall_misses::total               130924                       # number of overall misses
+system.l2c.overall_miss_rate::0              0.155323                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.004070                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.159393                       # miss rate for overall accesses
+system.l2c.overall_misses::0                   131005                       # number of overall misses
+system.l2c.overall_misses::1                       25                       # number of overall misses
+system.l2c.overall_misses::total               131030                       # number of overall misses
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
 system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
@@ -404,12 +404,12 @@ system.l2c.overall_mshr_miss_rate::total            0                       # ms
 system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                         97028                       # number of replacements
-system.l2c.sampled_refs                        129660                       # Sample count of references to valid blocks.
+system.l2c.replacements                         97025                       # number of replacements
+system.l2c.sampled_refs                        129753                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     36263.766890                       # Cycle average of tags in use
-system.l2c.total_refs                          874095                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     36307.457782                       # Cycle average of tags in use
+system.l2c.total_refs                          876005                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                           90970                       # number of writebacks
+system.l2c.writebacks                           90930                       # number of writebacks
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
index 586cb6b73..53b01d583 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
@@ -1 +1 @@
-build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
+build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
index 14d51f6d3..25e2f6c56 100644
Binary files a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal and b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal differ
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 49b04d190..54cda093b 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -75,6 +75,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -119,6 +120,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -170,7 +172,7 @@ latency_var=0
 null=false
 range=134217728:268435455
 zero=false
-port=system.membus.port[2]
+port=system.membus.port[1]
 
 [system.intrctrl]
 type=IntrControl
@@ -193,6 +195,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=false
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -224,6 +227,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
@@ -258,7 +262,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.diskmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -284,7 +288,7 @@ latency_var=0
 null=false
 range=0:134217727
 zero=true
-port=system.membus.port[1]
+port=system.membus.port[2]
 
 [system.realview]
 type=RealView
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 1503baa73..231e421ce 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 21 2011 14:33:02
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 14:33:10
+M5 compiled Mar  8 2011 18:03:23
+M5 revision bc33117f65cf 8095 default qtip tip ext/m5threads_regs_stats_2.patch
+M5 started Mar  8 2011 18:03:32
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing
+command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index a33aa42fc..b7164e421 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,11 +1,11 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 844061                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 378168                       # Number of bytes of host memory used
-host_seconds                                    59.91                       # Real time elapsed on the host
-host_tick_rate                             1914863662                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1109216                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 375472                       # Number of bytes of host memory used
+host_seconds                                    46.19                       # Real time elapsed on the host
+host_tick_rate                             2483966419                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    50570667                       # Number of instructions simulated
+sim_insts                                    51230867                       # Number of instructions simulated
 sim_seconds                                  0.114727                       # Number of seconds simulated
 sim_ticks                                114726567000                       # Number of ticks simulated
 system.cpu.dcache.LoadLockedReq_accesses::0       100290                       # number of LoadLockedReq accesses(hits+misses)
@@ -276,18 +276,18 @@ system.cpu.numCycles                        229453134                       # nu
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.num_busy_cycles                  229453134                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts      6949779                       # number of instructions that are conditional controls
 system.cpu.num_fp_alu_accesses                   6058                       # Number of float alu accesses
 system.cpu.num_fp_insts                          6058                       # number of float instructions
 system.cpu.num_fp_register_reads                 4226                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                1834                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     1112296                       # number of times a function call or return occured
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_insts                         50570667                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              41841366                       # Number of integer alu accesses
-system.cpu.num_int_insts                     41841366                       # number of integer instructions
-system.cpu.num_int_register_reads           138034734                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           34325875                       # number of times the integer registers were written
+system.cpu.num_insts                         51230867                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              42501566                       # Number of integer alu accesses
+system.cpu.num_int_insts                     42501566                       # number of integer instructions
+system.cpu.num_int_register_reads           139355134                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           34914798                       # number of times the integer registers were written
 system.cpu.num_load_insts                     9211791                       # Number of load instructions
 system.cpu.num_mem_refs                      16296219                       # number of memory refs
 system.cpu.num_store_insts                    7084428                       # Number of store instructions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
index 8953751c2..624e9a5f7 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
@@ -1 +1 @@
-build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
+build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!