From 2f40b3b8ae4fddcdd167fc86469254f40736c888 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 17 Mar 2011 19:20:19 -0500 Subject: [PATCH 01/18] O3: Fix unaligned stores when cache blocked Without this change the a store can be issued to the cache multiple times. If this case occurs when the l1 cache is out of mshrs (and thus blocked) the processor will never make forward progress because each cycle it will send a single request using the recently freed mshr and not completing the multipart store. This will continue forever. --- src/cpu/o3/lsq_unit_impl.hh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index b5d337935..1a4e686a3 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -1103,7 +1103,9 @@ LSQUnit::recvRetry() dynamic_cast(retryPkt->senderState); // Don't finish the store unless this is the last packet. - if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) { + if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || + state->pendingPacket == retryPkt) { + state->pktToSend = false; storePostSend(retryPkt); } retryPkt = NULL; From a432d8e0851de8d090676697e29ca6ed4be64fb7 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 17 Mar 2011 19:20:19 -0500 Subject: [PATCH 02/18] Mem: Fix issue with dirty block being lost when entire block transferred to non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues. --- configs/common/Caches.py | 3 +++ src/cpu/o3/fetch_impl.hh | 3 +++ src/dev/io_device.cc | 3 +++ src/mem/cache/BaseCache.py | 1 + src/mem/cache/base.cc | 1 + src/mem/cache/base.hh | 5 +++++ src/mem/cache/cache_impl.hh | 2 +- tests/configs/inorder-timing.py | 6 +++++- tests/configs/memtest.py | 1 + tests/configs/o3-timing-mp.py | 1 + tests/configs/o3-timing.py | 6 +++++- tests/configs/pc-simple-atomic.py | 3 +++ tests/configs/pc-simple-timing.py | 1 + tests/configs/realview-simple-atomic.py | 1 + tests/configs/realview-simple-timing.py | 1 + tests/configs/simple-atomic-mp.py | 1 + tests/configs/simple-timing-mp.py | 1 + tests/configs/simple-timing.py | 6 +++++- tests/configs/tsunami-o3-dual.py | 2 ++ tests/configs/tsunami-o3.py | 2 ++ tests/configs/tsunami-simple-atomic-dual.py | 2 ++ tests/configs/tsunami-simple-atomic.py | 2 ++ tests/configs/tsunami-simple-timing-dual.py | 2 ++ tests/configs/tsunami-simple-timing.py | 2 ++ 24 files changed, 54 insertions(+), 4 deletions(-) diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 3adc7e5c9..ffcd63c49 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -34,6 +34,7 @@ class L1Cache(BaseCache): latency = '1ns' mshrs = 10 tgts_per_mshr = 5 + is_top_level = True class L2Cache(BaseCache): assoc = 8 @@ -49,6 +50,7 @@ class PageTableWalkerCache(BaseCache): mshrs = 10 size = '1kB' tgts_per_mshr = 12 + is_top_level = True class IOCache(BaseCache): assoc = 8 @@ -58,3 +60,4 @@ class IOCache(BaseCache): size = '1kB' tgts_per_mshr = 12 forward_snoops = False + is_top_level = True diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index a2f2b4f8a..3092bd937 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -112,6 +112,9 @@ DefaultFetch::IcachePort::recvTiming(PacketPtr pkt) { DPRINTF(Fetch, "Received timing\n"); if (pkt->isResponse()) { + // We shouldn't ever get a block in ownership state + assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); + fetch->processCacheCompletion(pkt); } //else Snooped a coherence request, just return diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index be97bc4ad..ffe8fdf06 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -139,6 +139,9 @@ DmaPort::recvTiming(PacketPtr pkt) assert(pendingCount >= 0); assert(state); + // We shouldn't ever get a block in ownership state + assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); + state->numBytes += pkt->req->getSize(); assert(state->totBytes >= state->numBytes); if (state->totBytes == state->numBytes) { diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index dffac2234..5c7ae5274 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -48,6 +48,7 @@ class BaseCache(MemObject): size = Param.MemorySize("capacity in bytes") forward_snoops = Param.Bool(True, "forward snoops from mem side to cpu side") + is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)") subblock_size = Param.Int(0, "Size of subblock in IIC used for compression") tgts_per_mshr = Param.Int("max number of accesses per MSHR") diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 9166e1a09..b7e331d54 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -58,6 +58,7 @@ BaseCache::BaseCache(const Params *p) hitLatency(p->latency), numTarget(p->tgts_per_mshr), forwardSnoops(p->forward_snoops), + isTopLevel(p->is_top_level), blocked(0), noTargetMSHR(NULL), missCount(p->max_miss_count), diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index e8a644296..28ddf5054 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -194,6 +194,11 @@ class BaseCache : public MemObject /** Do we forward snoops from mem side port through to cpu side port? */ bool forwardSnoops; + /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should + * never try to forward ownership and similar optimizations to the cpu + * side */ + bool isTopLevel; + /** * Bit vector of the blocking reasons for the access path. * @sa #BlockedCause diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index e4e4a3c92..0b2b273f9 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -216,7 +216,7 @@ Cache::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, if (blk->isDirty()) { // special considerations if we're owner: - if (!deferred_response) { + if (!deferred_response && !isTopLevel) { // if we are responding immediately and can // signal that we're transferring ownership // along with exclusivity, do so diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py index af58cafa5..ddf37b5ec 100644 --- a/tests/configs/inorder-timing.py +++ b/tests/configs/inorder-timing.py @@ -37,8 +37,12 @@ class MyCache(BaseCache): mshrs = 10 tgts_per_mshr = 5 +class MyL1Cache(MyCache): + is_top_level = True + cpu = InOrderCPU(cpu_id=0) -cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), +cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), + MyL1Cache(size = '256kB'), MyCache(size = '2MB', latency='10ns')) cpu.clock = '2GHz' diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index d75bd3d8c..f62381473 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -38,6 +38,7 @@ class L1(BaseCache): block_size = 64 mshrs = 12 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 5c770cdbc..35811282c 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -39,6 +39,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index a4c054122..d4a69d94a 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -37,8 +37,12 @@ class MyCache(BaseCache): mshrs = 10 tgts_per_mshr = 5 +class MyL1Cache(MyCache): + is_top_level = True + cpu = DerivO3CPU(cpu_id=0) -cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), +cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), + MyL1Cache(size = '256kB'), MyCache(size = '2MB')) cpu.clock = '2GHz' diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py index 382899eb5..1c35ff2d9 100644 --- a/tests/configs/pc-simple-atomic.py +++ b/tests/configs/pc-simple-atomic.py @@ -43,6 +43,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache @@ -65,6 +66,7 @@ class PageTableWalkerCache(BaseCache): mshrs = 10 size = '1kB' tgts_per_mshr = 12 + is_top_level = True # --------------------- # I/O Cache @@ -78,6 +80,7 @@ class IOCache(BaseCache): tgts_per_mshr = 12 addr_range = AddrRange(0, size=mem_size) forward_snoops = False + is_top_level = True #cpu cpu = AtomicSimpleCPU(cpu_id=0) diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py index 7452e2542..9c9f4aeca 100644 --- a/tests/configs/pc-simple-timing.py +++ b/tests/configs/pc-simple-timing.py @@ -44,6 +44,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py index ab6d612d4..7340be7a4 100644 --- a/tests/configs/realview-simple-atomic.py +++ b/tests/configs/realview-simple-atomic.py @@ -40,6 +40,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py index 53b6ab2b2..83b643c52 100644 --- a/tests/configs/realview-simple-timing.py +++ b/tests/configs/realview-simple-timing.py @@ -41,6 +41,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index d88a9b395..4db741b8a 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -38,6 +38,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index f5793b282..6f4090ec2 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -38,6 +38,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 739e11e55..bc9d016c5 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -36,8 +36,12 @@ class MyCache(BaseCache): mshrs = 10 tgts_per_mshr = 5 +class MyL1Cache(MyCache): + is_top_level = True + cpu = TimingSimpleCPU(cpu_id=0) -cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), +cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), + MyL1Cache(size = '256kB'), MyCache(size = '2MB', latency='10ns')) system = System(cpu = cpu, physmem = PhysicalMemory(), diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py index 7744560f9..125e228a7 100644 --- a/tests/configs/tsunami-o3-dual.py +++ b/tests/configs/tsunami-o3-dual.py @@ -41,6 +41,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache @@ -65,6 +66,7 @@ class IOCache(BaseCache): tgts_per_mshr = 12 addr_range=AddrRange(0, size='8GB') forward_snoops = False + is_top_level = True #cpu cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ] diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py index fd2d66431..13212d5d9 100644 --- a/tests/configs/tsunami-o3.py +++ b/tests/configs/tsunami-o3.py @@ -41,6 +41,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache @@ -65,6 +66,7 @@ class IOCache(BaseCache): tgts_per_mshr = 12 addr_range=AddrRange(0, size='8GB') forward_snoops = False + is_top_level = True #cpu cpu = DerivO3CPU(cpu_id=0) diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 9d3dbaa91..2e56ce851 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -40,6 +40,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache @@ -64,6 +65,7 @@ class IOCache(BaseCache): tgts_per_mshr = 12 addr_range=AddrRange(0, size='8GB') forward_snoops = False + is_top_level = True #cpu cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index cbacf1995..3c1981464 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -40,6 +40,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache @@ -64,6 +65,7 @@ class IOCache(BaseCache): tgts_per_mshr = 12 addr_range=AddrRange(0, size='8GB') forward_snoops = False + is_top_level = True #cpu cpu = AtomicSimpleCPU(cpu_id=0) diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index f0105461d..747cdac18 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -40,6 +40,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache @@ -64,6 +65,7 @@ class IOCache(BaseCache): tgts_per_mshr = 12 addr_range=AddrRange(0, size='8GB') forward_snoops = False + is_top_level = True #cpu cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 9a262b3b2..110e6ee74 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -41,6 +41,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache @@ -65,6 +66,7 @@ class IOCache(BaseCache): tgts_per_mshr = 12 addr_range=AddrRange(0, size='8GB') forward_snoops = False + is_top_level = True #cpu cpu = TimingSimpleCPU(cpu_id=0) From 7112b443629d88ef7a6350652fdf4607563867ed Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 17 Mar 2011 19:20:19 -0500 Subject: [PATCH 03/18] O3: Update regressions for mem block caching change. --- .../alpha/linux/tsunami-o3-dual/config.ini | 18 +- .../ref/alpha/linux/tsunami-o3-dual/simout | 12 +- .../ref/alpha/linux/tsunami-o3-dual/stats.txt | 1732 ++++++++--------- .../ref/alpha/linux/tsunami-o3/config.ini | 16 +- .../ref/alpha/linux/tsunami-o3/simout | 12 +- .../ref/alpha/linux/tsunami-o3/stats.txt | 934 ++++----- 6 files changed, 1367 insertions(+), 1357 deletions(-) diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index b96a83286..80aefb4cf 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -10,12 +10,12 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -142,6 +142,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -440,6 +441,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -573,6 +575,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -871,6 +874,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -922,7 +926,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -942,7 +946,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -967,6 +971,7 @@ assoc=8 block_size=64 forward_snoops=false hash_delay=1 +is_top_level=true latency=50000 max_miss_count=0 mshrs=20 @@ -998,6 +1003,7 @@ assoc=8 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=92 @@ -1068,7 +1074,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index dcb4e3644..66e1dd01f 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:46:17 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:46:32 -M5 executing on burrito +M5 compiled Mar 15 2011 18:10:57 +M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip +M5 started Mar 15 2011 18:10:59 +M5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 118370500 -Exiting @ tick 1900831034500 because m5_exit instruction encountered +Exiting @ tick 1900831106500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 3a665541f..6dbfe53f2 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,395 +1,395 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 67358 # Simulator instruction rate (inst/s) -host_mem_usage 313516 # Number of bytes of host memory used -host_seconds 846.09 # Real time elapsed on the host -host_tick_rate 2246601111 # Simulator tick rate (ticks/s) +host_inst_rate 185731 # Simulator instruction rate (inst/s) +host_mem_usage 330796 # Number of bytes of host memory used +host_seconds 306.85 # Real time elapsed on the host +host_tick_rate 6194726969 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56990797 # Number of instructions simulated +sim_insts 56990828 # Number of instructions simulated sim_seconds 1.900831 # Number of seconds simulated -sim_ticks 1900831034500 # Number of ticks simulated +sim_ticks 1900831106500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 5875698 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 11164328 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 27744 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 509294 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 10430748 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 12489171 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 879952 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 7522146 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 923087 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 5875746 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 11164335 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 27734 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 509345 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 10431005 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 12489231 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 879926 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 7522155 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 922955 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 78252168 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.636069 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.403085 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 78251630 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.636074 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.403101 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 56997236 72.84% 72.84% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 9310198 11.90% 84.74% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 5423748 6.93% 91.67% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 2443659 3.12% 94.79% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 1857092 2.37% 97.16% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 632524 0.81% 97.97% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 342942 0.44% 98.41% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 321682 0.41% 98.82% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 923087 1.18% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 56997001 72.84% 72.84% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 9309948 11.90% 84.74% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 5423861 6.93% 91.67% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 2443172 3.12% 94.79% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 1857246 2.37% 97.16% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 632479 0.81% 97.97% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 343172 0.44% 98.41% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 321796 0.41% 98.82% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 922955 1.18% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 78252168 # Number of insts commited each cycle -system.cpu0.commit.COM:count 49773781 # Number of instructions committed +system.cpu0.commit.COM:committed_per_cycle::total 78251630 # Number of insts commited each cycle +system.cpu0.commit.COM:count 49773809 # Number of instructions committed system.cpu0.commit.COM:fp_insts 245595 # Number of committed floating point instructions. -system.cpu0.commit.COM:function_calls 636046 # Number of function calls committed. -system.cpu0.commit.COM:int_insts 46098576 # Number of committed integer instructions. -system.cpu0.commit.COM:loads 7894849 # Number of loads committed +system.cpu0.commit.COM:function_calls 636047 # Number of function calls committed. +system.cpu0.commit.COM:int_insts 46098602 # Number of committed integer instructions. +system.cpu0.commit.COM:loads 7894859 # Number of loads committed system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed -system.cpu0.commit.COM:refs 13318728 # Number of memory references committed +system.cpu0.commit.COM:refs 13318738 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 652792 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 49773781 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 564764 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 7279166 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 46913211 # Number of Instructions Simulated -system.cpu0.committedInsts_total 46913211 # Number of Instructions Simulated -system.cpu0.cpi 2.403631 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.403631 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 178258 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 178258 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14381.476316 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 652841 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 49773809 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 564763 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 7279602 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 46913237 # Number of Instructions Simulated +system.cpu0.committedInsts_total 46913237 # Number of Instructions Simulated +system.cpu0.cpi 2.403611 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.403611 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 178261 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 178261 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14383.272201 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10558.033333 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 158899 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 158899 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 278411000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108601 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 19359 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19359 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 4359 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158370500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084148 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10560.425277 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 158904 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 158904 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 278417000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108588 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 19357 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19357 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 4355 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158427500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084157 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 15000 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 8018067 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8018067 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 23754.598189 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 15002 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 8017759 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8017759 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 23757.902186 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.786651 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.503104 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 6640677 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6640677 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 32719346000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.171786 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1377390 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1377390 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 392262 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 23413327000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122864 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 6640640 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6640640 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 32717458500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.171759 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1377119 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1377119 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 391971 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 23413523000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122871 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 985128 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920863000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_misses 985148 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920844000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_accesses::0 185114 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 185114 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13329.315068 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13326.438356 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10326.164384 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10323.150685 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_hits::0 181464 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 181464 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 48652000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 48641500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019718 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_misses::0 3650 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 3650 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37690500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37679500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019718 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_misses 3650 # number of StoreCondReq MSHR misses system.cpu0.dcache.WriteReq_accesses::0 5223711 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 5223711 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 32400.753552 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 32402.197389 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30590.522294 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30590.574400 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 3606992 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3606992 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 52382913882 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.309496 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1616719 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1616719 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1353304 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 8058002430 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050427 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 3607020 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3607020 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 52384340899 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.309491 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 1616691 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1616691 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1353284 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 8057771431 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050425 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 263415 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320187498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8768.456221 # average number of cycles each access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 263407 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320171998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8769.741125 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 8.499270 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 83762 # number of cycles access was blocked +system.cpu0.dcache.avg_refs 8.499136 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 83743 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 734463430 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 734404431 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 13241778 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 13241470 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13241778 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 28423.233717 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 13241470 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 28425.918612 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 25206.444175 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 10247669 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 25206.173882 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 10247660 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10247669 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 85102259882 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.226111 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 10247660 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 85101799399 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.226093 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2994109 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2993810 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2994109 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1745566 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 31471329430 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.094288 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 2993810 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1745255 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 31471294431 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.094291 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1248543 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1248555 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.973184 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::0 0.973190 # Average percentage of cache occupancy system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 498.270236 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 498.273055 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 13241778 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::0 13241470 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13241778 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 28423.233717 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 13241470 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 28425.918612 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 25206.444175 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 25206.173882 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 10247669 # number of overall hits +system.cpu0.dcache.overall_hits::0 10247660 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10247669 # number of overall hits -system.cpu0.dcache.overall_miss_latency 85102259882 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.226111 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 10247660 # number of overall hits +system.cpu0.dcache.overall_miss_latency 85101799399 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.226093 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2994109 # number of overall misses +system.cpu0.dcache.overall_misses::0 2993810 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2994109 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1745566 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 31471329430 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.094288 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 2993810 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1745255 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 31471294431 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.094291 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1248543 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2241050498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1248555 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2241015998 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1246737 # number of replacements -system.cpu0.dcache.sampled_refs 1247249 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1246755 # number of replacements +system.cpu0.dcache.sampled_refs 1247267 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 497.270236 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10600706 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 497.273055 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10600692 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 721582 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33790460 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 33337 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 520850 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 62592464 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 32176672 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 11304141 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1271125 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 100674 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 980894 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 795039 # DTB accesses -system.cpu0.dtb.data_acv 690 # DTB access violations -system.cpu0.dtb.data_hits 14240441 # DTB hits -system.cpu0.dtb.data_misses 32243 # DTB misses +system.cpu0.dcache.writebacks 721595 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 33789769 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 33336 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 520770 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 62593203 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 32176765 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 11304168 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1271210 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 100660 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 980927 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 794756 # DTB accesses +system.cpu0.dtb.data_acv 688 # DTB access violations +system.cpu0.dtb.data_hits 14240512 # DTB hits +system.cpu0.dtb.data_misses 32288 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 599364 # DTB read accesses -system.cpu0.dtb.read_acv 521 # DTB read access violations -system.cpu0.dtb.read_hits 8656203 # DTB read hits -system.cpu0.dtb.read_misses 26609 # DTB read misses -system.cpu0.dtb.write_accesses 195675 # DTB write accesses +system.cpu0.dtb.read_accesses 599054 # DTB read accesses +system.cpu0.dtb.read_acv 519 # DTB read access violations +system.cpu0.dtb.read_hits 8656143 # DTB read hits +system.cpu0.dtb.read_misses 26649 # DTB read misses +system.cpu0.dtb.write_accesses 195702 # DTB write accesses system.cpu0.dtb.write_acv 169 # DTB write access violations -system.cpu0.dtb.write_hits 5584238 # DTB write hits -system.cpu0.dtb.write_misses 5634 # DTB write misses -system.cpu0.fetch.Branches 12489171 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 7790772 # Number of cache lines fetched -system.cpu0.fetch.Cycles 12447663 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 374479 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 63679882 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 30613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 745308 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.110757 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 7790769 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 6755650 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.564728 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 79523293 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.800770 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.103978 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.write_hits 5584369 # DTB write hits +system.cpu0.dtb.write_misses 5639 # DTB write misses +system.cpu0.fetch.Branches 12489231 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 7790870 # Number of cache lines fetched +system.cpu0.fetch.Cycles 12447773 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 374462 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 63680808 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 30775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 745389 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.110758 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 7790867 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 6755672 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.564741 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 79522840 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.800786 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.103997 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67075630 84.35% 84.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 894785 1.13% 85.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1774565 2.23% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 813228 1.02% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2745570 3.45% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 583311 0.73% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 681126 0.86% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 829932 1.04% 94.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4125146 5.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67075067 84.35% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 894690 1.13% 85.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1774768 2.23% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 813051 1.02% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2745482 3.45% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 583376 0.73% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 681368 0.86% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 829891 1.04% 94.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4125147 5.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79523293 # Number of instructions fetched each cycle (Total) -system.cpu0.fp_regfile_reads 120916 # number of floating regfile reads +system.cpu0.fetch.rateDist::total 79522840 # Number of instructions fetched each cycle (Total) +system.cpu0.fp_regfile_reads 120909 # number of floating regfile reads system.cpu0.fp_regfile_writes 122710 # number of floating regfile writes -system.cpu0.icache.ReadReq_accesses::0 7790772 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7790772 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.907100 # average ReadReq miss latency +system.cpu0.icache.ReadReq_accesses::0 7790870 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7790870 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.877874 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12016.512006 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 6933292 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6933292 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 12919571500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.110064 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 857480 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 857480 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 36653 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 9863477500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105359 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12016.582299 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 6933419 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6933419 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 12919109500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.110058 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 857451 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 857451 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 36636 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 9863391000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105356 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 820827 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11372.727273 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 820815 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11214.285714 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 8.447909 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu0.icache.avg_refs 8.448187 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 56 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 625500 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 628000 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 7790772 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 7790870 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7790772 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 15066.907100 # average overall miss latency +system.cpu0.icache.demand_accesses::total 7790870 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 15066.877874 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12016.512006 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 6933292 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 12016.582299 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 6933419 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6933292 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 12919571500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.110064 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 6933419 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 12919109500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.110058 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 857480 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 857451 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 857480 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 36653 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 9863477500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.105359 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 857451 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 36636 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 9863391000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.105356 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 820827 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 820815 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.occ_%::0 0.995823 # Average percentage of cache occupancy system.cpu0.icache.occ_blocks::0 509.861442 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 7790772 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::0 7790870 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7790772 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 15066.907100 # average overall miss latency +system.cpu0.icache.overall_accesses::total 7790870 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 15066.877874 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12016.512006 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12016.582299 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 6933292 # number of overall hits +system.cpu0.icache.overall_hits::0 6933419 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6933292 # number of overall hits -system.cpu0.icache.overall_miss_latency 12919571500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.110064 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 6933419 # number of overall hits +system.cpu0.icache.overall_miss_latency 12919109500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.110058 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 857480 # number of overall misses +system.cpu0.icache.overall_misses::0 857451 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 857480 # number of overall misses -system.cpu0.icache.overall_mshr_hits 36653 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 9863477500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.105359 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 857451 # number of overall misses +system.cpu0.icache.overall_mshr_hits 36636 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 9863391000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.105356 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 820827 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 820815 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 820200 # number of replacements -system.cpu0.icache.sampled_refs 820711 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 820188 # number of replacements +system.cpu0.icache.sampled_refs 820699 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.tagsinuse 509.861442 # Cycle average of tags in use -system.cpu0.icache.total_refs 6933292 # Total number of references to valid blocks. +system.cpu0.icache.total_refs 6933419 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 24435382000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 107 # number of writebacks -system.cpu0.idleCycles 33238734 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 8088887 # Number of branches executed -system.cpu0.iew.EXEC:nop 3190702 # number of nop insts executed +system.cpu0.icache.writebacks 160 # number of writebacks +system.cpu0.idleCycles 33238338 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 8088609 # Number of branches executed +system.cpu0.iew.EXEC:nop 3190653 # number of nop insts executed system.cpu0.iew.EXEC:rate 0.446643 # Inst execution rate -system.cpu0.iew.EXEC:refs 14307235 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 5602635 # Number of stores executed +system.cpu0.iew.EXEC:refs 14307346 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 5602769 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 31606218 # num instructions consuming a value -system.cpu0.iew.WB:count 49988672 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.757998 # average fanout of values written-back +system.cpu0.iew.WB:consumers 31606079 # num instructions consuming a value +system.cpu0.iew.WB:count 49988014 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.757991 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 23957449 # num instructions producing a value -system.cpu0.iew.WB:rate 0.443311 # insts written-back per cycle -system.cpu0.iew.WB:sent 50070625 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 711853 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 9019183 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 9134564 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1512032 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 755923 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 5843380 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 57163450 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 8704600 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 462366 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 50364381 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 59583 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 23957137 # num instructions producing a value +system.cpu0.iew.WB:rate 0.443309 # insts written-back per cycle +system.cpu0.iew.WB:sent 50069991 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 711883 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 9018658 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 9134985 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1511781 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 755973 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 5843371 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 57163675 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 8704577 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 462590 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 50363992 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 59575 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 7004 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1271125 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 547384 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 7002 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1271210 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 547356 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 122021 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 410783 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 10667 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 122264 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 410769 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 10661 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 38522 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 18606 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1239715 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 419501 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 38522 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 332064 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 379789 # Number of branches that were predicted taken incorrectly -system.cpu0.int_regfile_reads 66329266 # number of integer regfile reads -system.cpu0.int_regfile_writes 36276231 # number of integer regfile writes -system.cpu0.ipc 0.416037 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.416037 # IPC: Total IPC of All Threads +system.cpu0.iew.lsq.thread.0.memOrderViolation 38527 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 18607 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1240126 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 419492 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 38527 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 332123 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 379760 # Number of branches that were predicted taken incorrectly +system.cpu0.int_regfile_reads 66329017 # number of integer regfile reads +system.cpu0.int_regfile_writes 36275514 # number of integer regfile writes +system.cpu0.ipc 0.416041 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.416041 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35322205 69.50% 69.50% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 55712 0.11% 69.61% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35321880 69.49% 69.50% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 55711 0.11% 69.61% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.61% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.64% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.64% # Type of FU issued @@ -417,15 +417,15 @@ system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 69.65% system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 9003021 17.71% 87.36% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645656 11.11% 98.47% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779190 1.53% 100.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 9003030 17.71% 87.36% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645816 11.11% 98.47% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779182 1.53% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 50826749 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 382289 # FU busy when requested +system.cpu0.iq.ISSUE:FU_type_0::total 50826584 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 382291 # FU busy when requested system.cpu0.iq.ISSUE:fu_busy_rate 0.007521 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 40958 10.71% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 40945 10.71% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.71% # attempts to use FU when none available @@ -454,51 +454,51 @@ system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.71% # system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.71% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 226307 59.20% 69.91% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 115024 30.09% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 226304 59.20% 69.91% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 115042 30.09% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 79523293 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639143 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.209985 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 79522840 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639144 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.209964 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 54765331 68.87% 68.87% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 12086611 15.20% 84.07% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 5449422 6.85% 90.92% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 3416951 4.30% 95.22% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 2222762 2.80% 98.01% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 992615 1.25% 99.26% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 434574 0.55% 99.81% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 111342 0.14% 99.95% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 43685 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 54765189 68.87% 68.87% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 12085919 15.20% 84.07% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 5449520 6.85% 90.92% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 3416832 4.30% 95.21% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 2223696 2.80% 98.01% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 992162 1.25% 99.26% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 434798 0.55% 99.81% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 111045 0.14% 99.95% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 43679 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 79523293 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.450743 # Inst issue rate -system.cpu0.iq.fp_alu_accesses 260476 # Number of floating point alu accesses -system.cpu0.iq.fp_inst_queue_reads 508189 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_wakeup_accesses 246844 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_writes 251997 # Number of floating instruction queue writes -system.cpu0.iq.int_alu_accesses 50944800 # Number of integer alu accesses -system.cpu0.iq.int_inst_queue_reads 181074941 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_wakeup_accesses 49741828 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.int_inst_queue_writes 60494151 # Number of integer instruction queue writes -system.cpu0.iq.iqInstsAdded 52250537 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 50826749 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1722211 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 6740578 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 24052 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 1157447 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3424469 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 79522840 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.450745 # Inst issue rate +system.cpu0.iq.fp_alu_accesses 260468 # Number of floating point alu accesses +system.cpu0.iq.fp_inst_queue_reads 508171 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_wakeup_accesses 246837 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_writes 251931 # Number of floating instruction queue writes +system.cpu0.iq.int_alu_accesses 50944645 # Number of integer alu accesses +system.cpu0.iq.int_inst_queue_reads 181074223 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_wakeup_accesses 49741177 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.int_inst_queue_writes 60494022 # Number of integer instruction queue writes +system.cpu0.iq.iqInstsAdded 52251057 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 50826584 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1721965 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 6740106 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 24097 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 1157202 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3425536 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 951927 # ITB accesses -system.cpu0.itb.fetch_acv 732 # ITB acv -system.cpu0.itb.fetch_hits 922973 # ITB hits -system.cpu0.itb.fetch_misses 28954 # ITB misses +system.cpu0.itb.fetch_accesses 951932 # ITB accesses +system.cpu0.itb.fetch_acv 733 # ITB acv +system.cpu0.itb.fetch_hits 923000 # ITB hits +system.cpu0.itb.fetch_misses 28932 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -515,7 +515,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.22% # nu system.cpu0.kern.callpal::swpctx 3287 2.03% 2.25% # number of callpals executed system.cpu0.kern.callpal::tbi 43 0.03% 2.27% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 147045 90.75% 93.03% # number of callpals executed +system.cpu0.kern.callpal::swpipl 147044 90.75% 93.03% # number of callpals executed system.cpu0.kern.callpal::rdps 6369 3.93% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.96% # number of callpals executed @@ -524,45 +524,45 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.96% # nu system.cpu0.kern.callpal::rti 4450 2.75% 99.71% # number of callpals executed system.cpu0.kern.callpal::callsys 330 0.20% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 162037 # number of callpals executed +system.cpu0.kern.callpal::total 162036 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 176106 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 176105 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 6624 # number of quiesce instructions executed system.cpu0.kern.ipl_count::0 62137 40.37% 40.37% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 238 0.15% 40.53% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1925 1.25% 41.78% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 254 0.17% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 89359 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 153913 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 89358 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 153912 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 61267 49.13% 49.13% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 238 0.19% 49.32% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1925 1.54% 50.87% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 254 0.20% 51.07% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 61013 48.93% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 124697 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862706719500 97.99% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96293500 0.01% 98.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 398446500 0.02% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 103381000 0.01% 98.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37525343500 1.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1900830184000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1862707102000 97.99% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96290500 0.01% 98.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 398437500 0.02% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 103382500 0.01% 98.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37525043500 1.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900830256000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.985999 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682785 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1172 -system.cpu0.kern.mode_good::user 1173 +system.cpu0.kern.ipl_used::31 0.682793 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1171 +system.cpu0.kern.mode_good::user 1172 system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch::kernel 6890 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1172 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.170102 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.169956 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1898860791500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1969384500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1898861301500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1968946500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3288 # number of times the context was actually changed system.cpu0.kern.syscall::2 6 2.99% 2.99% # number of syscalls executed @@ -595,526 +595,526 @@ system.cpu0.kern.syscall::132 1 0.50% 98.51% # nu system.cpu0.kern.syscall::144 1 0.50% 99.00% # number of syscalls executed system.cpu0.kern.syscall::147 2 1.00% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 201 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2324520 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1920330 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 9134564 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5843380 # Number of stores inserted to the mem dependence unit. -system.cpu0.misc_regfile_reads 1626369 # number of misc regfile reads -system.cpu0.misc_regfile_writes 787165 # number of misc regfile writes -system.cpu0.numCycles 112762027 # number of cpu cycles simulated +system.cpu0.memDep0.conflictingLoads 2323915 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1919788 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 9134985 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5843371 # Number of stores inserted to the mem dependence unit. +system.cpu0.misc_regfile_reads 1626355 # number of misc regfile reads +system.cpu0.misc_regfile_writes 787160 # number of misc regfile writes +system.cpu0.numCycles 112761178 # number of cpu cycles simulated system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.rename.RENAME:BlockCycles 12784616 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 33979042 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 1006695 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 33581656 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1371330 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 43310 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 72537525 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 59326371 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 39979107 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 11035754 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1271125 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3987965 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 6000063 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:fp_rename_lookups 359001 # Number of floating rename lookups -system.cpu0.rename.RENAME:int_rename_lookups 72178524 # Number of integer rename lookups -system.cpu0.rename.RENAME:serializeStallCycles 16862175 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1393641 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 10087757 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 207582 # count of temporary serializing insts renamed -system.cpu0.rob.rob_reads 134196739 # The number of ROB reads -system.cpu0.rob.rob_writes 115376344 # The number of ROB writes -system.cpu0.timesIdled 1187239 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.rename.RENAME:BlockCycles 12784143 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 33979065 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 1006573 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 33581705 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1371242 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 43321 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 72539076 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 59327188 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 39979686 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 11035795 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1271210 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3987790 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 6000619 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:fp_rename_lookups 358919 # Number of floating rename lookups +system.cpu0.rename.RENAME:int_rename_lookups 72180157 # Number of integer rename lookups +system.cpu0.rename.RENAME:serializeStallCycles 16862195 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1393628 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 10087517 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 207585 # count of temporary serializing insts renamed +system.cpu0.rob.rob_reads 134196797 # The number of ROB reads +system.cpu0.rob.rob_writes 115377386 # The number of ROB writes +system.cpu0.timesIdled 1187168 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 1159872 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 2699541 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 8252 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.BTBHits 1161804 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 2701483 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 8265 # Number of incorrect RAS predictions. system.cpu1.BPredUnit.condIncorrect 107435 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 2484356 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 2997970 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 209804 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 1520810 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 200192 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.condPredicted 2484023 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 2997822 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 209923 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 1520807 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 198341 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 17838555 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.594502 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.408069 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 17840200 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.594448 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.407345 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 13455309 75.43% 75.43% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 2068240 11.59% 87.02% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 796982 4.47% 91.49% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 568404 3.19% 94.68% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 398869 2.24% 96.91% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 150882 0.85% 97.76% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 111519 0.63% 98.38% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 88158 0.49% 98.88% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 200192 1.12% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 13454331 75.42% 75.42% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 2070557 11.61% 87.02% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 797281 4.47% 91.49% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 568657 3.19% 94.68% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 399402 2.24% 96.92% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 150078 0.84% 97.76% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 111624 0.63% 98.38% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 89929 0.50% 98.89% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 198341 1.11% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 17838555 # Number of insts commited each cycle -system.cpu1.commit.COM:count 10605058 # Number of instructions committed +system.cpu1.commit.COM:committed_per_cycle::total 17840200 # Number of insts commited each cycle +system.cpu1.commit.COM:count 10605063 # Number of instructions committed system.cpu1.commit.COM:fp_insts 116296 # Number of committed floating point instructions. system.cpu1.commit.COM:function_calls 166623 # Number of function calls committed. -system.cpu1.commit.COM:int_insts 9814589 # Number of committed integer instructions. -system.cpu1.commit.COM:loads 1991974 # Number of loads committed +system.cpu1.commit.COM:int_insts 9814594 # Number of committed integer instructions. +system.cpu1.commit.COM:loads 1991971 # Number of loads committed system.cpu1.commit.COM:membars 52733 # Number of memory barriers committed -system.cpu1.commit.COM:refs 3376359 # Number of memory references committed +system.cpu1.commit.COM:refs 3376356 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 164468 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 10605058 # The number of committed instructions +system.cpu1.commit.branchMispredicts 164474 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 10605063 # The number of committed instructions system.cpu1.commit.commitNonSpecStalls 163004 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 1721791 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 10077586 # Number of Instructions Simulated -system.cpu1.committedInsts_total 10077586 # Number of Instructions Simulated -system.cpu1.cpi 1.948890 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.948890 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 46378 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 46378 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11069.539376 # average LoadLockedReq miss latency +system.cpu1.commit.commitSquashedInsts 1721637 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 10077591 # Number of Instructions Simulated +system.cpu1.committedInsts_total 10077591 # Number of Instructions Simulated +system.cpu1.cpi 1.948947 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.948947 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 46373 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 46373 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11076.917360 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7993.965806 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 39648 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 39648 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 74498000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145112 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 6730 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 6730 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 764 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47692000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128639 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7999.664711 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 39645 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 39645 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 74525500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145084 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 6728 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 6728 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 763 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47718000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128631 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 5966 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 2062902 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2062902 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15016.821540 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 5965 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 2063020 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2063020 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15006.932779 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11679.389313 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11671.409798 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 1868657 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1868657 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 2916942500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.094161 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 194245 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 194245 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 99139 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 1110780000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046103 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 1868365 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1868365 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 2921174500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.094354 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 194655 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 194655 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 99535 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 1110184500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046107 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 95106 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses 95120 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.StoreCondReq_accesses::0 43196 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 43196 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13130.603783 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13132.452048 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10135.856884 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 39337 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 39337 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 50671000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089337 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 3859 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3859 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39094000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089291 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10137.707469 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 39338 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 39338 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 50665000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089314 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 3858 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3858 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39091000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089268 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 3857 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 3856 # number of StoreCondReq MSHR misses system.cpu1.dcache.WriteReq_accesses::0 1334800 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 1334800 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 21227.985433 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 21239.554449 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18769.279348 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18778.969096 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1085325 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1085325 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 5295851666 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.186901 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 249475 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 249475 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 201005 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 909746970 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036313 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1085291 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1085291 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 5299459991 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.186926 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 249509 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 249509 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 201036 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 910272969 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036315 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 48470 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377654500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9972.984645 # average number of cycles each access was blocked +system.cpu1.dcache.WriteReq_mshr_misses 48473 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377656000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9801.734092 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 22.879556 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 5275 # number of cycles access was blocked +system.cpu1.dcache.avg_refs 22.873773 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 5359 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 52607494 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 52527493 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 3397702 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 3397820 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3397702 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 18508.956473 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 3397820 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 18508.106220 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14072.874088 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 2953982 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 14070.723984 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 2953656 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2953982 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 8212794166 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.130594 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 2953656 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 8220634491 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.130720 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 443720 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 444164 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 443720 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 300144 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 2020526970 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.042257 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 444164 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 300571 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 2020457469 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.042260 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 143576 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 143593 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.933238 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 477.817937 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 3397702 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.933239 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 477.818308 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 3397820 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3397702 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 18508.956473 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 3397820 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 18508.106220 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14072.874088 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14070.723984 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 2953982 # number of overall hits +system.cpu1.dcache.overall_hits::0 2953656 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 2953982 # number of overall hits -system.cpu1.dcache.overall_miss_latency 8212794166 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.130594 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 2953656 # number of overall hits +system.cpu1.dcache.overall_miss_latency 8220634491 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.130720 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 443720 # number of overall misses +system.cpu1.dcache.overall_misses::0 444164 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 443720 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 300144 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 2020526970 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.042257 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 444164 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 300571 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 2020457469 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.042260 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 143576 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 395332000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 143593 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 395333500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 132522 # number of replacements -system.cpu1.dcache.sampled_refs 132916 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 132541 # number of replacements +system.cpu1.dcache.sampled_refs 132935 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 477.817937 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3041059 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 477.818308 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3040725 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1877659429000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 88703 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 6965197 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 7952 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 127936 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 13953075 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 8268454 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 2505615 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 305805 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 23745 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 99288 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 453627 # DTB accesses -system.cpu1.dtb.data_acv 183 # DTB access violations -system.cpu1.dtb.data_hits 3614601 # DTB hits -system.cpu1.dtb.data_misses 12965 # DTB misses +system.cpu1.dcache.writebacks 88729 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 6964749 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 7942 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 127908 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 13950494 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 8268833 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 2507185 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 305915 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 23718 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 99432 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 453938 # DTB accesses +system.cpu1.dtb.data_acv 180 # DTB access violations +system.cpu1.dtb.data_hits 3612649 # DTB hits +system.cpu1.dtb.data_misses 12920 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 321686 # DTB read accesses +system.cpu1.dtb.read_accesses 321913 # DTB read accesses system.cpu1.dtb.read_acv 80 # DTB read access violations -system.cpu1.dtb.read_hits 2187439 # DTB read hits -system.cpu1.dtb.read_misses 10558 # DTB read misses -system.cpu1.dtb.write_accesses 131941 # DTB write accesses -system.cpu1.dtb.write_acv 103 # DTB write access violations -system.cpu1.dtb.write_hits 1427162 # DTB write hits -system.cpu1.dtb.write_misses 2407 # DTB write misses -system.cpu1.fetch.Branches 2997970 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 1676515 # Number of cache lines fetched -system.cpu1.fetch.Cycles 2637646 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 103832 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 14205200 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 9114 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 191574 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.152645 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 1676514 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 1369676 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.723275 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 18144360 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.782899 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.130950 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_hits 2185375 # DTB read hits +system.cpu1.dtb.read_misses 10510 # DTB read misses +system.cpu1.dtb.write_accesses 132025 # DTB write accesses +system.cpu1.dtb.write_acv 100 # DTB write access violations +system.cpu1.dtb.write_hits 1427274 # DTB write hits +system.cpu1.dtb.write_misses 2410 # DTB write misses +system.cpu1.fetch.Branches 2997822 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 1676432 # Number of cache lines fetched +system.cpu1.fetch.Cycles 2639364 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 103824 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 14202816 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 9160 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 191448 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.152633 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 1676430 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 1371727 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.723132 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 18146115 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.782692 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.130549 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 15506714 85.46% 85.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 209351 1.15% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 321604 1.77% 88.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 202250 1.11% 89.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 379744 2.09% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 126923 0.70% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 169833 0.94% 93.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 250226 1.38% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 977715 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 15506751 85.45% 85.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 211557 1.17% 86.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 323359 1.78% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 200500 1.10% 89.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 379117 2.09% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 126850 0.70% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 170740 0.94% 93.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 250045 1.38% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 977196 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 18144360 # Number of instructions fetched each cycle (Total) -system.cpu1.fp_regfile_reads 63103 # number of floating regfile reads -system.cpu1.fp_regfile_writes 63156 # number of floating regfile writes -system.cpu1.icache.ReadReq_accesses::0 1676515 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1676515 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.731413 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 18146115 # Number of instructions fetched each cycle (Total) +system.cpu1.fp_regfile_reads 63126 # number of floating regfile reads +system.cpu1.fp_regfile_writes 63154 # number of floating regfile writes +system.cpu1.icache.ReadReq_accesses::0 1676432 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1676432 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.725411 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11628.822702 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 1412481 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1412481 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 3874364000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.157490 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 264034 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 264034 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 8194 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 2975118000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152602 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11629.810943 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 1412386 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1412386 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 3874538500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.157505 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 264046 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 264046 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 8197 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 2975475500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152615 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 255840 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 5000 # average number of cycles each access was blocked +system.cpu1.icache.ReadReq_mshr_misses 255849 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5555.555556 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.522142 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu1.icache.avg_refs 5.521576 # Average number of references to valid blocks. +system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 40000 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 50000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 1676515 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 1676432 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1676515 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14673.731413 # average overall miss latency +system.cpu1.icache.demand_accesses::total 1676432 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14673.725411 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11628.822702 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 1412481 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11629.810943 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 1412386 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1412481 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 3874364000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.157490 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 1412386 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 3874538500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.157505 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 264034 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 264046 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 264034 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 8194 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 2975118000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.152602 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 264046 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 8197 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 2975475500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.152615 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 255840 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 255849 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.occ_%::0 0.900434 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 461.022394 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 1676515 # number of overall (read+write) accesses +system.cpu1.icache.occ_blocks::0 461.022397 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 1676432 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1676515 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14673.731413 # average overall miss latency +system.cpu1.icache.overall_accesses::total 1676432 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14673.725411 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11628.822702 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11629.810943 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 1412481 # number of overall hits +system.cpu1.icache.overall_hits::0 1412386 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1412481 # number of overall hits -system.cpu1.icache.overall_miss_latency 3874364000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.157490 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 1412386 # number of overall hits +system.cpu1.icache.overall_miss_latency 3874538500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.157505 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 264034 # number of overall misses +system.cpu1.icache.overall_misses::0 264046 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 264034 # number of overall misses -system.cpu1.icache.overall_mshr_hits 8194 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 2975118000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.152602 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 264046 # number of overall misses +system.cpu1.icache.overall_mshr_hits 8197 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 2975475500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.152615 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 255840 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 255849 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 255273 # number of replacements -system.cpu1.icache.sampled_refs 255785 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 255282 # number of replacements +system.cpu1.icache.sampled_refs 255794 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 461.022394 # Cycle average of tags in use -system.cpu1.icache.total_refs 1412481 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1897915849000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 13 # number of writebacks -system.cpu1.idleCycles 1495744 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 1630347 # Number of branches executed -system.cpu1.iew.EXEC:nop 601729 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.552052 # Inst execution rate -system.cpu1.iew.EXEC:refs 3644132 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 1436628 # Number of stores executed +system.cpu1.icache.tagsinuse 461.022397 # Cycle average of tags in use +system.cpu1.icache.total_refs 1412386 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1897915594000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 23 # number of writebacks +system.cpu1.idleCycles 1494579 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 1630757 # Number of branches executed +system.cpu1.iew.EXEC:nop 601681 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.552014 # Inst execution rate +system.cpu1.iew.EXEC:refs 3642117 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 1436733 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 6274106 # num instructions consuming a value -system.cpu1.iew.WB:count 10735003 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.735138 # average fanout of values written-back +system.cpu1.iew.WB:consumers 6271876 # num instructions consuming a value +system.cpu1.iew.WB:count 10737023 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.735626 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 4612335 # num instructions producing a value -system.cpu1.iew.WB:rate 0.546586 # insts written-back per cycle -system.cpu1.iew.WB:sent 10758148 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 178810 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 256636 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 2309588 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 500342 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 209309 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 1512714 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 12409933 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 2207504 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 107468 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 10842361 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 2486 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 4613753 # num instructions producing a value +system.cpu1.iew.WB:rate 0.546672 # insts written-back per cycle +system.cpu1.iew.WB:sent 10760010 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 178779 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 257448 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 2307630 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 500245 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 209270 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 1513195 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 12409620 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 2205384 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 107607 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 10841947 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 2515 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 4828 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 305805 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 10156 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 4902 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 305915 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 10123 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 22318 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 68189 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 2236 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 20397 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 68108 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 2244 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 10653 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 380 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 317614 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 128329 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 10653 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 104816 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 73994 # Number of branches that were predicted taken incorrectly -system.cpu1.int_regfile_reads 13933756 # number of integer regfile reads -system.cpu1.int_regfile_writes 7611585 # number of integer regfile writes -system.cpu1.ipc 0.513113 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.513113 # IPC: Total IPC of All Threads +system.cpu1.iew.lsq.thread.0.memOrderViolation 10644 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 381 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 315659 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 128810 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 10644 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 104770 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 74009 # Number of branches that were predicted taken incorrectly +system.cpu1.int_regfile_reads 13934200 # number of integer regfile reads +system.cpu1.int_regfile_writes 7613029 # number of integer regfile writes +system.cpu1.ipc 0.513098 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.513098 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3524 0.03% 0.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6870860 62.75% 62.78% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 18138 0.17% 62.95% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.95% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.05% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.05% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.05% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.05% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282503 20.85% 83.91% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1453754 13.28% 97.19% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6872542 62.77% 62.80% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 18152 0.17% 62.96% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.96% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 2280411 20.83% 83.91% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1453875 13.28% 97.19% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307856 2.81% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 10949829 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 154910 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.014147 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 10949554 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 155065 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.014162 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 4092 2.64% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 90881 58.67% 61.31% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 59937 38.69% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 4030 2.60% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 91114 58.76% 61.36% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 59921 38.64% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 18144360 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.603484 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.209438 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 18146115 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.603410 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.208341 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 12920190 71.21% 71.21% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 2565455 14.14% 85.35% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 1066502 5.88% 91.22% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 689185 3.80% 95.02% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 526783 2.90% 97.93% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 236336 1.30% 99.23% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 93675 0.52% 99.75% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7 36919 0.20% 99.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 9315 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 12918859 71.19% 71.19% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 2566374 14.14% 85.34% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 1069941 5.90% 91.23% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 687798 3.79% 95.02% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 527186 2.91% 97.93% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 238422 1.31% 99.24% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 93189 0.51% 99.76% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7 34852 0.19% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 9494 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 18144360 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.557524 # Inst issue rate -system.cpu1.iq.fp_alu_accesses 125165 # Number of floating point alu accesses -system.cpu1.iq.fp_inst_queue_reads 243017 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_wakeup_accesses 117535 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_writes 119622 # Number of floating instruction queue writes -system.cpu1.iq.int_alu_accesses 10976050 # Number of integer alu accesses -system.cpu1.iq.int_inst_queue_reads 39966063 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_wakeup_accesses 10617468 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.int_inst_queue_writes 13352810 # Number of integer instruction queue writes -system.cpu1.iq.iqInstsAdded 11252421 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 10949829 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 555783 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 1655590 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 10152 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 392779 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 854299 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 18146115 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.557493 # Inst issue rate +system.cpu1.iq.fp_alu_accesses 125187 # Number of floating point alu accesses +system.cpu1.iq.fp_inst_queue_reads 243060 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_wakeup_accesses 117556 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_writes 119680 # Number of floating instruction queue writes +system.cpu1.iq.int_alu_accesses 10975908 # Number of integer alu accesses +system.cpu1.iq.int_inst_queue_reads 39967405 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_wakeup_accesses 10619467 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.int_inst_queue_writes 13352100 # Number of integer instruction queue writes +system.cpu1.iq.iqInstsAdded 11252265 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 10949554 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 555674 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 1655179 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 10177 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 392670 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 852165 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 448461 # ITB accesses -system.cpu1.itb.fetch_acv 279 # ITB acv -system.cpu1.itb.fetch_hits 439821 # ITB hits -system.cpu1.itb.fetch_misses 8640 # ITB misses +system.cpu1.itb.fetch_accesses 448608 # ITB accesses +system.cpu1.itb.fetch_acv 274 # ITB acv +system.cpu1.itb.fetch_hits 439933 # ITB hits +system.cpu1.itb.fetch_misses 8675 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1154,11 +1154,11 @@ system.cpu1.kern.ipl_good::22 1922 4.55% 52.28% # nu system.cpu1.kern.ipl_good::30 351 0.83% 53.11% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 19806 46.89% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 42236 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870770703000 98.44% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 347961500 0.02% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 137588500 0.01% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29223568000 1.54% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900479821000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1870770905000 98.44% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 347965500 0.02% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 137591500 0.01% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29223562000 1.54% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900480024000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.975465 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -1173,9 +1173,9 @@ system.cpu1.kern.mode_switch_good::kernel 0.480747 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.108619 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 1.589366 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6317362000 0.33% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1020701000 0.05% 0.39% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893129288000 99.61% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 6317215000 0.33% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1021115000 0.05% 0.39% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893129227000 99.61% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1451 # number of times the context was actually changed system.cpu1.kern.syscall::2 2 1.60% 1.60% # number of syscalls executed system.cpu1.kern.syscall::3 13 10.40% 12.00% # number of syscalls executed @@ -1200,37 +1200,37 @@ system.cpu1.kern.syscall::92 2 1.60% 96.80% # nu system.cpu1.kern.syscall::132 3 2.40% 99.20% # number of syscalls executed system.cpu1.kern.syscall::144 1 0.80% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 125 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 496033 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 413880 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 2309588 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1512714 # Number of stores inserted to the mem dependence unit. -system.cpu1.misc_regfile_reads 594436 # number of misc regfile reads +system.cpu1.memDep0.conflictingLoads 495102 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 416651 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 2307630 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1513195 # Number of stores inserted to the mem dependence unit. +system.cpu1.misc_regfile_reads 594453 # number of misc regfile reads system.cpu1.misc_regfile_writes 255211 # number of misc regfile writes -system.cpu1.numCycles 19640104 # number of cpu cycles simulated +system.cpu1.numCycles 19640694 # number of cpu cycles simulated system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.rename.RENAME:BlockCycles 522822 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 7159583 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 32718 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 8500925 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 256778 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 15506 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 15473473 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 12930857 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 8489204 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 2359874 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 305805 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 801183 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 1329621 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:fp_rename_lookups 171444 # Number of floating rename lookups -system.cpu1.rename.RENAME:int_rename_lookups 15302029 # Number of integer rename lookups -system.cpu1.rename.RENAME:serializeStallCycles 5653749 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 515468 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 2303190 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 52722 # count of temporary serializing insts renamed -system.cpu1.rob.rob_reads 29861070 # The number of ROB reads -system.cpu1.rob.rob_writes 24957765 # The number of ROB writes -system.cpu1.timesIdled 194766 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.rename.RENAME:BlockCycles 523712 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 7159591 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 32710 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 8501498 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 256763 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 15504 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 15470992 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 12928500 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 8487290 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 2361527 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 305915 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 801170 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 1327699 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:fp_rename_lookups 171482 # Number of floating rename lookups +system.cpu1.rename.RENAME:int_rename_lookups 15299510 # Number of integer rename lookups +system.cpu1.rename.RENAME:serializeStallCycles 5652291 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 515456 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 2302074 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 52719 # count of temporary serializing insts renamed +system.cpu1.rob.rob_reads 29864417 # The number of ROB reads +system.cpu1.rob.rob_writes 24957573 # The number of ROB writes +system.cpu1.timesIdled 194633 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1261,37 +1261,37 @@ system.iocache.ReadReq_mshr_misses 172 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137704.871149 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137701.983202 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85701.289902 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5721912806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85698.425972 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5721792806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3561059998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3560940996 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6175.549096 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6175.644708 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64590068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64591068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137612.376666 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137609.500623 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85608.810181 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85605.958058 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5741738804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5741618804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -1299,7 +1299,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41724 # number of demand (read+write) misses system.iocache.demand_misses::total 41724 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3571941996 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571822994 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -1313,14 +1313,14 @@ system.iocache.overall_accesses::0 0 # nu system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137612.376666 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137609.500623 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85608.810181 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85605.958058 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5741738804 # number of overall miss cycles +system.iocache.overall_miss_latency 5741618804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -1328,7 +1328,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41724 # number of overall misses system.iocache.overall_misses::total 41724 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3571941996 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571822994 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -1342,55 +1342,55 @@ system.iocache.tagsinuse 0.467303 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1711286190000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 257294 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 42294 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 299588 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 55984.033368 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 838025.398663 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 257283 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 42295 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 299578 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 55985.536569 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 837818.012343 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40323.668210 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 140895 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 34518 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 175413 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6516485500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.452397 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.183856 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 116399 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 7776 # number of ReadExReq misses +system.l2c.ReadExReq_avg_mshr_miss_latency 40324.759412 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 140886 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 34517 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 175403 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6516548500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.452408 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.183899 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 116397 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 7778 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 124175 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5007191500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.482619 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 2.935996 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_latency 5007327000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.482640 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 2.935926 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 124175 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1807450 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 343665 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2151115 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52801.925207 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3681603.345555 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 1807428 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 343680 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2151108 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52801.503186 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3683358.780376 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40018.264766 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40018.194749 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1503171 # number of ReadReq hits -system.l2c.ReadReq_hits::1 339301 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1842472 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16066517000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.168347 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.012698 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 304279 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4364 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308643 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1503141 # number of ReadReq hits +system.l2c.ReadReq_hits::1 339318 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1842459 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16066811000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.168354 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.012692 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 304287 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4362 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308649 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12350717000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.170753 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.898046 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12350935500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.170758 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.898024 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 308627 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 840465500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_misses 308633 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 840464000 # number of ReadReq MSHR uncacheable cycles system.l2c.SCUpgradeReq_accesses::0 609 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::1 601 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1210 # number of SCUpgradeReq accesses(hits+misses) @@ -1414,120 +1414,120 @@ system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.886855 # m system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_misses 1134 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 2885 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2883 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 1622 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4507 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4505 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_avg_miss_latency::0 5855.677656 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 12557.737628 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 12567.610063 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.987260 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 155 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 349 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 504 # number of UpgradeReq hits +system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.991504 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 153 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 350 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 503 # number of UpgradeReq hits system.l2c.UpgradeReq_miss_latency 15986000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.946274 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.784834 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.946930 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.784217 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_misses::0 2730 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 1273 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4003 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 160188000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.387522 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.467941 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::1 1272 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4002 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 160148000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.388137 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.467324 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 4003 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 4002 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1532818498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 810405 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 810405 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 810405 # number of Writeback hits -system.l2c.Writeback_hits::total 810405 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1532817998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 810507 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 810507 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 810507 # number of Writeback hits +system.l2c.Writeback_hits::total 810507 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.657708 # Average number of references to valid blocks. +system.l2c.avg_refs 5.658014 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2064744 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 385959 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2064711 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 385975 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2450703 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 53682.394848 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1860214.373970 # average overall miss latency +system.l2c.demand_accesses::total 2450686 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 53682.477822 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1860243.780890 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40105.887912 # average overall mshr miss latency -system.l2c.demand_hits::0 1644066 # number of demand (read+write) hits -system.l2c.demand_hits::1 373819 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40106.149840 # average overall mshr miss latency +system.l2c.demand_hits::0 1644027 # number of demand (read+write) hits +system.l2c.demand_hits::1 373835 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2017885 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22583002500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.203743 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.031454 # miss rate for demand accesses +system.l2c.demand_hits::total 2017862 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22583359500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.203750 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.031453 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 420678 # number of demand (read+write) misses +system.l2c.demand_misses::0 420684 # number of demand (read+write) misses system.l2c.demand_misses::1 12140 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 432818 # number of demand (read+write) misses +system.l2c.demand_misses::total 432824 # number of demand (read+write) misses system.l2c.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17357908500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.209615 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.121368 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 17358262500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.209622 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.121337 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 432802 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 432808 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.187715 # Average percentage of cache occupancy +system.l2c.occ_%::0 0.187716 # Average percentage of cache occupancy system.l2c.occ_%::1 0.005740 # Average percentage of cache occupancy system.l2c.occ_%::2 0.351851 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 12302.114841 # Average occupied blocks per context -system.l2c.occ_blocks::1 376.171902 # Average occupied blocks per context -system.l2c.occ_blocks::2 23058.891094 # Average occupied blocks per context -system.l2c.overall_accesses::0 2064744 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 385959 # number of overall (read+write) accesses +system.l2c.occ_blocks::0 12302.143800 # Average occupied blocks per context +system.l2c.occ_blocks::1 376.171509 # Average occupied blocks per context +system.l2c.occ_blocks::2 23058.900248 # Average occupied blocks per context +system.l2c.overall_accesses::0 2064711 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 385975 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2450703 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 53682.394848 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1860214.373970 # average overall miss latency +system.l2c.overall_accesses::total 2450686 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 53682.477822 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1860243.780890 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40105.887912 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40106.149840 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1644066 # number of overall hits -system.l2c.overall_hits::1 373819 # number of overall hits +system.l2c.overall_hits::0 1644027 # number of overall hits +system.l2c.overall_hits::1 373835 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2017885 # number of overall hits -system.l2c.overall_miss_latency 22583002500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.203743 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.031454 # miss rate for overall accesses +system.l2c.overall_hits::total 2017862 # number of overall hits +system.l2c.overall_miss_latency 22583359500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.203750 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.031453 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 420678 # number of overall misses +system.l2c.overall_misses::0 420684 # number of overall misses system.l2c.overall_misses::1 12140 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 432818 # number of overall misses +system.l2c.overall_misses::total 432824 # number of overall misses system.l2c.overall_mshr_hits 16 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17357908500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.209615 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.121368 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 17358262500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.209622 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.121337 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 432802 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2373283998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 432808 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2373281998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 395562 # number of replacements -system.l2c.sampled_refs 431632 # Sample count of references to valid blocks. +system.l2c.replacements 395559 # number of replacements +system.l2c.sampled_refs 431638 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 35737.177838 # Cycle average of tags in use -system.l2c.total_refs 2442048 # Total number of references to valid blocks. +system.l2c.tagsinuse 35737.215556 # Cycle average of tags in use +system.l2c.total_refs 2442214 # Total number of references to valid blocks. system.l2c.warmup_cycle 9270445000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 121361 # number of writebacks +system.l2c.writebacks 121360 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 838d9a364..a3d5d3586 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -10,12 +10,12 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -142,6 +142,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -440,6 +441,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -491,7 +493,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -511,7 +513,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -536,6 +538,7 @@ assoc=8 block_size=64 forward_snoops=false hash_delay=1 +is_top_level=true latency=50000 max_miss_count=0 mshrs=20 @@ -567,6 +570,7 @@ assoc=8 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=92 @@ -637,7 +641,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index bdb8a98f8..9021122e3 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:46:17 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:46:32 -M5 executing on burrito +M5 compiled Mar 15 2011 18:10:57 +M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip +M5 started Mar 15 2011 18:10:59 +M5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1866702838500 because m5_exit instruction encountered +Exiting @ tick 1865724648500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index e3a6bbb06..2e169bdbb 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 66360 # Simulator instruction rate (inst/s) -host_mem_usage 311288 # Number of bytes of host memory used -host_seconds 799.45 # Real time elapsed on the host -host_tick_rate 2334981918 # Simulator tick rate (ticks/s) +host_inst_rate 180508 # Simulator instruction rate (inst/s) +host_mem_usage 328492 # Number of bytes of host memory used +host_seconds 293.90 # Real time elapsed on the host +host_tick_rate 6348189027 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53051251 # Number of instructions simulated -sim_seconds 1.866703 # Number of seconds simulated -sim_ticks 1866702838500 # Number of ticks simulated +sim_insts 53051011 # Number of instructions simulated +sim_seconds 1.865725 # Number of seconds simulated +sim_ticks 1865724648500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6623157 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 12789444 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 40569 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 601028 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11937575 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14339384 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1014923 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8457250 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 1007675 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6620966 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 12786893 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 40572 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 600914 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11937031 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14338397 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1014681 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8457274 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 1008616 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 89231545 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.630319 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.393269 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 89227396 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.630345 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.393343 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 65110491 72.97% 72.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10643752 11.93% 84.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 6057329 6.79% 91.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 2842358 3.19% 94.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2098441 2.35% 97.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 701144 0.79% 98.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 394504 0.44% 98.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 375851 0.42% 98.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 1007675 1.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 65107231 72.97% 72.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10642774 11.93% 84.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 6057714 6.79% 91.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 2842201 3.19% 94.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2098462 2.35% 97.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 700908 0.79% 98.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 394479 0.44% 98.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 375011 0.42% 98.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 1008616 1.13% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 89231545 # Number of insts commited each cycle -system.cpu.commit.COM:count 56244349 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 89227396 # Number of insts commited each cycle +system.cpu.commit.COM:count 56244072 # Number of instructions committed system.cpu.commit.COM:fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 744090 # Number of function calls committed. -system.cpu.commit.COM:int_insts 52084301 # Number of committed integer instructions. -system.cpu.commit.COM:loads 9107235 # Number of loads committed -system.cpu.commit.COM:membars 227951 # Number of memory barriers committed -system.cpu.commit.COM:refs 15496318 # Number of memory references committed +system.cpu.commit.COM:function_calls 744089 # Number of function calls committed. +system.cpu.commit.COM:int_insts 52084090 # Number of committed integer instructions. +system.cpu.commit.COM:loads 9107066 # Number of loads committed +system.cpu.commit.COM:membars 227958 # Number of memory barriers committed +system.cpu.commit.COM:refs 15496059 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 771510 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56244349 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667563 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8699299 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53051251 # Number of Instructions Simulated -system.cpu.committedInsts_total 53051251 # Number of Instructions Simulated -system.cpu.cpi 2.358137 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.358137 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 215722 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 215722 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14725.540425 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 771395 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56244072 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667553 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 8698928 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53051011 # Number of Instructions Simulated +system.cpu.committedInsts_total 53051011 # Number of Instructions Simulated +system.cpu.cpi 2.358035 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.358035 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 215741 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 215741 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14722.823889 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11882.875143 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 193471 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 193471 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 327658000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11882.359679 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 193488 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 193488 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 327627000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103147 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 22251 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22251 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4791 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207475000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080938 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 22253 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22253 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4793 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207466000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080930 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 17460 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9297964 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9297964 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 22717.133732 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses::0 9298482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9298482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 22717.267883 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.439279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.415740 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7723736 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7723736 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 35761948000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.169309 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1574228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1574228 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 490302 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24691226500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116577 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7724340 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7724340 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 35760205500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.169290 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1574142 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1574142 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 490275 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24689857000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116564 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1083926 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 905134500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219685 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219685 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.ReadReq_mshr_misses 1083867 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 905506500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219687 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219687 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 219682 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 219682 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::0 219684 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219684 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_miss_latency 42000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_rate::0 0.000014 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_misses::0 3 # number of StoreCondReq misses @@ -107,287 +107,287 @@ system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000014 system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_misses 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6154252 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6154252 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 29747.302403 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses::0 6154158 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6154158 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 29745.716858 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28091.080381 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28090.291333 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4299090 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4299090 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 55186065021 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.301444 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 1855162 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1855162 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1555538 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 8416761868 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048686 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 4298986 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4298986 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 55183421035 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.301450 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 1855172 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1855172 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1555560 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 8416188367 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048684 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 299624 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235207998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8963.151072 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 299612 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235453998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8964.775985 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.877326 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 83371 # number of cycles access was blocked +system.cpu.dcache.avg_refs 8.878146 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 83356 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 747266868 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 747267867 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15452216 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15452640 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15452216 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26520.172107 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15452640 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26519.480729 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23929.737536 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 12022826 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23929.561177 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 12023326 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12022826 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 90948013021 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.221935 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 12023326 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 90943626535 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.221924 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3429390 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3429314 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3429390 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2045840 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33107988368 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.089537 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3429314 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2045835 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 33106045367 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.089530 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1383550 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1383479 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995490 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15452216 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.995488 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15452640 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15452216 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26520.172107 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15452640 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26519.480729 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23929.737536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23929.561177 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 12022826 # number of overall hits +system.cpu.dcache.overall_hits::0 12023326 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 12022826 # number of overall hits -system.cpu.dcache.overall_miss_latency 90948013021 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.221935 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 12023326 # number of overall hits +system.cpu.dcache.overall_miss_latency 90943626535 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.221924 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3429390 # number of overall misses +system.cpu.dcache.overall_misses::0 3429314 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3429390 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2045840 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33107988368 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.089537 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3429314 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2045835 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 33106045367 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.089530 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1383550 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140342498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1383479 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140960498 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1400366 # number of replacements -system.cpu.dcache.sampled_refs 1400878 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1400295 # number of replacements +system.cpu.dcache.sampled_refs 1400807 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995490 # Cycle average of tags in use -system.cpu.dcache.total_refs 12436050 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.995488 # Cycle average of tags in use +system.cpu.dcache.total_refs 12436569 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 832764 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 37803166 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42143 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 613837 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 71397647 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37493968 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 12849862 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1515496 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134350 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1084548 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1235511 # DTB accesses -system.cpu.dtb.data_acv 814 # DTB access violations -system.cpu.dtb.data_hits 16593720 # DTB hits -system.cpu.dtb.data_misses 46888 # DTB misses +system.cpu.dcache.writebacks 832735 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 37803322 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42125 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 613661 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 71395902 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37491497 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12847985 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1515320 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134367 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1084591 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1236212 # DTB accesses +system.cpu.dtb.data_acv 809 # DTB access violations +system.cpu.dtb.data_hits 16593947 # DTB hits +system.cpu.dtb.data_misses 46903 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 910670 # DTB read accesses -system.cpu.dtb.read_acv 580 # DTB read access violations -system.cpu.dtb.read_hits 10006545 # DTB read hits -system.cpu.dtb.read_misses 38646 # DTB read misses -system.cpu.dtb.write_accesses 324841 # DTB write accesses -system.cpu.dtb.write_acv 234 # DTB write access violations -system.cpu.dtb.write_hits 6587175 # DTB write hits +system.cpu.dtb.read_accesses 911157 # DTB read accesses +system.cpu.dtb.read_acv 576 # DTB read access violations +system.cpu.dtb.read_hits 10006781 # DTB read hits +system.cpu.dtb.read_misses 38661 # DTB read misses +system.cpu.dtb.write_accesses 325055 # DTB write accesses +system.cpu.dtb.write_acv 233 # DTB write access violations +system.cpu.dtb.write_hits 6587166 # DTB write hits system.cpu.dtb.write_misses 8242 # DTB write misses -system.cpu.fetch.Branches 14339384 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8856318 # Number of cache lines fetched -system.cpu.fetch.Cycles 14115387 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 454337 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 72663163 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 43087 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 884394 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.114621 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8856315 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7638080 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.580831 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 90747041 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.800722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.110012 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 14338397 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8855922 # Number of cache lines fetched +system.cpu.fetch.Cycles 14113501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 454413 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 72660960 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 42720 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 884189 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.114619 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8855919 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7635647 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.580841 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 90742716 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.800736 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.110037 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 76631654 84.45% 84.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1046048 1.15% 85.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1970042 2.17% 87.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 921005 1.01% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2984540 3.29% 92.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 648959 0.72% 92.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 776516 0.86% 93.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1074251 1.18% 94.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4694026 5.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 76629215 84.45% 84.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1044484 1.15% 85.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1968851 2.17% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 922109 1.02% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2984062 3.29% 92.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 649093 0.72% 92.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 777227 0.86% 93.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1074028 1.18% 94.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4693647 5.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 90747041 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 164450 # number of floating regfile reads +system.cpu.fetch.rateDist::total 90742716 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 164464 # number of floating regfile reads system.cpu.fp_regfile_writes 166718 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses::0 8856318 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8856318 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14954.328072 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses::0 8855922 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8855922 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14953.893584 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.426022 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7816051 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7816051 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15556494000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.117460 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1040267 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1040267 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 47648 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11850308500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112080 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.313504 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7815698 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7815698 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15555399000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.117461 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1040224 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1040224 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 47681 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11849289500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112077 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 992619 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 12375 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 992543 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs 12554.545455 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.875653 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.875900 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 693000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 690500 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8856318 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8855922 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8856318 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14954.328072 # average overall miss latency +system.cpu.icache.demand_accesses::total 8855922 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14953.893584 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11938.426022 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7816051 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11938.313504 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7815698 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7816051 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15556494000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.117460 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7815698 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15555399000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.117461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1040267 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1040224 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1040267 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 47648 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11850308500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.112080 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1040224 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 47681 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11849289500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.112077 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 992619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 992543 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995726 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.811601 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8856318 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995724 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.810451 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8855922 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8856318 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14954.328072 # average overall miss latency +system.cpu.icache.overall_accesses::total 8855922 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14953.893584 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11938.426022 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11938.313504 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7816051 # number of overall hits +system.cpu.icache.overall_hits::0 7815698 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7816051 # number of overall hits -system.cpu.icache.overall_miss_latency 15556494000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.117460 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7815698 # number of overall hits +system.cpu.icache.overall_miss_latency 15555399000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.117461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1040267 # number of overall misses +system.cpu.icache.overall_misses::0 1040224 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1040267 # number of overall misses -system.cpu.icache.overall_mshr_hits 47648 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11850308500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.112080 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1040224 # number of overall misses +system.cpu.icache.overall_mshr_hits 47681 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11849289500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.112077 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 992619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 992543 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 991921 # number of replacements -system.cpu.icache.sampled_refs 992432 # Sample count of references to valid blocks. +system.cpu.icache.replacements 991845 # number of replacements +system.cpu.icache.sampled_refs 992356 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.811601 # Cycle average of tags in use -system.cpu.icache.total_refs 7816050 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 509.810451 # Cycle average of tags in use +system.cpu.icache.total_refs 7815697 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 24432989000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 92 # number of writebacks -system.cpu.idleCycles 34355081 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9120774 # Number of branches executed -system.cpu.iew.EXEC:nop 3587033 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.456767 # Inst execution rate -system.cpu.iew.EXEC:refs 16683612 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6610329 # Number of stores executed +system.cpu.icache.writebacks 176 # number of writebacks +system.cpu.idleCycles 34353421 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9120660 # Number of branches executed +system.cpu.iew.EXEC:nop 3587020 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.456799 # Inst execution rate +system.cpu.iew.EXEC:refs 16683854 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6610322 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 35257849 # num instructions consuming a value -system.cpu.iew.WB:count 56697227 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.757274 # average fanout of values written-back +system.cpu.iew.WB:consumers 35263910 # num instructions consuming a value +system.cpu.iew.WB:count 56698677 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.757187 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26699852 # num instructions producing a value -system.cpu.iew.WB:rate 0.453208 # insts written-back per cycle -system.cpu.iew.WB:sent 56799146 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 837773 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9250897 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 10628246 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1790214 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 887997 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 6943382 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65075490 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10073283 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 520965 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57142461 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 61275 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26701367 # num instructions producing a value +system.cpu.iew.WB:rate 0.453241 # insts written-back per cycle +system.cpu.iew.WB:sent 56800727 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 837733 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9250224 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 10628233 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1789856 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 887489 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6943615 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65074740 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10073532 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 521272 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57143754 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61252 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 11738 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1515496 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 557834 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 11749 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1515320 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 557849 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 132328 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 438613 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 9607 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 132030 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 438592 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 9600 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 42661 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 17611 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1521011 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 554299 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 42661 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 406369 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 431404 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 74886349 # number of integer regfile reads -system.cpu.int_regfile_writes 40928930 # number of integer regfile writes -system.cpu.ipc 0.424064 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.424064 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 42579 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 17615 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1521167 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 554622 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 42579 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 406353 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 431380 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 74888686 # number of integer regfile reads +system.cpu.int_regfile_writes 40930439 # number of integer regfile writes +system.cpu.ipc 0.424082 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.424082 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39527901 68.55% 68.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62346 0.11% 68.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39529083 68.55% 68.56% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62345 0.11% 68.67% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.71% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.71% # Type of FU issued @@ -415,15 +415,15 @@ system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.72% system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.72% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.72% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10424527 18.08% 86.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659257 11.55% 98.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 952873 1.65% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10424979 18.08% 86.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659276 11.55% 98.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 952821 1.65% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 57663428 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 432905 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007507 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 57665028 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 432817 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007506 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 49058 11.33% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 49052 11.33% 11.33% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.33% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.33% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.33% # attempts to use FU when none available @@ -452,51 +452,51 @@ system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.33% # system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.33% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.33% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 267419 61.77% 73.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 116428 26.89% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 267357 61.77% 73.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 116408 26.90% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 90747041 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635430 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200309 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 90742716 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635478 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200410 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 62366198 68.73% 68.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 14061379 15.50% 84.22% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 6226874 6.86% 91.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 3821617 4.21% 95.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2539194 2.80% 98.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1091409 1.20% 99.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 462366 0.51% 99.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 128599 0.14% 99.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 49405 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 62361590 68.72% 68.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 14062254 15.50% 84.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 6225923 6.86% 91.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 3822183 4.21% 95.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2538846 2.80% 98.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1090826 1.20% 99.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 462139 0.51% 99.80% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 129609 0.14% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 49346 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 90747041 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.460931 # Inst issue rate -system.cpu.iq.fp_alu_accesses 341243 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 667907 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 325691 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 334133 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 57747809 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 205867710 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 56371536 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 69251365 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 59448706 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 57663428 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2039751 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8060465 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 28817 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1372188 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4168617 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 90742716 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.460966 # Inst issue rate +system.cpu.iq.fp_alu_accesses 341264 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 667947 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 325705 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 334327 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 57749300 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 205866504 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 56372972 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 69249578 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 59448335 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 57665028 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2039385 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8059661 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 28864 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1371832 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4166065 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1294583 # ITB accesses -system.cpu.itb.fetch_acv 923 # ITB acv -system.cpu.itb.fetch_hits 1255493 # ITB hits -system.cpu.itb.fetch_misses 39090 # ITB misses +system.cpu.itb.fetch_accesses 1294620 # ITB accesses +system.cpu.itb.fetch_acv 913 # ITB acv +system.cpu.itb.fetch_hits 1255661 # ITB hits +system.cpu.itb.fetch_misses 38959 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -512,8 +512,8 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175591 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175578 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed @@ -521,42 +521,42 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192561 # number of callpals executed +system.cpu.kern.callpal::total 192547 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211718 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6427 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74916 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 238 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1890 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105896 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182940 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73549 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 238 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73550 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149227 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1827171336500 97.88% 97.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 97547000 0.01% 97.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 392033000 0.02% 97.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 39041048500 2.09% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1866701965000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981753 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211704 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6424 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74914 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 239 0.13% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105885 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182927 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73547 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 239 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73548 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149223 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1826194216500 97.88% 97.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 97924500 0.01% 97.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 391796500 0.02% 97.91% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 39039837500 2.09% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865723775000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694549 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694603 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.mode_good::kernel 1906 system.cpu.kern.mode_good::user 1736 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5959 # number of protection mode switches system.cpu.kern.mode_switch::user 1736 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2107 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.320013 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::idle 2104 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.319852 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080683 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400697 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 30086574000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 3015068000 0.16% 1.77% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1833600315000 98.23% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080798 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.400651 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 30091122000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 3014546000 0.16% 1.77% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832618099000 98.23% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed @@ -589,37 +589,37 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3018201 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2591237 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 10628246 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6943382 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1993439 # number of misc regfile reads -system.cpu.misc_regfile_writes 949389 # number of misc regfile writes -system.cpu.numCycles 125102122 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 3018997 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2591949 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 10628233 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6943615 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1993395 # number of misc regfile reads +system.cpu.misc_regfile_writes 949366 # number of misc regfile writes +system.cpu.numCycles 125096137 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 13297534 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38227478 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1065628 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39060011 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1661101 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 58596 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 82213921 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 67573183 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 45293711 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12514369 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1515496 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4654173 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7066231 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 474968 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 81738953 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 19705456 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1694142 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 11744700 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 247271 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 152916375 # The number of ROB reads -system.cpu.rob.rob_writes 131403689 # The number of ROB writes -system.cpu.timesIdled 1310957 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 13296621 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38227330 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1065712 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39057588 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1661249 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 58583 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 82211156 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 67570562 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 45292482 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12512523 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1515320 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 4654421 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7065150 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 475144 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 81736012 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 19706241 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1694164 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 11744747 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 247277 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 152910637 # The number of ROB reads +system.cpu.rob.rob_writes 131402179 # The number of ROB writes +system.cpu.timesIdled 1310794 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -650,37 +650,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137707.205574 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137705.665335 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85703.600260 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5722009806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85702.060021 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5721945806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3561155998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561091998 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6170.205040 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6170.968690 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64639068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64647068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137614.087573 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137612.553721 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85610.497208 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85608.963355 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5741947804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5741883804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -688,7 +688,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3572097996 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572033996 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -696,20 +696,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.081528 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.304443 # Average occupied blocks per context +system.iocache.occ_%::1 0.081046 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.296738 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137614.087573 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137612.553721 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85610.497208 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85608.963355 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5741947804 # number of overall miss cycles +system.iocache.overall_miss_latency 5741883804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -717,7 +717,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3572097996 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572033996 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -727,145 +727,145 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.304443 # Cycle average of tags in use +system.iocache.tagsinuse 1.296738 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1711281262000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300850 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300850 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52488.966283 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300822 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300822 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52489.461538 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40339.814538 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 183845 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183845 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6141471500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.388915 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 117005 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 117005 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4719960000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.388915 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40340.521368 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 183822 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183822 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6141267000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.388934 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 117000 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 117000 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4719841000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.388934 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 117005 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2092533 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2092533 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52046.060634 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 117000 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2092337 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2092337 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52046.096131 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40015.025123 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40015.012554 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1785047 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1785047 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16003435000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.146944 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 307486 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307486 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1784860 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1784860 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16002977500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.146954 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 307477 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307477 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12304020000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146944 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12303656000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146953 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307485 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 810593000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_misses 307476 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810924000 # number of ReadReq MSHR uncacheable cycles system.l2c.SCUpgradeReq_accesses::0 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.UpgradeReq_accesses::0 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 21400 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::0 22 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 22928.571429 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 44000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 10 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10 # number of UpgradeReq hits +system.l2c.UpgradeReq_avg_mshr_miss_latency 44285.714286 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 8 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits system.l2c.UpgradeReq_miss_latency 321000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.600000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 660000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.600000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.636364 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 620000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.636364 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1115666998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 832856 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 832856 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 832856 # number of Writeback hits -system.l2c.Writeback_hits::total 832856 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1115890498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 832911 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 832911 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 832911 # number of Writeback hits +system.l2c.Writeback_hits::total 832911 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.629154 # Average number of references to valid blocks. +system.l2c.avg_refs 5.628523 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2393383 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2393159 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2393383 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52168.141374 # average overall miss latency +system.l2c.demand_accesses::total 2393159 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52168.302405 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40104.548988 # average overall mshr miss latency -system.l2c.demand_hits::0 1968892 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40104.733837 # average overall mshr miss latency +system.l2c.demand_hits::0 1968682 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1968892 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22144906500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.177360 # miss rate for demand accesses +system.l2c.demand_hits::total 1968682 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22144244500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.177371 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 424491 # number of demand (read+write) misses +system.l2c.demand_misses::0 424477 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 424491 # number of demand (read+write) misses +system.l2c.demand_misses::total 424477 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17023980000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.177360 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 17023497000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.177371 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 424490 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 424476 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.186942 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.344679 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 12251.423039 # Average occupied blocks per context -system.l2c.occ_blocks::1 22588.894949 # Average occupied blocks per context -system.l2c.overall_accesses::0 2393383 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.186906 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.344678 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 12249.050591 # Average occupied blocks per context +system.l2c.occ_blocks::1 22588.829074 # Average occupied blocks per context +system.l2c.overall_accesses::0 2393159 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2393383 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52168.141374 # average overall miss latency +system.l2c.overall_accesses::total 2393159 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52168.302405 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40104.548988 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40104.733837 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1968892 # number of overall hits +system.l2c.overall_hits::0 1968682 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1968892 # number of overall hits -system.l2c.overall_miss_latency 22144906500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.177360 # miss rate for overall accesses +system.l2c.overall_hits::total 1968682 # number of overall hits +system.l2c.overall_miss_latency 22144244500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.177371 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 424491 # number of overall misses +system.l2c.overall_misses::0 424477 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 424491 # number of overall misses +system.l2c.overall_misses::total 424477 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17023980000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.177360 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 17023497000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.177371 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 424490 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926259998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 424476 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926814498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 390992 # number of replacements -system.l2c.sampled_refs 423734 # Sample count of references to valid blocks. +system.l2c.replacements 390976 # number of replacements +system.l2c.sampled_refs 423725 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 34840.317988 # Cycle average of tags in use -system.l2c.total_refs 2385264 # Total number of references to valid blocks. +system.l2c.tagsinuse 34837.879666 # Cycle average of tags in use +system.l2c.total_refs 2384946 # Total number of references to valid blocks. system.l2c.warmup_cycle 5637119000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 117628 # number of writebacks +system.l2c.writebacks 117616 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post From db350536555d7509b703b0707141e3f677645df0 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 17 Mar 2011 19:20:19 -0500 Subject: [PATCH 04/18] ARM: Previous change didn't end up setting instFlags, this does. --- src/arch/arm/isa/insts/str.isa | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index f661961f7..e5d47c28f 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -222,7 +222,6 @@ let {{ decConstBase = 'StoreExImm' basePrefix = 'MemoryExImm' nameFunc = staticmethod(storeImmClassName) - instFlags = ['IsStoreConditional'] def __init__(self, *args, **kargs): super(StoreImmEx, self).__init__(*args, **kargs) @@ -302,7 +301,6 @@ let {{ decConstBase = 'StoreExDImm' basePrefix = 'MemoryExDImm' nameFunc = staticmethod(storeDoubleImmClassName) - instFlags = ['IsStoreConditional'] def __init__(self, *args, **kargs): super(StoreDoubleImmEx, self).__init__(*args, **kargs) @@ -370,10 +368,14 @@ let {{ buildDoubleStores("strd") - StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit() - StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit() - StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit() - StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit() + StoreImmEx("strex", False, True, False, size=4, flavor="exclusive", + instFlags = ['IsStoreConditional']).emit() + StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive", + instFlags = ['IsStoreConditional']).emit() + StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive", + instFlags = ['IsStoreConditional']).emit() + StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive", + instFlags = ['IsStoreConditional']).emit() StoreImm("vstr", False, True, False, size=4, flavor="fp").emit() StoreImm("vstr", False, False, False, size=4, flavor="fp").emit() From 30143baf7e35a73acaff1d02cf71278248a86515 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 17 Mar 2011 19:20:19 -0500 Subject: [PATCH 05/18] O3: Cleanup the commitInfo comm struct. Get rid of unused members and use base types rather than derrived values where possible to limit amount of state. --- src/cpu/o3/comm.hh | 57 ++++++++++++++++++++++++++++----------- src/cpu/o3/commit.hh | 3 ++- src/cpu/o3/commit_impl.hh | 28 +++++++++++-------- src/cpu/o3/fetch_impl.hh | 7 ++--- src/cpu/o3/iew_impl.hh | 6 ++--- 5 files changed, 64 insertions(+), 37 deletions(-) diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh index 897807fdb..840dde9ea 100644 --- a/src/cpu/o3/comm.hh +++ b/src/cpu/o3/comm.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2004-2006 The Regents of The University of Michigan * All rights reserved. * @@ -123,7 +135,6 @@ struct TimeBufStruct { bool branchTaken; Addr mispredPC; TheISA::PCState nextPC; - unsigned branchCount; }; @@ -151,29 +162,45 @@ struct TimeBufStruct { iewComm iewInfo[Impl::MaxThreads]; struct commitComm { - bool usedROB; - unsigned freeROBEntries; - bool emptyROB; + /////////////// For Decode, IEW, Rename, Fetch /////////// bool squash; bool robSquashing; - bool branchMispredict; - DynInstPtr mispredictInst; - bool branchTaken; - Addr mispredPC; - TheISA::PCState pc; - + ////////// For Fetch & IEW ///////////// // Represents the instruction that has either been retired or // squashed. Similar to having a single bus that broadcasts the // retired or squashed sequence number. InstSeqNum doneSeqNum; - //Just in case we want to do a commit/squash on a cycle - //(necessary for multiple ROBs?) - bool commitInsts; - InstSeqNum squashSeqNum; + ////////////// For Rename ///////////////// + // Rename should re-read number of free rob entries + bool usedROB; + // Notify Rename that the ROB is empty + bool emptyROB; + // Tell Rename how many free entries it has in the ROB + unsigned freeROBEntries; + + ///////////// For Fetch ////////////////// + // Provide fetch the instruction that mispredicted, if this + // pointer is not-null a misprediction occured + DynInstPtr mispredictInst; + // Was the branch taken or not + bool branchTaken; + // The pc of the next instruction to execute. This is the next + // instruction for a branch mispredict, but the same instruction for + // order violation and the like + TheISA::PCState pc; + + // Instruction that caused the a non-mispredict squash + DynInstPtr squashInst; + // If an interrupt is pending and fetch should stall + bool interruptPending; + // If the interrupt ended up being cleared before being handled + bool clearInterrupt; + + //////////// For IEW ////////////////// // Communication specifically to the IQ to tell the IQ that it can // schedule a non-speculative instruction. InstSeqNum nonSpecSeqNum; @@ -182,8 +209,6 @@ struct TimeBufStruct { bool uncached; DynInstPtr uncachedLoad; - bool interruptPending; - bool clearInterrupt; }; commitComm commitInfo[Impl::MaxThreads]; diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 047e29f5d..ff7b53440 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -262,7 +262,8 @@ class DefaultCommit * instructions instead of the current instruction and doesn't * clean up various status bits about traps/tc writes pending. */ - void squashAfter(ThreadID tid, uint64_t squash_after_seq_num); + void squashAfter(ThreadID tid, DynInstPtr &head_inst, + uint64_t squash_after_seq_num); #if FULL_SYSTEM /** Handles processing an interrupt. */ diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 104e7fb58..8c651e203 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -541,8 +541,8 @@ DefaultCommit::squashAll(ThreadID tid) // the ROB is in the process of squashing. toIEW->commitInfo[tid].robSquashing = true; - toIEW->commitInfo[tid].branchMispredict = false; toIEW->commitInfo[tid].mispredictInst = NULL; + toIEW->commitInfo[tid].squashInst = NULL; toIEW->commitInfo[tid].pc = pc[tid]; } @@ -584,7 +584,8 @@ DefaultCommit::squashFromTC(ThreadID tid) template void -DefaultCommit::squashAfter(ThreadID tid, uint64_t squash_after_seq_num) +DefaultCommit::squashAfter(ThreadID tid, DynInstPtr &head_inst, + uint64_t squash_after_seq_num) { youngestSeqNum[tid] = squash_after_seq_num; @@ -594,6 +595,7 @@ DefaultCommit::squashAfter(ThreadID tid, uint64_t squash_after_seq_num) // Send back the sequence number of the squashed instruction. toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; + toIEW->commitInfo[tid].squashInst = head_inst; // Send back the squash signal to tell stages that they should squash. toIEW->commitInfo[tid].squash = true; @@ -601,7 +603,7 @@ DefaultCommit::squashAfter(ThreadID tid, uint64_t squash_after_seq_num) // the ROB is in the process of squashing. toIEW->commitInfo[tid].robSquashing = true; - toIEW->commitInfo[tid].branchMispredict = false; + toIEW->commitInfo[tid].mispredictInst = NULL; toIEW->commitInfo[tid].pc = pc[tid]; DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", @@ -801,10 +803,17 @@ DefaultCommit::commit() commitStatus[tid] != TrapPending && fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { - DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", + if (fromIEW->mispredictInst[tid]) { + DPRINTF(Commit, + "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", tid, - fromIEW->mispredPC[tid], + fromIEW->mispredictInst[tid]->instAddr(), fromIEW->squashedSeqNum[tid]); + } else { + DPRINTF(Commit, + "[tid:%i]: Squashing due to order violation [sn:%i]\n", + tid, fromIEW->squashedSeqNum[tid]); + } DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", tid, @@ -835,18 +844,15 @@ DefaultCommit::commit() // the ROB is in the process of squashing. toIEW->commitInfo[tid].robSquashing = true; - toIEW->commitInfo[tid].branchMispredict = - fromIEW->branchMispredict[tid]; toIEW->commitInfo[tid].mispredictInst = fromIEW->mispredictInst[tid]; toIEW->commitInfo[tid].branchTaken = fromIEW->branchTaken[tid]; + toIEW->commitInfo[tid].squashInst = NULL; toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; - toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; - - if (toIEW->commitInfo[tid].branchMispredict) { + if (toIEW->commitInfo[tid].mispredictInst) { ++branchMispredicts; } } @@ -988,7 +994,7 @@ DefaultCommit::commitInsts() // If this is an instruction that doesn't play nicely with // others squash everything and restart fetch if (head_inst->isSquashAfter()) - squashAfter(tid, head_inst->seqNum); + squashAfter(tid, head_inst, head_inst->seqNum); int count = 0; Addr oldpc; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 3092bd937..5f9be039f 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -934,15 +934,12 @@ DefaultFetch::checkSignalsAndUpdate(ThreadID tid) // In any case, squash. squash(fromCommit->commitInfo[tid].pc, fromCommit->commitInfo[tid].doneSeqNum, - tid); + fromCommit->commitInfo[tid].squashInst, tid); // If it was a branch mispredict on a control instruction, update the // branch predictor with that instruction, otherwise just kill the // invalid state we generated in after sequence number - assert(!fromCommit->commitInfo[tid].branchMispredict || - fromCommit->commitInfo[tid].mispredictInst); - - if (fromCommit->commitInfo[tid].branchMispredict && + if (fromCommit->commitInfo[tid].mispredictInst && fromCommit->commitInfo[tid].mispredictInst->isControl()) { branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, fromCommit->commitInfo[tid].pc, diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index dff287ff5..8bf3c56f4 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -456,8 +456,6 @@ DefaultIEW::squashDueToBranch(DynInstPtr &inst, ThreadID tid) inst->seqNum < toCommit->squashedSeqNum[tid]) { toCommit->squash[tid] = true; toCommit->squashedSeqNum[tid] = inst->seqNum; - toCommit->mispredPC[tid] = inst->instAddr(); - toCommit->branchMispredict[tid] = true; toCommit->branchTaken[tid] = inst->pcState().branching(); TheISA::PCState pc = inst->pcState(); @@ -486,7 +484,7 @@ DefaultIEW::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) TheISA::PCState pc = inst->pcState(); TheISA::advancePC(pc, inst->staticInst); toCommit->pc[tid] = pc; - toCommit->branchMispredict[tid] = false; + toCommit->mispredictInst[tid] = NULL; toCommit->includeSquashInst[tid] = false; @@ -506,7 +504,7 @@ DefaultIEW::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) toCommit->squashedSeqNum[tid] = inst->seqNum; toCommit->pc[tid] = inst->pcState(); - toCommit->branchMispredict[tid] = false; + toCommit->mispredictInst[tid] = NULL; // Must include the broadcasted SN in the squash. toCommit->includeSquashInst[tid] = true; From 799c3da8d0086bfdfbae532e05018828387e4497 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 17 Mar 2011 19:20:19 -0500 Subject: [PATCH 06/18] O3: Send instruction back to fetch on squash to seed predecoder correctly. --- src/arch/alpha/predecoder.hh | 6 ++++++ src/arch/arm/predecoder.hh | 6 ++++++ src/arch/mips/predecoder.hh | 6 ++++++ src/arch/power/predecoder.hh | 6 ++++++ src/arch/sparc/predecoder.hh | 7 +++++++ src/arch/x86/predecoder.hh | 6 ++++++ src/cpu/o3/cpu.cc | 5 +++-- src/cpu/o3/fetch.hh | 4 ++-- src/cpu/o3/fetch_impl.hh | 5 ++++- src/kern/linux/events.cc | 12 ++++++++++++ 10 files changed, 58 insertions(+), 5 deletions(-) diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh index a8788051f..2f8c4c2ef 100644 --- a/src/arch/alpha/predecoder.hh +++ b/src/arch/alpha/predecoder.hh @@ -76,6 +76,12 @@ class Predecoder emiIsReady = false; } + void + reset(const ExtMachInst &old_emi) + { + reset(); + } + // Use this to give data to the predecoder. This should be used // when there is control flow. void diff --git a/src/arch/arm/predecoder.hh b/src/arch/arm/predecoder.hh index a99e38ce7..511bc29bc 100644 --- a/src/arch/arm/predecoder.hh +++ b/src/arch/arm/predecoder.hh @@ -83,6 +83,12 @@ namespace ArmISA predAddrValid = false; } + void reset(const ExtMachInst &old_emi) + { + reset(); + itstate = old_emi.newItstate; + } + Predecoder(ThreadContext * _tc) : tc(_tc), data(0) { diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh index 4220b768c..110493cc5 100644 --- a/src/arch/mips/predecoder.hh +++ b/src/arch/mips/predecoder.hh @@ -75,6 +75,12 @@ class Predecoder emiIsReady = false; } + void + reset(const ExtMachInst &old_emi) + { + reset(); + } + //Use this to give data to the predecoder. This should be used //when there is control flow. void diff --git a/src/arch/power/predecoder.hh b/src/arch/power/predecoder.hh index 8b1089095..c10bc51bf 100644 --- a/src/arch/power/predecoder.hh +++ b/src/arch/power/predecoder.hh @@ -82,6 +82,12 @@ class Predecoder emiIsReady = false; } + void + reset(const ExtMachInst &old_emi) + { + reset(); + } + // Use this to give data to the predecoder. This should be used // when there is control flow. void diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index 670c547d0..082adeb72 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -68,12 +68,19 @@ class Predecoder } void process() {} + void reset() { emiIsReady = false; } + void + reset(const ExtMachInst &old_emi) + { + reset(); + } + // Use this to give data to the predecoder. This should be used // when there is control flow. void diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh index 5c67e28e1..790453b98 100644 --- a/src/arch/x86/predecoder.hh +++ b/src/arch/x86/predecoder.hh @@ -174,6 +174,12 @@ namespace X86ISA state = ResetState; } + void + reset(const ExtMachInst &old_emi) + { + reset(); + } + ThreadContext * getTC() { return tc; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 2d3bc3f72..4088f2399 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -808,8 +808,9 @@ FullO3CPU::removeThread(ThreadID tid) } // Squash Throughout Pipeline - InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; - fetch.squash(0, squash_seq_num, tid); + DynInstPtr inst = commit.rob->readHeadInst(tid); + InstSeqNum squash_seq_num = inst->seqNum; + fetch.squash(0, squash_seq_num, inst, tid); decode.squash(tid); rename.squash(squash_seq_num, tid); iew.squash(tid); diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index c51658104..4a4ac0902 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -312,8 +312,8 @@ class DefaultFetch * remove any instructions that are not in the ROB. The source of this * squash should be the commit stage. */ - void squash(const TheISA::PCState &newPC, - const InstSeqNum &seq_num, ThreadID tid); + void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num, + DynInstPtr &squashInst, ThreadID tid); /** Ticks the fetch stage, processing all inputs signals and fetching * as many instructions as possible. diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 5f9be039f..6c1ac456d 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -815,11 +815,14 @@ DefaultFetch::updateFetchStatus() template void DefaultFetch::squash(const TheISA::PCState &newPC, - const InstSeqNum &seq_num, ThreadID tid) + const InstSeqNum &seq_num, DynInstPtr &squashInst, + ThreadID tid) { DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); doSquash(newPC, tid); + if (squashInst) + predecoder.reset(squashInst->staticInst->machInst); // Tell the CPU to remove any instructions that are not in the ROB. cpu->removeInstsNotInROB(tid); diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc index f619dd11b..60aa857ac 100644 --- a/src/kern/linux/events.cc +++ b/src/kern/linux/events.cc @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2004-2006 The Regents of The University of Michigan * All rights reserved. * From e65f480d62e0112e89af6130e2f2024d89417df0 Mon Sep 17 00:00:00 2001 From: Matt Horsnell Date: Thu, 17 Mar 2011 19:20:19 -0500 Subject: [PATCH 07/18] ARM: Rename registers used as temporary state by microops. --- src/arch/arm/isa/insts/macromem.isa | 32 ++++++++++++++--------------- src/arch/arm/isa/operands.isa | 6 +++--- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 33d57a60b..0e3bcc648 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -51,7 +51,7 @@ let {{ microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', 'MicroMemOp', {'memacc_code': microLdrUopCode, - 'ea_code': 'EA = Rb + (up ? imm : -imm);', + 'ea_code': 'EA = URb + (up ? imm : -imm);', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -60,7 +60,7 @@ let {{ 'MicroMemOp', {'memacc_code': microLdrFpUopCode, 'ea_code': vfpEnabledCheckCode + - 'EA = Rb + (up ? imm : -imm);', + 'EA = URb + (up ? imm : -imm);', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -69,7 +69,7 @@ let {{ 'MicroMemOp', {'memacc_code': microLdrFpUopCode, 'ea_code': vfpEnabledCheckCode + ''' - EA = Rb + (up ? imm : -imm) + + EA = URb + (up ? imm : -imm) + (((CPSR)Cpsr).e ? 4 : 0); ''', 'predicate_test': predicateTest}, @@ -80,7 +80,7 @@ let {{ 'MicroMemOp', {'memacc_code': microLdrFpUopCode, 'ea_code': vfpEnabledCheckCode + ''' - EA = Rb + (up ? imm : -imm) - + EA = URb + (up ? imm : -imm) - (((CPSR)Cpsr).e ? 4 : 0); ''', 'predicate_test': predicateTest}, @@ -101,16 +101,16 @@ let {{ 'MicroMemOp', {'memacc_code': microLdrRetUopCode, 'ea_code': - 'EA = Rb + (up ? imm : -imm);', + 'EA = URb + (up ? imm : -imm);', 'predicate_test': condPredicateTest}, ['IsMicroop','IsNonSpeculative','IsSerializeAfter']) - microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);" + microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);" microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', 'MicroMemOp', {'memacc_code': microStrUopCode, 'postacc_code': "", - 'ea_code': 'EA = Rb + (up ? imm : -imm);', + 'ea_code': 'EA = URb + (up ? imm : -imm);', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -120,7 +120,7 @@ let {{ {'memacc_code': microStrFpUopCode, 'postacc_code': "", 'ea_code': vfpEnabledCheckCode + - 'EA = Rb + (up ? imm : -imm);', + 'EA = URb + (up ? imm : -imm);', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -130,7 +130,7 @@ let {{ {'memacc_code': microStrFpUopCode, 'postacc_code': "", 'ea_code': vfpEnabledCheckCode + ''' - EA = Rb + (up ? imm : -imm) + + EA = URb + (up ? imm : -imm) + (((CPSR)Cpsr).e ? 4 : 0); ''', 'predicate_test': predicateTest}, @@ -142,7 +142,7 @@ let {{ {'memacc_code': microStrFpUopCode, 'postacc_code': "", 'ea_code': vfpEnabledCheckCode + ''' - EA = Rb + (up ? imm : -imm) - + EA = URb + (up ? imm : -imm) - (((CPSR)Cpsr).e ? 4 : 0); ''', 'predicate_test': predicateTest}, @@ -170,7 +170,7 @@ let {{ let {{ exec_output = header_output = '' - eaCode = 'EA = Ra + imm;' + eaCode = 'EA = URa + imm;' for size in (1, 2, 3, 4, 6, 8, 12, 16): # Set up the memory access. @@ -572,14 +572,14 @@ let {{ let {{ microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', 'MicroIntImmOp', - {'code': 'Ra = Rb + imm;', + {'code': 'URa = URb + imm;', 'predicate_test': predicateTest}, ['IsMicroop']) microAddUopIop = InstObjParams('add_uop', 'MicroAddUop', 'MicroIntRegOp', {'code': - '''Ra = Rb + shift_rm_imm(Rc, shiftAmt, + '''URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, CondCodes<29:>); ''', @@ -588,14 +588,14 @@ let {{ microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', 'MicroIntImmOp', - {'code': 'Ra = Rb - imm;', + {'code': 'URa = URb - imm;', 'predicate_test': predicateTest}, ['IsMicroop']) microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop', 'MicroIntRegOp', {'code': - '''Ra = Rb - shift_rm_imm(Rc, shiftAmt, + '''URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, CondCodes<29:>); ''', @@ -604,7 +604,7 @@ let {{ microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov', 'MicroIntMov', - {'code': 'IWRa = Rb;', + {'code': 'IWRa = URb;', 'predicate_test': predicateTest}, ['IsMicroop']) diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index f403f9372..7b014acd0 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -228,11 +228,11 @@ def operands {{ 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'), #Register fields for microops - 'Ra' : intReg('ura'), + 'URa' : intReg('ura'), 'IWRa' : intRegIWPC('ura'), 'Fa' : floatReg('ura'), - 'Rb' : intReg('urb'), - 'Rc' : intReg('urc'), + 'URb' : intReg('urb'), + 'URc' : intReg('urc'), #Memory Operand 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal), From 031f396c71e750fede19651ba3a14e262a87e117 Mon Sep 17 00:00:00 2001 From: Matt Horsnell Date: Thu, 17 Mar 2011 19:20:19 -0500 Subject: [PATCH 08/18] ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. --- src/arch/arm/insts/macromem.cc | 9 +++++++ src/arch/arm/insts/macromem.hh | 21 +++++++++++++++ src/arch/arm/insts/mem.hh | 8 ++++-- src/arch/arm/intregs.hh | 2 ++ src/arch/arm/isa/insts/ldr.isa | 25 +++++++----------- src/arch/arm/isa/insts/macromem.isa | 31 +++++++++++++++++++--- src/arch/arm/isa/insts/mem.isa | 25 +++++++++++++++--- src/arch/arm/isa/templates/macromem.isa | 35 +++++++++++++++++++++++++ src/arch/arm/isa/templates/mem.isa | 24 ++++++++++------- 9 files changed, 146 insertions(+), 34 deletions(-) diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index 2a45cf2e6..c03b7ccc1 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -895,6 +895,15 @@ MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const return ss.str(); } +std::string +MicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + ss << "[PC,CPSR]"; + return ss.str(); +} + std::string MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const { diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh index 1a2db8b9a..4933a1e7c 100644 --- a/src/arch/arm/insts/macromem.hh +++ b/src/arch/arm/insts/macromem.hh @@ -134,6 +134,27 @@ class MicroNeonMixLaneOp : public MicroNeonMixOp { } }; + +/** + * Microops of the form + * PC = IntRegA + * CPSR = IntRegB + */ +class MicroSetPCCPSR : public MicroOp +{ + protected: + IntRegIndex ura, urb, urc; + + MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass, + IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc) + : MicroOp(mnem, machInst, __opClass), + ura(_ura), urb(_urb), urc(_urc) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + /** * Microops of the form IntRegA = IntRegB */ diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh index a4fc62603..324d86fed 100644 --- a/src/arch/arm/insts/mem.hh +++ b/src/arch/arm/insts/mem.hh @@ -97,14 +97,18 @@ class RfeOp : public MightBeMicro IntRegIndex base; AddrMode mode; bool wb; - static const unsigned numMicroops = 2; + IntRegIndex ura, urb, urc; + static const unsigned numMicroops = 3; StaticInstPtr *uops; RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _base, AddrMode _mode, bool _wb) : MightBeMicro(mnem, _machInst, __opClass), - base(_base), mode(_mode), wb(_wb), uops(NULL) + base(_base), mode(_mode), wb(_wb), + ura(INTREG_UREG0), urb(INTREG_UREG1), + urc(INTREG_UREG2), + uops(NULL) {} virtual diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh index 4b2cc560d..2cbed6c59 100644 --- a/src/arch/arm/intregs.hh +++ b/src/arch/arm/intregs.hh @@ -110,6 +110,8 @@ enum IntRegIndex INTREG_ZERO, // Dummy zero reg since there has to be one. INTREG_UREG0, + INTREG_UREG1, + INTREG_UREG2, INTREG_CONDCODES, INTREG_FPCONDCODES, diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index c60a91a50..2e45f2875 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -67,7 +67,7 @@ let {{ self.memFlags = ["ArmISA::TLB::MustBeOne"] self.codeBlobs = {"postacc_code" : ""} - def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = []): + def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = [], pcDecl = None): global header_output, decoder_output, exec_output @@ -76,7 +76,8 @@ let {{ (newHeader, newDecoder, newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, - self.memFlags, instFlags, base, wbDecl) + self.memFlags, instFlags, base, + wbDecl, pcDecl) header_output += newHeader decoder_output += newDecoder @@ -104,26 +105,18 @@ let {{ wbDiff = 8 accCode = ''' CPSR cpsr = Cpsr; - SCTLR sctlr = Sctlr; - // Use the version of NPC that gets set before NextThumb - pNPC = cSwap(Mem.ud, cpsr.e); - uint32_t tempSpsr = cSwap(Mem.ud >> 32, cpsr.e); - uint32_t newCpsr = - cpsrWriteByInstr(cpsr | CondCodes, tempSpsr, - 0xF, true, sctlr.nmfi); - Cpsr = ~CondCodesMask & newCpsr; - NextThumb = ((CPSR)newCpsr).t; - NextJazelle = ((CPSR)newCpsr).j; - ForcedItState = ((((CPSR)tempSpsr).it2 << 2) & 0xFC) - | (((CPSR)tempSpsr).it1 & 0x3); - CondCodes = CondCodesMask & newCpsr; + URc = cpsr | CondCodes; + URa = cSwap(Mem.ud, cpsr.e); + URb = cSwap(Mem.ud >> 32, cpsr.e); ''' self.codeBlobs["memacc_code"] = accCode wbDecl = None + pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);" + if self.writeback: wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff - self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"]) + self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"], pcDecl) class LoadImmInst(LoadInst): def __init__(self, *args, **kargs): diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 0e3bcc648..d6c929353 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -608,23 +608,48 @@ let {{ 'predicate_test': predicateTest}, ['IsMicroop']) + setPCCPSRDecl = ''' + CPSR cpsrOrCondCodes = URc; + SCTLR sctlr = Sctlr; + pNPC = URa; + uint32_t newCpsr = + cpsrWriteByInstr(cpsrOrCondCodes, URb, + 0xF, true, sctlr.nmfi); + Cpsr = ~CondCodesMask & newCpsr; + NextThumb = ((CPSR)newCpsr).t; + NextJazelle = ((CPSR)newCpsr).j; + ForcedItState = ((((CPSR)URb).it2 << 2) & 0xFC) + | (((CPSR)URb).it1 & 0x3); + CondCodes = CondCodesMask & newCpsr; + ''' + + microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR', + 'MicroSetPCCPSR', + {'code': setPCCPSRDecl, + 'predicate_test': predicateTest}, + ['IsMicroop']) + header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \ MicroIntImmDeclare.subst(microSubiUopIop) + \ MicroIntRegDeclare.subst(microAddUopIop) + \ MicroIntRegDeclare.subst(microSubUopIop) + \ - MicroIntMovDeclare.subst(microUopRegMovIop) + MicroIntMovDeclare.subst(microUopRegMovIop) + \ + MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop) decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \ MicroIntImmConstructor.subst(microSubiUopIop) + \ MicroIntRegConstructor.subst(microAddUopIop) + \ MicroIntRegConstructor.subst(microSubUopIop) + \ - MicroIntMovConstructor.subst(microUopRegMovIop) + MicroIntMovConstructor.subst(microUopRegMovIop) + \ + MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop) exec_output = PredOpExecute.subst(microAddiUopIop) + \ PredOpExecute.subst(microSubiUopIop) + \ PredOpExecute.subst(microAddUopIop) + \ PredOpExecute.subst(microSubUopIop) + \ - PredOpExecute.subst(microUopRegMovIop) + PredOpExecute.subst(microUopRegMovIop) + \ + PredOpExecute.subst(microUopSetPCCPSRIop) + }}; let {{ diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa index 507f8cd4b..d0c0f0710 100644 --- a/src/arch/arm/isa/insts/mem.isa +++ b/src/arch/arm/isa/insts/mem.isa @@ -48,7 +48,7 @@ let {{ self.constructTemplate = eval(self.decConstBase + 'Constructor') def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags, - base = 'Memory', wbDecl = None): + base = 'Memory', wbDecl = None, pcDecl = None): # Make sure flags are in lists (convert to lists if not). memFlags = makeList(memFlags) instFlags = makeList(instFlags) @@ -65,12 +65,26 @@ let {{ macroName = Name instFlagsCopy = list(instFlags) codeBlobsCopy = dict(codeBlobs) - if wbDecl is not None: + + use_uops = 0 + if wbDecl is not None or pcDecl is not None: instFlagsCopy.append('IsMicroop') Name = Name + 'Acc' + use_uops = 1 + + use_wb = 0 + use_pc = 0 + if wbDecl is not None: + use_wb = 1 + if pcDecl is not None: + use_pc = 1 + codeBlobsCopy['acc_name'] = Name codeBlobsCopy['wb_decl'] = wbDecl + codeBlobsCopy['pc_decl'] = pcDecl codeBlobsCopy['use_uops'] = 0 + codeBlobsCopy['use_wb'] = 0 + codeBlobsCopy['use_pc'] = 0 iop = InstObjParams(name, Name, base, codeBlobsCopy, instFlagsCopy) @@ -81,11 +95,14 @@ let {{ self.initiateAccTemplate.subst(iop) + \ self.completeAccTemplate.subst(iop) - if wbDecl is not None: + if wbDecl is not None or pcDecl is not None: iop = InstObjParams(name, macroName, base, { "wb_decl" : wbDecl, + "pc_decl" : pcDecl, "acc_name" : Name, - "use_uops" : 1 }, + "use_uops" : use_uops, + "use_pc" : use_pc, + "use_wb" : use_wb }, ['IsMacroop']) header_output += self.declareTemplate.subst(iop) decoder_output += self.constructTemplate.subst(iop) diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa index b7ca7fa48..a7f7f0da8 100644 --- a/src/arch/arm/isa/templates/macromem.isa +++ b/src/arch/arm/isa/templates/macromem.isa @@ -107,6 +107,41 @@ def template MicroNeonMemDeclare {{ }; }}; +//////////////////////////////////////////////////////////////////// +// +// PC = Integer(ura) +// CPSR = Integer(urb) +// + +def template MicroSetPCCPSRDeclare {{ + class %(class_name)s : public %(base_class)s + { + public: + %(class_name)s(ExtMachInst machInst, + IntRegIndex _ura, + IntRegIndex _urb, + IntRegIndex _urc); + %(BasicExecDeclare)s + }; +}}; + +def template MicroSetPCCPSRConstructor {{ + %(class_name)s::%(class_name)s(ExtMachInst machInst, + IntRegIndex _ura, + IntRegIndex _urb, + IntRegIndex _urc) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + _ura, _urb, _urc) + { + %(constructor)s; + if (!(condCode == COND_AL || condCode == COND_UC)) { + for (int x = 0; x < _numDestRegs; x++) { + _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; + } + } + } +}}; + //////////////////////////////////////////////////////////////////// // // Integer = Integer op Integer microops diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index 3d073b322..dcfd47ace 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -917,9 +917,9 @@ def template CompleteAccDeclare {{ def template RfeConstructor {{ inline %(class_name)s::%(class_name)s(ExtMachInst machInst, - uint32_t _base, int _mode, bool _wb) - : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, - (IntRegIndex)_base, (AddrMode)_mode, _wb) + uint32_t _base, int _mode, bool _wb) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + (IntRegIndex)_base, (AddrMode)_mode, _wb) { %(constructor)s; if (!(condCode == COND_AL || condCode == COND_UC)) { @@ -928,12 +928,18 @@ def template RfeConstructor {{ } } #if %(use_uops)d - assert(numMicroops >= 2); - uops = new StaticInstPtr[numMicroops]; - uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb); - uops[0]->setDelayedCommit(); - uops[1] = new %(wb_decl)s; - uops[1]->setLastMicroop(); + uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d]; + int uopIdx = 0; + uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb); + uops[uopIdx]->setDelayedCommit(); +#if %(use_wb)d + uops[++uopIdx] = new %(wb_decl)s; + uops[uopIdx]->setDelayedCommit(); +#endif +#if %(use_pc)d + uops[++uopIdx] = new %(pc_decl)s; +#endif + uops[uopIdx]->setLastMicroop(); #endif } }}; From 845f791f377001bf348d8f99798d4b1b6fb5d581 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 17 Mar 2011 19:20:20 -0500 Subject: [PATCH 09/18] Stats: Update the statistics for rfe patch. --- .../ref/arm/linux/o3-timing/config.ini | 2 +- .../00.gzip/ref/arm/linux/o3-timing/simout | 8 +- .../00.gzip/ref/arm/linux/o3-timing/stats.txt | 32 ++-- .../ref/arm/linux/o3-timing/config.ini | 4 +- .../20.parser/ref/arm/linux/o3-timing/simout | 10 +- .../ref/arm/linux/o3-timing/stats.txt | 150 +++++++++--------- .../ref/arm/linux/o3-timing/config.ini | 2 +- .../40.perlbmk/ref/arm/linux/o3-timing/simout | 8 +- .../ref/arm/linux/o3-timing/stats.txt | 46 +++--- .../00.hello/ref/arm/linux/o3-timing/simout | 8 +- .../ref/arm/linux/o3-timing/stats.txt | 8 +- 11 files changed, 139 insertions(+), 139 deletions(-) diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index b2393d69d..12a85f3ff 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -493,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index 3549187ab..1244f3aca 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 21 2011 14:34:16 -M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch -M5 started Feb 21 2011 14:34:24 +M5 compiled Feb 22 2011 10:22:27 +M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip +M5 started Feb 22 2011 10:22:49 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 70c39bd1c..7e719ad32 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 84615 # Simulator instruction rate (inst/s) -host_mem_usage 256696 # Number of bytes of host memory used -host_seconds 7097.77 # Real time elapsed on the host -host_tick_rate 30571310 # Simulator tick rate (ticks/s) +host_inst_rate 123576 # Simulator instruction rate (inst/s) +host_mem_usage 255024 # Number of bytes of host memory used +host_seconds 4860.01 # Real time elapsed on the host +host_tick_rate 44647688 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 600581343 # Number of instructions simulated sim_seconds 0.216988 # Number of seconds simulated @@ -119,9 +119,9 @@ system.cpu.dcache.tagsinuse 4094.932523 # Cy system.cpu.dcache.total_refs 208054728 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 90723000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 394050 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 84141897 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 763381678 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 172755507 # Number of cycles decode is idle +system.cpu.decode.DECODE:BlockedCycles 84141899 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 763381679 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 172755505 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 145178933 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 17467706 # Number of cycles decode is squashing system.cpu.decode.DECODE:UnblockCycles 13550939 # Number of cycles decode is unblocking @@ -165,8 +165,8 @@ system.cpu.fetch.rateDist::0 271374463 62.66% 62.66% # Nu system.cpu.fetch.rateDist::1 26620223 6.15% 68.81% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 18536414 4.28% 73.09% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 23464508 5.42% 78.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11465886 2.65% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12676535 2.93% 84.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11465885 2.65% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12676536 2.93% 84.08% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 5122176 1.18% 85.26% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 7816549 1.80% 87.07% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 56018228 12.93% 100.00% # Number of instructions fetched each cycle (Total) @@ -492,22 +492,22 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.rename.RENAME:BlockCycles 12394449 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 469246940 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 63310870 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 190431449 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 190431447 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 3181742 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 2146129409 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenameLookups 2146129408 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 749361548 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 579635255 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RenamedOperands 579635256 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 140764920 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 17467706 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 71980154 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 110388312 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 110388313 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 2146129313 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 56304 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:int_rename_lookups 2146129312 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 56306 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 3959 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 128598458 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 3953 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:tempSerializingInsts 3954 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 1130320351 # The number of ROB reads system.cpu.rob.rob_writes 1461345715 # The number of ROB writes system.cpu.timesIdled 36569 # Number of times that the entire CPU went into an idle state and unscheduled itself diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini index 92faf41fb..1a957b9e0 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -493,9 +493,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index 85a6ac5af..3478ca485 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 21 2011 14:34:16 -M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch -M5 started Feb 21 2011 15:43:32 +M5 compiled Feb 22 2011 10:22:27 +M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip +M5 started Feb 22 2011 10:22:49 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -72,4 +72,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 365986074500 because target called exit() +Exiting @ tick 365986112500 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index afae24f2b..d87c32cd3 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,29 +1,29 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 77433 # Simulator instruction rate (inst/s) -host_mem_usage 260740 # Number of bytes of host memory used -host_seconds 7232.86 # Real time elapsed on the host -host_tick_rate 50600448 # Simulator tick rate (ticks/s) +host_inst_rate 97202 # Simulator instruction rate (inst/s) +host_mem_usage 259080 # Number of bytes of host memory used +host_seconds 5761.84 # Real time elapsed on the host +host_tick_rate 63518944 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 560059971 # Number of instructions simulated sim_seconds 0.365986 # Number of seconds simulated -sim_ticks 365986074500 # Number of ticks simulated +sim_ticks 365986112500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 140387936 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 174401300 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 140387928 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 174400171 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 15511612 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 191766015 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 191766015 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 191749151 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 191749151 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 110089780 # Number of branches committed system.cpu.commit.COM:bw_lim_events 3558142 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 662070266 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 662070279 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::mean 0.847952 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 1.257926 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 343782937 51.93% 51.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 343782950 51.93% 51.93% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::1 194895590 29.44% 81.36% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::2 65587700 9.91% 91.27% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::3 25120372 3.79% 95.06% # Number of insts commited each cycle @@ -35,7 +35,7 @@ system.cpu.commit.COM:committed_per_cycle::8 3558142 0.54% 100.00% system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 662070266 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 662070279 # Number of insts commited each cycle system.cpu.commit.COM:count 561403855 # Number of instructions committed system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -97,7 +97,7 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.992547 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4065.472807 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 4065.472811 # Average occupied blocks per context system.cpu.dcache.overall_accesses 205633216 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 12753.485870 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 8794.286111 # average overall mshr miss latency @@ -115,13 +115,13 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 1169307 # number of replacements system.cpu.dcache.sampled_refs 1173403 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4065.472807 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4065.472811 # Cycle average of tags in use system.cpu.dcache.total_refs 203333005 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 6053772000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1049504 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 23915687 # Number of cycles decode is blocked system.cpu.decode.DECODE:DecodedInsts 1082602718 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 296214320 # Number of cycles decode is idle +system.cpu.decode.DECODE:IdleCycles 296214333 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 338871926 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 65446321 # Number of cycles decode is squashing system.cpu.decode.DECODE:UnblockCycles 3068332 # Number of cycles decode is unblocking @@ -146,23 +146,23 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 191766015 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 122748340 # Number of cache lines fetched -system.cpu.fetch.Cycles 351971872 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 3710699 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Branches 191749151 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 122693966 # Number of cache lines fetched +system.cpu.fetch.Cycles 352026246 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3656325 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 938893733 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 4527385 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 26711690 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.261985 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 122748340 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 140387936 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.282691 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 727516586 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.537241 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.455426 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261962 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 122693966 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 140387928 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.282690 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 727516599 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.537316 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.455394 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 376259318 51.72% 51.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 167730540 23.06% 74.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 376204957 51.71% 51.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 167784914 23.06% 74.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 28515235 3.92% 78.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 34553707 4.75% 83.44% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 26720758 3.67% 87.12% # Number of instructions fetched each cycle (Total) @@ -173,53 +173,53 @@ system.cpu.fetch.rateDist::8 60208180 8.28% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 727516586 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 727516599 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 122748340 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 13369.913613 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 9679.346455 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 122731555 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 224414000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 122693966 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 13369.943402 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 9679.377996 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 122677181 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 224414500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000137 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 16785 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 933 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 153437000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 153437500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000129 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 15852 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7742.827266 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 7739.396947 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 122748340 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 13369.913613 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 9679.346455 # average overall mshr miss latency -system.cpu.icache.demand_hits 122731555 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 224414000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 122693966 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 13369.943402 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 9679.377996 # average overall mshr miss latency +system.cpu.icache.demand_hits 122677181 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 224414500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000137 # miss rate for demand accesses system.cpu.icache.demand_misses 16785 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 933 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 153437000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 153437500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000129 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 15852 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.543111 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1112.290548 # Average occupied blocks per context -system.cpu.icache.overall_accesses 122748340 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 13369.913613 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 9679.346455 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.543041 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1112.147272 # Average occupied blocks per context +system.cpu.icache.overall_accesses 122693966 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 13369.943402 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 9679.377996 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 122731555 # number of overall hits -system.cpu.icache.overall_miss_latency 224414000 # number of overall miss cycles +system.cpu.icache.overall_hits 122677181 # number of overall hits +system.cpu.icache.overall_miss_latency 224414500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000137 # miss rate for overall accesses system.cpu.icache.overall_misses 16785 # number of overall misses system.cpu.icache.overall_mshr_hits 933 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 153437000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 153437500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000129 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 15852 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -227,11 +227,11 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 14002 # number of replacements system.cpu.icache.sampled_refs 15851 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1112.290548 # Cycle average of tags in use -system.cpu.icache.total_refs 122731555 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1112.147272 # Cycle average of tags in use +system.cpu.icache.total_refs 122677181 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 4455564 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 4455627 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 125457274 # Number of branches executed system.cpu.iew.EXEC:nop 13838185 # number of nop insts executed system.cpu.iew.EXEC:rate 0.981178 # Inst execution rate @@ -349,11 +349,11 @@ system.cpu.iq.ISSUE:fu_full::MemRead 5982996 51.74% 53.07% # at system.cpu.iq.ISSUE:fu_full::MemWrite 5427500 46.93% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 727516586 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 727516599 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::mean 1.031184 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.359043 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 340760839 46.84% 46.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 340760852 46.84% 46.84% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::1 195196887 26.83% 73.67% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::2 103112393 14.17% 87.84% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::3 43508042 5.98% 93.82% # Number of insts issued each cycle @@ -365,14 +365,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::8 1771379 0.24% 100.00% # Nu system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 727516586 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 727516599 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.024907 # Inst issue rate system.cpu.iq.fp_alu_accesses 100 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 196 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes system.cpu.iq.int_alu_accesses 761767408 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 2247505915 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 2247505928 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 665966032 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_writes 1323699335 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 946810264 # Number of instructions added to the IQ (excludes non-spec) @@ -414,10 +414,10 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 3705469500 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.343563 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 119513 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 841391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34185.632593 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34185.636939 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.780138 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 726325 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3933604000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 3933604500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.136757 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 115066 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_hits 30 # number of ReadReq MSHR hits @@ -437,10 +437,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 1189254 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34217.201881 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34217.204012 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.097476 # average overall mshr miss latency system.cpu.l2cache.demand_hits 954675 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8026637000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 8026637500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.197249 # miss rate for demand accesses system.cpu.l2cache.demand_misses 234579 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 30 # number of demand (read+write) MSHR hits @@ -452,14 +452,14 @@ system.cpu.l2cache.mshr_cap_events 0 # nu system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.185910 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.449873 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 6091.890422 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14741.450627 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 6091.910767 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14741.440748 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 1189254 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34217.201881 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34217.204012 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.097476 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 954675 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8026637000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 8026637500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.197249 # miss rate for overall accesses system.cpu.l2cache.overall_misses 234579 # number of overall misses system.cpu.l2cache.overall_mshr_hits 30 # number of overall MSHR hits @@ -471,9 +471,9 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 215449 # number of replacements system.cpu.l2cache.sampled_refs 235636 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 20833.341048 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 20833.351516 # Cycle average of tags in use system.cpu.l2cache.total_refs 1493772 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 262779341000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 262779379000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 171632 # number of writebacks system.cpu.memDep0.conflictingLoads 58798533 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 76400324 # Number of conflicting stores. @@ -481,31 +481,31 @@ system.cpu.memDep0.insertedLoads 199993331 # Nu system.cpu.memDep0.insertedStores 140409395 # Number of stores inserted to the mem dependence unit. system.cpu.misc_regfile_reads 1169227072 # number of misc regfile reads system.cpu.misc_regfile_writes 344748 # number of misc regfile writes -system.cpu.numCycles 731972150 # number of cpu cycles simulated +system.cpu.numCycles 731972226 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 7146790 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 435368498 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 5207540 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 311739226 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 311739239 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 9258079 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 25 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 2640447492 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenameLookups 2640393118 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 1043812056 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 713532745 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RenamedOperands 713587119 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 325976886 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 65446321 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 15480980 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 278164244 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 278218618 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 1939 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 2640445553 # Number of integer rename lookups +system.cpu.rename.RENAME:int_rename_lookups 2640391179 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 1726383 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 233275 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 49072391 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 185712 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 1619326892 # The number of ROB reads +system.cpu.rob.rob_reads 1619326905 # The number of ROB reads system.cpu.rob.rob_writes 1987147936 # The number of ROB writes -system.cpu.timesIdled 95874 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 95875 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 548 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 3820d828c..eb78a5974 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -493,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index f9727ee45..cb125c559 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 21 2011 14:34:16 -M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch -M5 started Feb 21 2011 15:06:31 +M5 compiled Feb 22 2011 10:22:27 +M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip +M5 started Feb 22 2011 10:32:06 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 5b889551e..ecc795b7f 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 80651 # Simulator instruction rate (inst/s) -host_mem_usage 263088 # Number of bytes of host memory used -host_seconds 22860.92 # Real time elapsed on the host -host_tick_rate 48422649 # Simulator tick rate (ticks/s) +host_inst_rate 123409 # Simulator instruction rate (inst/s) +host_mem_usage 261412 # Number of bytes of host memory used +host_seconds 14940.26 # Real time elapsed on the host +host_tick_rate 74094191 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1843755906 # Number of instructions simulated sim_seconds 1.106986 # Number of seconds simulated @@ -119,10 +119,10 @@ system.cpu.dcache.tagsinuse 4095.125005 # Cy system.cpu.dcache.total_refs 988465092 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 341948000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 106863 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 223702819 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3748475941 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 853302516 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 949015542 # Number of cycles decode is running +system.cpu.decode.DECODE:BlockedCycles 223702822 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3748475939 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 853302514 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 949015541 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 187283447 # Number of cycles decode is squashing system.cpu.decode.DECODE:UnblockCycles 404118 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses @@ -148,9 +148,9 @@ system.cpu.dtb.write_hits 0 # DT system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 562377080 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 400588374 # Number of cache lines fetched -system.cpu.fetch.Cycles 1002800662 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 1002800660 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 11586077 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2972268197 # Number of instructions fetch has processed +system.cpu.fetch.Insts 2972268195 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 34317 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 86966870 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.254013 # Number of branch fetches per cycle @@ -161,11 +161,11 @@ system.cpu.fetch.rateDist::samples 2213708442 # Nu system.cpu.fetch.rateDist::mean 1.777306 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.798612 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1213776792 54.83% 54.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 388415260 17.55% 72.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1213776794 54.83% 54.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 388415258 17.55% 72.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 93122307 4.21% 76.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48895921 2.21% 78.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 60943546 2.75% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48895922 2.21% 78.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 60943545 2.75% 81.54% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 76981670 3.48% 85.02% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 16173405 0.73% 85.75% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 35829919 1.62% 87.37% # Number of instructions fetched each cycle (Total) @@ -485,7 +485,7 @@ system.cpu.memDep0.conflictingLoads 48375882 # Nu system.cpu.memDep0.conflictingStores 167873780 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 976823889 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 487070109 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 4207984132 # number of misc regfile reads +system.cpu.misc_regfile_reads 4207984130 # number of misc regfile reads system.cpu.misc_regfile_writes 14227476 # number of misc regfile writes system.cpu.numCycles 2213972592 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -493,22 +493,22 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.rename.RENAME:BlockCycles 17658494 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1482327508 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 4825678 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 919120367 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 919120364 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 8406320 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 9255846830 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenameLookups 9255846828 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 3353421825 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2685986513 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RenamedOperands 2685986515 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 880460594 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 187283447 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 23975324 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1203659002 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 1203659004 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 485863672 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 8769983158 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 185210216 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:int_rename_lookups 8769983156 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 185210219 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 19466962 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 226114383 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 13965391 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:skidInsts 226114384 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 13965392 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 4997592808 # The number of ROB reads system.cpu.rob.rob_writes 6212468368 # The number of ROB writes system.cpu.timesIdled 87017 # Number of times that the entire CPU went into an idle state and unscheduled itself diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index 1af21cc60..8bf593f7e 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2011 14:37:21 -M5 revision bc7f8168ee84 7973 default ext/update_regressions.patch qtip tip -M5 started Feb 23 2011 14:37:24 +M5 compiled Feb 22 2011 10:22:27 +M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip +M5 started Feb 22 2011 11:23:21 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index b4704e4ff..919a5f961 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6235 # Simulator instruction rate (inst/s) -host_mem_usage 252896 # Number of bytes of host memory used -host_seconds 0.90 # Real time elapsed on the host -host_tick_rate 11404126 # Simulator tick rate (ticks/s) +host_inst_rate 53641 # Simulator instruction rate (inst/s) +host_mem_usage 251224 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 97879368 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5620 # Number of instructions simulated sim_seconds 0.000010 # Number of seconds simulated From fe3d790ac8da41e8a0b9af93510cd874585c37e7 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 17 Mar 2011 19:20:20 -0500 Subject: [PATCH 10/18] ARM: Allow conditional quiesce instructions. This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage. --- src/arch/arm/isa/insts/m5ops.isa | 6 ++--- src/arch/arm/isa/insts/misc.isa | 20 +++++++++++------ src/arch/arm/isa/templates/pred.isa | 32 +++++++++++++++++++++++++++ src/sim/pseudo_inst.cc | 34 +++++++++++++++++++++++++++++ src/sim/pseudo_inst.hh | 1 + 5 files changed, 83 insertions(+), 10 deletions(-) diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index da3609bbc..8521cbc97 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -66,7 +66,7 @@ let {{ ["IsNonSpeculative", "IsQuiesce"]) header_output += BasicDeclare.subst(quiesceIop) decoder_output += BasicConstructor.subst(quiesceIop) - exec_output += PredOpExecute.subst(quiesceIop) + exec_output += QuiescePredOpExecute.subst(quiesceIop) quiesceNsCode = ''' #if FULL_SYSTEM @@ -80,7 +80,7 @@ let {{ ["IsNonSpeculative", "IsQuiesce"]) header_output += BasicDeclare.subst(quiesceNsIop) decoder_output += BasicConstructor.subst(quiesceNsIop) - exec_output += PredOpExecute.subst(quiesceNsIop) + exec_output += QuiescePredOpExecute.subst(quiesceNsIop) quiesceCyclesCode = ''' #if FULL_SYSTEM @@ -94,7 +94,7 @@ let {{ ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"]) header_output += BasicDeclare.subst(quiesceCyclesIop) decoder_output += BasicConstructor.subst(quiesceCyclesIop) - exec_output += PredOpExecute.subst(quiesceCyclesIop) + exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) quiesceTimeCode = ''' #if FULL_SYSTEM diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index be51d927d..cf5c7b47a 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -491,10 +491,13 @@ let {{ wfeCode = ''' #if FULL_SYSTEM - if (SevMailbox) + if (SevMailbox) { SevMailbox = 0; - else + PseudoInst::quiesceSkip(xc->tcBase()); + } + else { PseudoInst::quiesce(xc->tcBase()); + } #endif ''' wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ @@ -502,7 +505,7 @@ let {{ ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) header_output += BasicDeclare.subst(wfeIop) decoder_output += BasicConstructor.subst(wfeIop) - exec_output += PredOpExecute.subst(wfeIop) + exec_output += QuiescePredOpExecute.subst(wfeIop) wfiCode = ''' #if FULL_SYSTEM @@ -511,22 +514,25 @@ let {{ ''' wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ { "code" : wfiCode, "predicate_test" : predicateTest }, - ["IsNonSpeculative", "IsQuiesce"]) + ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) header_output += BasicDeclare.subst(wfiIop) decoder_output += BasicConstructor.subst(wfiIop) - exec_output += PredOpExecute.subst(wfiIop) + exec_output += QuiescePredOpExecute.subst(wfiIop) sevCode = ''' // Need a way for O3 to not scoreboard these accesses as pipe flushes. + SevMailbox = 1; System *sys = xc->tcBase()->getSystemPtr(); for (int x = 0; x < sys->numContexts(); x++) { ThreadContext *oc = sys->getThreadContext(x); - oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); + if (oc != xc->tcBase()) { + oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); + } } ''' sevIop = InstObjParams("sev", "SevInst", "PredOp", \ { "code" : sevCode, "predicate_test" : predicateTest }, - ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) + ["IsNonSpeculative", "IsSquashAfter"]) header_output += BasicDeclare.subst(sevIop) decoder_output += BasicConstructor.subst(sevIop) exec_output += PredOpExecute.subst(sevIop) diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index c9e7b1803..2a4bd9dab 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -170,6 +170,38 @@ def template PredOpExecute {{ } }}; +def template QuiescePredOpExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + uint64_t resTemp = 0; + resTemp = resTemp; + %(op_decl)s; + %(op_rd)s; + + if (%(predicate_test)s) + { + %(code)s; + if (fault == NoFault) + { + %(op_wb)s; + } + } else { + xc->setPredicate(false); +#if FULL_SYSTEM + PseudoInst::quiesceSkip(xc->tcBase()); +#endif + } + + if (fault == NoFault && machInst.itstateMask != 0&& + (!isMicroop() || isLastMicroop())) { + xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); + } + + return fault; + } +}}; + def template DataDecode {{ if (machInst.opcode4 == 0) { if (machInst.sField == 0) diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index f3b10f6d2..bcff2f5c1 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -1,4 +1,16 @@ /* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2003-2006 The Regents of The University of Michigan * All rights reserved. * @@ -85,6 +97,28 @@ quiesce(ThreadContext *tc) tc->getKernelStats()->quiesce(); } +void +quiesceSkip(ThreadContext *tc) +{ + BaseCPU *cpu = tc->getCpuPtr(); + + if (!cpu->params()->do_quiesce) + return; + + EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); + + Tick resume = curTick() + 1; + + cpu->reschedule(quiesceEvent, resume, true); + + DPRINTF(Quiesce, "%s: quiesceSkip() until %d\n", + cpu->name(), resume); + + tc->suspend(); + if (tc->getKernelStats()) + tc->getKernelStats()->quiesce(); +} + void quiesceNs(ThreadContext *tc, uint64_t ns) { diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh index 296b1556b..aec3b5d8a 100644 --- a/src/sim/pseudo_inst.hh +++ b/src/sim/pseudo_inst.hh @@ -45,6 +45,7 @@ extern bool doQuiesce; #if FULL_SYSTEM void arm(ThreadContext *tc); void quiesce(ThreadContext *tc); +void quiesceSkip(ThreadContext *tc); void quiesceNs(ThreadContext *tc, uint64_t ns); void quiesceCycles(ThreadContext *tc, uint64_t cycles); uint64_t quiesceTime(ThreadContext *tc); From b78be240cf1c1269ed83548bf71095193487ca33 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 17 Mar 2011 19:20:20 -0500 Subject: [PATCH 11/18] ARM: Detect and skip udelay() functions in linux kernel. This change speeds up booting, especially in MP cases, by not executing udelay() on the core but instead skipping ahead tha amount of time that is being delayed. --- src/arch/arm/linux/system.cc | 24 ++++++++++++++++++++++++ src/arch/arm/linux/system.hh | 13 +++++++++++++ src/cpu/simple/atomic.cc | 3 +++ src/cpu/simple/timing.cc | 4 ++++ src/kern/linux/events.cc | 25 +++++++++++++++++++++++++ src/kern/linux/events.hh | 27 +++++++++++++++++++++++++++ 6 files changed, 96 insertions(+) diff --git a/src/arch/arm/linux/system.cc b/src/arch/arm/linux/system.cc index 38024c058..7aff2b6ef 100644 --- a/src/arch/arm/linux/system.cc +++ b/src/arch/arm/linux/system.cc @@ -47,9 +47,11 @@ #include "base/loader/object_file.hh" #include "base/loader/symtab.hh" #include "cpu/thread_context.hh" +#include "kern/linux/events.hh" #include "mem/physical.hh" using namespace ArmISA; +using namespace Linux; LinuxArmSystem::LinuxArmSystem(Params *p) : ArmSystem(p) @@ -96,6 +98,24 @@ LinuxArmSystem::LinuxArmSystem(Params *p) if (!kernelPanicEvent) panic("could not find kernel symbol \'panic\'"); #endif + + // With ARM udelay() is #defined to __udelay + Addr addr = 0; + if (kernelSymtab->findAddress("__udelay", addr)) { + uDelaySkipEvent = new UDelayEvent(&pcEventQueue, "__udelay", + fixFuncEventAddr(addr), 1000, 0); + } else { + panic("couldn't find kernel symbol \'udelay\'"); + } + + // constant arguments to udelay() have some precomputation done ahead of + // time. Constant comes from code. + if (kernelSymtab->findAddress("__const_udelay", addr)) { + constUDelaySkipEvent = new UDelayEvent(&pcEventQueue, "__const_udelay", + fixFuncEventAddr(addr), 1000, 107374); + } else { + panic("couldn't find kernel symbol \'udelay\'"); + } } void @@ -115,6 +135,10 @@ LinuxArmSystem::initState() LinuxArmSystem::~LinuxArmSystem() { + if (uDelaySkipEvent) + delete uDelaySkipEvent; + if (constUDelaySkipEvent) + delete constUDelaySkipEvent; } LinuxArmSystem * diff --git a/src/arch/arm/linux/system.hh b/src/arch/arm/linux/system.hh index 4e5ebcd73..2ef65fea2 100644 --- a/src/arch/arm/linux/system.hh +++ b/src/arch/arm/linux/system.hh @@ -74,6 +74,19 @@ class LinuxArmSystem : public ArmSystem /** Event to halt the simulator if the kernel calls panic() */ BreakPCEvent *kernelPanicEvent; #endif + /** + * PC based event to skip udelay(