cpu: Tidy up the MemTest and make false sharing more obvious
The MemTest class really only tests false sharing, and as such there was a lot of old cruft that could be removed. This patch cleans up the tester, and also makes it more clear what the assumptions are. As part of this simplification the reference functional memory is also removed. The regression configs using MemTest are updated to reflect the changes, and the stats will be bumped in a separate patch. The example config will be updated in a separate patch due to more extensive re-work. In a follow-on patch a new tester will be introduced that uses the MemChecker to implement true sharing.
This commit is contained in:
Andreas Hansson
parent
550c318490
commit
6563ec8634
7 changed files with 286 additions and 352 deletions
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@ -124,7 +124,7 @@ else:
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# build a list of prototypes, one for each level of treespec, starting
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# at the end (last entry is tester objects)
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prototypes = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
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prototypes = [ MemTest(max_loads=options.maxloads,
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percent_functional=options.functional,
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percent_uncacheable=options.uncacheable,
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progress_interval=options.progress) ]
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@ -146,12 +146,9 @@ for scale in treespec[:-2]:
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prototypes.insert(0, next)
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# system simulated
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system = System(funcmem = SimpleMemory(in_addr_map = False),
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funcbus = NoncoherentXBar(),
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physmem = SimpleMemory(latency = "100ns"),
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system = System(physmem = SimpleMemory(latency = "100ns"),
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cache_line_size = block_size)
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system.voltage_domain = VoltageDomain(voltage = '1V')
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system.clk_domain = SrcClockDomain(clock = options.sys_clock,
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@ -182,14 +179,10 @@ def make_level(spec, prototypes, attach_obj, attach_port):
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# we just built the MemTest objects
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parent.cpu = objs
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for t in objs:
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t.test = getattr(attach_obj, attach_port)
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t.functional = system.funcbus.slave
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t.port = getattr(attach_obj, attach_port)
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make_level(treespec, prototypes, system.physmem, "port")
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# connect reference memory to funcbus
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system.funcbus.master = system.funcmem.port
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# -----------------------
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# run simulation
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# -----------------------
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@ -202,7 +195,7 @@ else:
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# The system port is never used in the tester so merely connect it
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# to avoid problems
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root.system.system_port = root.system.funcbus.slave
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root.system.system_port = root.system.physmem.cpu_side_bus.slave
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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@ -1,3 +1,15 @@
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# Copyright (c) 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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@ -25,6 +37,7 @@
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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# Andreas Hansson
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from MemObject import MemObject
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from m5.params import *
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@ -33,26 +46,30 @@ from m5.proxy import *
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class MemTest(MemObject):
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type = 'MemTest'
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cxx_header = "cpu/testers/memtest/memtest.hh"
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max_loads = Param.Counter(0, "number of loads to execute")
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atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
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memory_size = Param.Int(65536, "memory size")
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percent_dest_unaligned = Param.Percent(50,
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"percent of copy dest address that are unaligned")
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percent_reads = Param.Percent(65, "target read percentage")
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issue_dmas = Param.Bool(False, "this memtester should issue dma requests")
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percent_source_unaligned = Param.Percent(50,
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"percent of copy source address that are unaligned")
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percent_functional = Param.Percent(50, "percent of access that are functional")
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percent_uncacheable = Param.Percent(10,
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"target uncacheable percentage")
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# Interval of packet injection, the size of the memory range
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# touched, and an optional stop condition
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interval = Param.Cycles(1, "Interval between request packets")
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size = Param.Unsigned(65536, "Size of memory region to use (bytes)")
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max_loads = Param.Counter(0, "Number of loads to execute before exiting")
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# Control the mix of packets and if functional accesses are part of
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# the mix or not
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percent_reads = Param.Percent(65, "Percentage reads")
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percent_functional = Param.Percent(50, "Percentage functional accesses")
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percent_uncacheable = Param.Percent(10, "Percentage uncacheable")
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# Determine how often to print progress messages and what timeout
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# to use for checking progress of both requests and responses
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progress_interval = Param.Counter(1000000,
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"progress report interval (in accesses)")
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trace_addr = Param.Addr(0, "address to trace")
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"Progress report interval (in accesses)")
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progress_check = Param.Cycles(5000000, "Cycles before exiting " \
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"due to lack of progress")
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test = MasterPort("Port to the memory system to test")
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functional = MasterPort("Port to the functional memory " \
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"used for verification")
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suppress_func_warnings = Param.Bool(False,
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"suppress warnings when functional accesses fail.\n")
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sys = Param.System(Parent.any, "System Parameter")
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port = MasterPort("Port to the memory system")
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system = Param.System(Parent.any, "System this tester is part of")
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# Add the ability to supress error responses on functional
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# accesses as Ruby needs this
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suppress_func_warnings = Param.Bool(False, "Suppress warnings when "\
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"functional accesses fail.")
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@ -1,4 +1,16 @@
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/*
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* Copyright (c) 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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@ -27,173 +39,129 @@
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*
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* Authors: Erik Hallnor
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* Steve Reinhardt
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* Andreas Hansson
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*/
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// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
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#include <iomanip>
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#include <set>
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#include <string>
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#include <vector>
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#include "base/misc.hh"
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#include "base/random.hh"
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#include "base/statistics.hh"
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#include "cpu/testers/memtest/memtest.hh"
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#include "debug/MemTest.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "mem/request.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_exit.hh"
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#include "sim/stats.hh"
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#include "sim/system.hh"
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using namespace std;
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int TESTER_ALLOCATOR=0;
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unsigned int TESTER_ALLOCATOR = 0;
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bool
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MemTest::CpuPort::recvTimingResp(PacketPtr pkt)
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{
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memtest->completeRequest(pkt);
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memtest.completeRequest(pkt);
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return true;
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}
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void
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MemTest::CpuPort::recvRetry()
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{
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memtest->doRetry();
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memtest.recvRetry();
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}
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void
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bool
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MemTest::sendPkt(PacketPtr pkt) {
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if (atomic) {
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cachePort.sendAtomic(pkt);
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port.sendAtomic(pkt);
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completeRequest(pkt);
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}
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else if (!cachePort.sendTimingReq(pkt)) {
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DPRINTF(MemTest, "accessRetry setting to true\n");
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//
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// dma requests should never be retried
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//
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if (issueDmas) {
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panic("Nacked DMA requests are not supported\n");
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}
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accessRetry = true;
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retryPkt = pkt;
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} else {
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if (issueDmas) {
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dmaOutstanding = true;
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if (!port.sendTimingReq(pkt)) {
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retryPkt = pkt;
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return false;
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}
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}
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return true;
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}
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MemTest::MemTest(const Params *p)
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: MemObject(p),
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tickEvent(this),
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cachePort("test", this),
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funcPort("functional", this),
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funcProxy(funcPort, p->sys->cacheLineSize()),
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retryPkt(NULL),
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// mainMem(main_mem),
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// checkMem(check_mem),
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size(p->memory_size),
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noRequestEvent(this),
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noResponseEvent(this),
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port("port", *this),
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retryPkt(nullptr),
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size(p->size),
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interval(p->interval),
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percentReads(p->percent_reads),
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percentFunctional(p->percent_functional),
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percentUncacheable(p->percent_uncacheable),
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issueDmas(p->issue_dmas),
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masterId(p->sys->getMasterId(name())),
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blockSize(p->sys->cacheLineSize()),
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masterId(p->system->getMasterId(name())),
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blockSize(p->system->cacheLineSize()),
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blockAddrMask(blockSize - 1),
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progressInterval(p->progress_interval),
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progressCheck(p->progress_check),
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nextProgressMessage(p->progress_interval),
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percentSourceUnaligned(p->percent_source_unaligned),
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percentDestUnaligned(p->percent_dest_unaligned),
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maxLoads(p->max_loads),
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atomic(p->atomic),
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suppress_func_warnings(p->suppress_func_warnings)
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atomic(p->system->isAtomicMode()),
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suppressFuncWarnings(p->suppress_func_warnings)
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{
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id = TESTER_ALLOCATOR++;
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fatal_if(id >= blockSize, "Too many testers, only %d allowed\n",
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blockSize - 1);
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// Needs to be masked off once we know the block size.
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traceBlockAddr = p->trace_addr;
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baseAddr1 = 0x100000;
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baseAddr2 = 0x400000;
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uncacheAddr = 0x800000;
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blockAddrMask = blockSize - 1;
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traceBlockAddr = blockAddr(traceBlockAddr);
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// set up counters
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noResponseCycles = 0;
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numReads = 0;
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numWrites = 0;
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schedule(tickEvent, 0);
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accessRetry = false;
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dmaOutstanding = false;
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// kick things into action
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schedule(tickEvent, curTick());
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schedule(noRequestEvent, clockEdge(progressCheck));
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schedule(noResponseEvent, clockEdge(progressCheck));
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}
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BaseMasterPort &
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MemTest::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "functional")
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return funcPort;
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else if (if_name == "test")
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return cachePort;
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if (if_name == "port")
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return port;
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else
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return MemObject::getMasterPort(if_name, idx);
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}
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void
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MemTest::init()
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{
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// initial memory contents for both physical memory and functional
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// memory should be 0; no need to initialize them.
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}
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void
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MemTest::completeRequest(PacketPtr pkt)
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MemTest::completeRequest(PacketPtr pkt, bool functional)
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{
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Request *req = pkt->req;
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assert(req->getSize() == 1);
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if (issueDmas) {
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dmaOutstanding = false;
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}
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// this address is no longer outstanding
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auto remove_addr = outstandingAddrs.find(req->getPaddr());
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assert(remove_addr != outstandingAddrs.end());
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outstandingAddrs.erase(remove_addr);
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DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n",
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DPRINTF(MemTest, "Completing %s at address %x (blk %x) %s\n",
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pkt->isWrite() ? "write" : "read",
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req->getPaddr(), blockAddr(req->getPaddr()),
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req->getPaddr(), blockAlign(req->getPaddr()),
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pkt->isError() ? "error" : "success");
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MemTestSenderState *state =
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safe_cast<MemTestSenderState *>(pkt->senderState);
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uint8_t *data = state->data;
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// @todo: This should really be a const pointer
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uint8_t *pkt_data = pkt->getPtr<uint8_t>();
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//Remove the address from the list of outstanding
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std::set<unsigned>::iterator removeAddr =
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outstandingAddrs.find(req->getPaddr());
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assert(removeAddr != outstandingAddrs.end());
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outstandingAddrs.erase(removeAddr);
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const uint8_t *pkt_data = pkt->getConstPtr<uint8_t>();
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if (pkt->isError()) {
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if (!suppress_func_warnings) {
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warn("Functional %s access failed at %#x\n",
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pkt->isWrite() ? "write" : "read", req->getPaddr());
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if (!functional || !suppressFuncWarnings) {
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warn("%s access failed at %#x\n",
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pkt->isWrite() ? "Write" : "Read", req->getPaddr());
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}
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} else {
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if (pkt->isRead()) {
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if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
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uint8_t ref_data = referenceData[req->getPaddr()];
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if (pkt_data[0] != ref_data) {
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panic("%s: read of %x (blk %x) @ cycle %d "
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"returns %x, expected %x\n", name(),
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req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
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*pkt_data, *data);
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req->getPaddr(), blockAlign(req->getPaddr()), curTick(),
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pkt_data[0], ref_data);
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}
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numReads++;
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@ -209,17 +177,21 @@ MemTest::completeRequest(PacketPtr pkt)
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exitSimLoop("maximum number of loads reached");
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} else {
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assert(pkt->isWrite());
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funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize());
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// update the reference data
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referenceData[req->getPaddr()] = pkt_data[0];
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numWrites++;
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numWritesStat++;
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}
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}
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noResponseCycles = 0;
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delete state;
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delete [] data;
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delete pkt->req;
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// the packet will delete the data
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delete pkt;
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// finally shift the response timeout forward
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reschedule(noResponseEvent, clockEdge(progressCheck), true);
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}
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void
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@ -236,151 +208,126 @@ MemTest::regStats()
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.name(name() + ".num_writes")
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.desc("number of write accesses completed")
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;
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numCopiesStat
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.name(name() + ".num_copies")
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.desc("number of copy accesses completed")
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;
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}
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void
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MemTest::tick()
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{
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if (!tickEvent.scheduled())
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schedule(tickEvent, clockEdge(Cycles(1)));
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// we should never tick if we are waiting for a retry
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assert(!retryPkt);
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if (++noResponseCycles >= 500000) {
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if (issueDmas) {
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cerr << "DMA tester ";
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}
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cerr << name() << ": deadlocked at cycle " << curTick() << endl;
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fatal("");
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}
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if (accessRetry || (issueDmas && dmaOutstanding)) {
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DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
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return;
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}
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//make new request
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// create a new request
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unsigned cmd = random_mt.random(0, 100);
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unsigned offset = random_mt.random<unsigned>(0, size - 1);
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unsigned base = random_mt.random(0, 1);
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uint64_t data = random_mt.random<uint64_t>();
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unsigned access_size = random_mt.random(0, 3);
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uint8_t data = random_mt.random<uint8_t>();
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bool uncacheable = random_mt.random(0, 100) < percentUncacheable;
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unsigned dma_access_size = random_mt.random(0, 3);
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//If we aren't doing copies, use id as offset, and do a false sharing
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//mem tester
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//We can eliminate the lower bits of the offset, and then use the id
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//to offset within the blks
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offset = blockAddr(offset);
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offset += id;
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access_size = 0;
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dma_access_size = 0;
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unsigned base = random_mt.random(0, 1);
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Request::Flags flags;
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Addr paddr;
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// generate a unique address
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do {
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unsigned offset = random_mt.random<unsigned>(0, size - 1);
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// use the tester id as offset within the block for false sharing
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offset = blockAlign(offset);
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offset += id;
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if (uncacheable) {
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flags.set(Request::UNCACHEABLE);
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paddr = uncacheAddr + offset;
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} else {
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paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
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}
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// For now we only allow one outstanding request per address
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||||
// per tester This means we assume CPU does write forwarding
|
||||
// to reads that alias something in the cpu store buffer.
|
||||
if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
|
||||
return;
|
||||
}
|
||||
} while (outstandingAddrs.find(paddr) != outstandingAddrs.end());
|
||||
|
||||
bool do_functional = (random_mt.random(0, 100) < percentFunctional) &&
|
||||
!uncacheable;
|
||||
Request *req = nullptr;
|
||||
uint8_t *result = new uint8_t[8];
|
||||
Request *req = new Request(paddr, 1, flags, masterId);
|
||||
req->setThreadContext(id, 0);
|
||||
|
||||
if (issueDmas) {
|
||||
paddr &= ~((1 << dma_access_size) - 1);
|
||||
req = new Request(paddr, 1 << dma_access_size, flags, masterId);
|
||||
req->setThreadContext(id,0);
|
||||
} else {
|
||||
paddr &= ~((1 << access_size) - 1);
|
||||
req = new Request(paddr, 1 << access_size, flags, masterId);
|
||||
req->setThreadContext(id,0);
|
||||
}
|
||||
assert(req->getSize() == 1);
|
||||
outstandingAddrs.insert(paddr);
|
||||
|
||||
// sanity check
|
||||
panic_if(outstandingAddrs.size() > 100,
|
||||
"Tester %s has more than 100 outstanding requests\n", name());
|
||||
|
||||
PacketPtr pkt = nullptr;
|
||||
uint8_t *pkt_data = new uint8_t[1];
|
||||
|
||||
if (cmd < percentReads) {
|
||||
// read
|
||||
outstandingAddrs.insert(paddr);
|
||||
|
||||
// ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
|
||||
funcProxy.readBlob(req->getPaddr(), result, req->getSize());
|
||||
// start by ensuring there is a reference value if we have not
|
||||
// seen this address before
|
||||
uint8_t M5_VAR_USED ref_data = 0;
|
||||
auto ref = referenceData.find(req->getPaddr());
|
||||
if (ref == referenceData.end()) {
|
||||
referenceData[req->getPaddr()] = 0;
|
||||
} else {
|
||||
ref_data = ref->second;
|
||||
}
|
||||
|
||||
DPRINTF(MemTest,
|
||||
"id %d initiating %sread at addr %x (blk %x) expecting %x\n",
|
||||
id, do_functional ? "functional " : "", req->getPaddr(),
|
||||
blockAddr(req->getPaddr()), *result);
|
||||
|
||||
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
|
||||
pkt->dataDynamic(new uint8_t[req->getSize()]);
|
||||
MemTestSenderState *state = new MemTestSenderState(result);
|
||||
pkt->senderState = state;
|
||||
|
||||
if (do_functional) {
|
||||
assert(pkt->needsResponse());
|
||||
pkt->setSuppressFuncError();
|
||||
cachePort.sendFunctional(pkt);
|
||||
completeRequest(pkt);
|
||||
} else {
|
||||
sendPkt(pkt);
|
||||
}
|
||||
} else {
|
||||
// write
|
||||
outstandingAddrs.insert(paddr);
|
||||
|
||||
DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n",
|
||||
"Initiating %sread at addr %x (blk %x) expecting %x\n",
|
||||
do_functional ? "functional " : "", req->getPaddr(),
|
||||
blockAddr(req->getPaddr()), data & 0xff);
|
||||
blockAlign(req->getPaddr()), ref_data);
|
||||
|
||||
PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
|
||||
uint8_t *pkt_data = new uint8_t[req->getSize()];
|
||||
pkt = new Packet(req, MemCmd::ReadReq);
|
||||
pkt->dataDynamic(pkt_data);
|
||||
memcpy(pkt_data, &data, req->getSize());
|
||||
MemTestSenderState *state = new MemTestSenderState(result);
|
||||
pkt->senderState = state;
|
||||
} else {
|
||||
DPRINTF(MemTest, "Initiating %swrite at addr %x (blk %x) value %x\n",
|
||||
do_functional ? "functional " : "", req->getPaddr(),
|
||||
blockAlign(req->getPaddr()), data);
|
||||
|
||||
pkt = new Packet(req, MemCmd::WriteReq);
|
||||
pkt->dataDynamic(pkt_data);
|
||||
pkt_data[0] = data;
|
||||
}
|
||||
|
||||
// there is no point in ticking if we are waiting for a retry
|
||||
bool keep_ticking = true;
|
||||
if (do_functional) {
|
||||
pkt->setSuppressFuncError();
|
||||
cachePort.sendFunctional(pkt);
|
||||
completeRequest(pkt);
|
||||
port.sendFunctional(pkt);
|
||||
completeRequest(pkt, true);
|
||||
} else {
|
||||
sendPkt(pkt);
|
||||
keep_ticking = sendPkt(pkt);
|
||||
}
|
||||
|
||||
if (keep_ticking) {
|
||||
// schedule the next tick
|
||||
schedule(tickEvent, clockEdge(interval));
|
||||
|
||||
// finally shift the timeout for sending of requests forwards
|
||||
// as we have successfully sent a packet
|
||||
reschedule(noRequestEvent, clockEdge(progressCheck), true);
|
||||
} else {
|
||||
DPRINTF(MemTest, "Waiting for retry\n");
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
MemTest::doRetry()
|
||||
MemTest::noRequest()
|
||||
{
|
||||
if (cachePort.sendTimingReq(retryPkt)) {
|
||||
DPRINTF(MemTest, "accessRetry setting to false\n");
|
||||
accessRetry = false;
|
||||
retryPkt = NULL;
|
||||
}
|
||||
panic("%s did not send a request for %d cycles", name(), progressCheck);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
MemTest::printAddr(Addr a)
|
||||
MemTest::noResponse()
|
||||
{
|
||||
cachePort.printAddr(a);
|
||||
panic("%s did not see a response for %d cycles", name(), progressCheck);
|
||||
}
|
||||
|
||||
void
|
||||
MemTest::recvRetry()
|
||||
{
|
||||
assert(retryPkt);
|
||||
if (port.sendTimingReq(retryPkt)) {
|
||||
DPRINTF(MemTest, "Proceeding after successful retry\n");
|
||||
|
||||
retryPkt = nullptr;
|
||||
// kick things into action again
|
||||
schedule(tickEvent, clockEdge(interval));
|
||||
}
|
||||
}
|
||||
|
||||
MemTest *
|
||||
MemTestParams::create()
|
||||
|
|
|
|||
|
|
@ -1,4 +1,16 @@
|
|||
/*
|
||||
* Copyright (c) 2015 ARM Limited
|
||||
* All rights reserved
|
||||
*
|
||||
* The license below extends only to copyright in the software and shall
|
||||
* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
||||
* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
|
||||
* unmodified and in its entirety in all distributions of the software,
|
||||
* modified or unmodified, in source code or in binary form.
|
||||
*
|
||||
* Copyright (c) 2002-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
|
|
@ -27,166 +39,152 @@
|
|||
*
|
||||
* Authors: Erik Hallnor
|
||||
* Steve Reinhardt
|
||||
* Andreas Hansson
|
||||
*/
|
||||
|
||||
#ifndef __CPU_MEMTEST_MEMTEST_HH__
|
||||
#define __CPU_MEMTEST_MEMTEST_HH__
|
||||
|
||||
#include <set>
|
||||
#include <unordered_map>
|
||||
|
||||
#include "base/statistics.hh"
|
||||
#include "mem/mem_object.hh"
|
||||
#include "mem/port.hh"
|
||||
#include "mem/port_proxy.hh"
|
||||
#include "params/MemTest.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
#include "sim/stats.hh"
|
||||
|
||||
class Packet;
|
||||
/**
|
||||
* The MemTest class tests a cache coherent memory system by
|
||||
* generating false sharing and verifying the read data against a
|
||||
* reference updated on the completion of writes. Each tester reads
|
||||
* and writes a specific byte in a cache line, as determined by its
|
||||
* unique id. Thus, all requests issued by the MemTest instance are a
|
||||
* single byte and a specific address is only ever touched by a single
|
||||
* tester.
|
||||
*
|
||||
* In addition to verifying the data, the tester also has timeouts for
|
||||
* both requests and responses, thus checking that the memory-system
|
||||
* is making progress.
|
||||
*/
|
||||
class MemTest : public MemObject
|
||||
{
|
||||
|
||||
public:
|
||||
|
||||
typedef MemTestParams Params;
|
||||
MemTest(const Params *p);
|
||||
|
||||
virtual void init();
|
||||
|
||||
// register statistics
|
||||
virtual void regStats();
|
||||
|
||||
// main simulation loop (one cycle)
|
||||
void tick();
|
||||
|
||||
virtual BaseMasterPort &getMasterPort(const std::string &if_name,
|
||||
PortID idx = InvalidPortID);
|
||||
|
||||
/**
|
||||
* Print state of address in memory system via PrintReq (for
|
||||
* debugging).
|
||||
*/
|
||||
void printAddr(Addr a);
|
||||
|
||||
protected:
|
||||
class TickEvent : public Event
|
||||
{
|
||||
private:
|
||||
MemTest *cpu;
|
||||
|
||||
public:
|
||||
TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
|
||||
void process() { cpu->tick(); }
|
||||
virtual const char *description() const { return "MemTest tick"; }
|
||||
};
|
||||
void tick();
|
||||
|
||||
TickEvent tickEvent;
|
||||
EventWrapper<MemTest, &MemTest::tick> tickEvent;
|
||||
|
||||
void noRequest();
|
||||
|
||||
EventWrapper<MemTest, &MemTest::noRequest> noRequestEvent;
|
||||
|
||||
void noResponse();
|
||||
|
||||
EventWrapper<MemTest, &MemTest::noResponse> noResponseEvent;
|
||||
|
||||
class CpuPort : public MasterPort
|
||||
{
|
||||
MemTest *memtest;
|
||||
MemTest &memtest;
|
||||
|
||||
public:
|
||||
|
||||
CpuPort(const std::string &_name, MemTest *_memtest)
|
||||
: MasterPort(_name, _memtest), memtest(_memtest)
|
||||
CpuPort(const std::string &_name, MemTest &_memtest)
|
||||
: MasterPort(_name, &_memtest), memtest(_memtest)
|
||||
{ }
|
||||
|
||||
protected:
|
||||
|
||||
virtual bool recvTimingResp(PacketPtr pkt);
|
||||
bool recvTimingResp(PacketPtr pkt);
|
||||
|
||||
virtual void recvTimingSnoopReq(PacketPtr pkt) { }
|
||||
void recvTimingSnoopReq(PacketPtr pkt) { }
|
||||
|
||||
virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
|
||||
void recvFunctionalSnoop(PacketPtr pkt) { }
|
||||
|
||||
virtual void recvFunctionalSnoop(PacketPtr pkt) { }
|
||||
Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
|
||||
|
||||
virtual void recvRetry();
|
||||
void recvRetry();
|
||||
};
|
||||
|
||||
CpuPort cachePort;
|
||||
CpuPort funcPort;
|
||||
PortProxy funcProxy;
|
||||
|
||||
class MemTestSenderState : public Packet::SenderState
|
||||
{
|
||||
public:
|
||||
/** Constructor. */
|
||||
MemTestSenderState(uint8_t *_data)
|
||||
: data(_data)
|
||||
{ }
|
||||
|
||||
// Hold onto data pointer
|
||||
uint8_t *data;
|
||||
};
|
||||
CpuPort port;
|
||||
|
||||
PacketPtr retryPkt;
|
||||
|
||||
bool accessRetry;
|
||||
const unsigned size;
|
||||
|
||||
//
|
||||
// The dmaOustanding flag enforces only one dma at a time
|
||||
//
|
||||
bool dmaOutstanding;
|
||||
const Cycles interval;
|
||||
|
||||
unsigned size; // size of testing memory region
|
||||
|
||||
unsigned percentReads; // target percentage of read accesses
|
||||
unsigned percentFunctional; // target percentage of functional accesses
|
||||
unsigned percentUncacheable;
|
||||
|
||||
bool issueDmas;
|
||||
const unsigned percentReads;
|
||||
const unsigned percentFunctional;
|
||||
const unsigned percentUncacheable;
|
||||
|
||||
/** Request id for all generated traffic */
|
||||
MasterID masterId;
|
||||
|
||||
int id;
|
||||
unsigned int id;
|
||||
|
||||
std::set<unsigned> outstandingAddrs;
|
||||
std::set<Addr> outstandingAddrs;
|
||||
|
||||
unsigned blockSize;
|
||||
// store the expected value for the addresses we have touched
|
||||
std::unordered_map<Addr, uint8_t> referenceData;
|
||||
|
||||
Addr blockAddrMask;
|
||||
const unsigned blockSize;
|
||||
|
||||
Addr blockAddr(Addr addr)
|
||||
const Addr blockAddrMask;
|
||||
|
||||
/**
|
||||
* Get the block aligned address.
|
||||
*
|
||||
* @param addr Address to align
|
||||
* @return The block aligned address
|
||||
*/
|
||||
Addr blockAlign(Addr addr) const
|
||||
{
|
||||
return (addr & ~blockAddrMask);
|
||||
}
|
||||
|
||||
Addr traceBlockAddr;
|
||||
|
||||
Addr baseAddr1; // fix this to option
|
||||
Addr baseAddr2; // fix this to option
|
||||
Addr baseAddr1;
|
||||
Addr baseAddr2;
|
||||
Addr uncacheAddr;
|
||||
|
||||
unsigned progressInterval; // frequency of progress reports
|
||||
const unsigned progressInterval; // frequency of progress reports
|
||||
const Cycles progressCheck;
|
||||
Tick nextProgressMessage; // access # for next progress report
|
||||
|
||||
unsigned percentSourceUnaligned;
|
||||
unsigned percentDestUnaligned;
|
||||
|
||||
Tick noResponseCycles;
|
||||
|
||||
uint64_t numReads;
|
||||
uint64_t numWrites;
|
||||
uint64_t maxLoads;
|
||||
const uint64_t maxLoads;
|
||||
|
||||
bool atomic;
|
||||
bool suppress_func_warnings;
|
||||
const bool atomic;
|
||||
|
||||
const bool suppressFuncWarnings;
|
||||
|
||||
Stats::Scalar numReadsStat;
|
||||
Stats::Scalar numWritesStat;
|
||||
Stats::Scalar numCopiesStat;
|
||||
|
||||
// called by MemCompleteEvent::process()
|
||||
void completeRequest(PacketPtr pkt);
|
||||
/**
|
||||
* Complete a request by checking the response.
|
||||
*
|
||||
* @param pkt Response packet
|
||||
* @param functional Whether the access was functional or not
|
||||
*/
|
||||
void completeRequest(PacketPtr pkt, bool functional = false);
|
||||
|
||||
void sendPkt(PacketPtr pkt);
|
||||
bool sendPkt(PacketPtr pkt);
|
||||
|
||||
void doRetry();
|
||||
void recvRetry();
|
||||
|
||||
friend class MemCompleteEvent;
|
||||
};
|
||||
|
||||
#endif // __CPU_MEMTEST_MEMTEST_HH__
|
||||
|
|
|
|||
|
|
@ -36,8 +36,7 @@ nb_cores = 8
|
|||
cpus = [ MemTest() for i in xrange(nb_cores) ]
|
||||
|
||||
# system simulated
|
||||
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
|
||||
funcbus = NoncoherentXBar(),
|
||||
system = System(cpu = cpus,
|
||||
physmem = SimpleMemory(),
|
||||
membus = CoherentXBar(width=16, snoop_filter = SnoopFilter()))
|
||||
# Dummy voltage domain for all our clock domains
|
||||
|
|
@ -63,15 +62,11 @@ for cpu in cpus:
|
|||
# All cpus are associated with cpu_clk_domain
|
||||
cpu.clk_domain = system.cpu_clk_domain
|
||||
cpu.l1c = L1Cache(size = '32kB', assoc = 4)
|
||||
cpu.l1c.cpu_side = cpu.test
|
||||
cpu.l1c.cpu_side = cpu.port
|
||||
cpu.l1c.mem_side = system.toL2Bus.slave
|
||||
system.funcbus.slave = cpu.functional
|
||||
|
||||
system.system_port = system.membus.slave
|
||||
|
||||
# connect reference memory to funcbus
|
||||
system.funcmem.port = system.funcbus.master
|
||||
|
||||
# connect memory to membus
|
||||
system.physmem.port = system.membus.master
|
||||
|
||||
|
|
@ -82,6 +77,3 @@ system.physmem.port = system.membus.master
|
|||
|
||||
root = Root( full_system = False, system = system )
|
||||
root.system.mem_mode = 'timing'
|
||||
#root.trace.flags="Cache CachePort MemoryAccess"
|
||||
#root.trace.cycle=1
|
||||
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ options.ports=32
|
|||
nb_cores = 8
|
||||
|
||||
# ruby does not support atomic, functional, or uncacheable accesses
|
||||
cpus = [ MemTest(atomic=False, percent_functional=50,
|
||||
cpus = [ MemTest(percent_functional=50,
|
||||
percent_uncacheable=0, suppress_func_warnings=True) \
|
||||
for i in xrange(nb_cores) ]
|
||||
|
||||
|
|
@ -78,9 +78,7 @@ cpus = [ MemTest(atomic=False, percent_functional=50,
|
|||
options.num_cpus = nb_cores
|
||||
|
||||
# system simulated
|
||||
system = System(cpu = cpus,
|
||||
funcmem = SimpleMemory(in_addr_map = False),
|
||||
funcbus = NoncoherentXBar())
|
||||
system = System(cpu = cpus)
|
||||
# Dummy voltage domain for all our clock domains
|
||||
system.voltage_domain = VoltageDomain()
|
||||
system.clk_domain = SrcClockDomain(clock = '1GHz',
|
||||
|
|
@ -107,11 +105,10 @@ assert(len(cpus) == len(system.ruby._cpu_ports))
|
|||
|
||||
for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
|
||||
#
|
||||
# Tie the cpu test and functional ports to the ruby cpu ports and
|
||||
# Tie the cpu port to the ruby cpu ports and
|
||||
# physmem, respectively
|
||||
#
|
||||
cpus[i].test = ruby_port.slave
|
||||
cpus[i].functional = system.funcbus.slave
|
||||
cpus[i].port = ruby_port.slave
|
||||
|
||||
#
|
||||
# Since the memtester is incredibly bursty, increase the deadlock
|
||||
|
|
@ -119,9 +116,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
|
|||
#
|
||||
ruby_port.deadlock_threshold = 1000000
|
||||
|
||||
# connect reference memory to funcbus
|
||||
system.funcmem.port = system.funcbus.master
|
||||
|
||||
# -----------------------
|
||||
# run simulation
|
||||
# -----------------------
|
||||
|
|
|
|||
|
|
@ -36,8 +36,7 @@ nb_cores = 8
|
|||
cpus = [ MemTest() for i in xrange(nb_cores) ]
|
||||
|
||||
# system simulated
|
||||
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
|
||||
funcbus = NoncoherentXBar(),
|
||||
system = System(cpu = cpus,
|
||||
physmem = SimpleMemory(),
|
||||
membus = CoherentXBar(width=16))
|
||||
# Dummy voltage domain for all our clock domains
|
||||
|
|
@ -62,15 +61,11 @@ for cpu in cpus:
|
|||
# All cpus are associated with cpu_clk_domain
|
||||
cpu.clk_domain = system.cpu_clk_domain
|
||||
cpu.l1c = L1Cache(size = '32kB', assoc = 4)
|
||||
cpu.l1c.cpu_side = cpu.test
|
||||
cpu.l1c.cpu_side = cpu.port
|
||||
cpu.l1c.mem_side = system.toL2Bus.slave
|
||||
system.funcbus.slave = cpu.functional
|
||||
|
||||
system.system_port = system.membus.slave
|
||||
|
||||
# connect reference memory to funcbus
|
||||
system.funcmem.port = system.funcbus.master
|
||||
|
||||
# connect memory to membus
|
||||
system.physmem.port = system.membus.master
|
||||
|
||||
|
|
@ -81,6 +76,4 @@ system.physmem.port = system.membus.master
|
|||
|
||||
root = Root( full_system = False, system = system )
|
||||
root.system.mem_mode = 'timing'
|
||||
#root.trace.flags="Cache CachePort MemoryAccess"
|
||||
#root.trace.cycle=1
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue