6563ec8634
The MemTest class really only tests false sharing, and as such there was a lot of old cruft that could be removed. This patch cleans up the tester, and also makes it more clear what the assumptions are. As part of this simplification the reference functional memory is also removed. The regression configs using MemTest are updated to reflect the changes, and the stats will be bumped in a separate patch. The example config will be updated in a separate patch due to more extensive re-work. In a follow-on patch a new tester will be introduced that uses the MemChecker to implement true sharing.
80 lines
3.1 KiB
Python
80 lines
3.1 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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import m5
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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from Caches import *
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#MAX CORES IS 8 with the fals sharing method
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nb_cores = 8
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cpus = [ MemTest() for i in xrange(nb_cores) ]
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# system simulated
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system = System(cpu = cpus,
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physmem = SimpleMemory(),
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membus = CoherentXBar(width=16))
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# Dummy voltage domain for all our clock domains
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system.voltage_domain = VoltageDomain()
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system.clk_domain = SrcClockDomain(clock = '1GHz',
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voltage_domain = system.voltage_domain)
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# Create a seperate clock domain for components that should run at
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# CPUs frequency
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system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
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voltage_domain = system.voltage_domain)
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system.toL2Bus = CoherentXBar(clk_domain = system.cpu_clk_domain, width=16)
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system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
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system.l2c.cpu_side = system.toL2Bus.master
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# connect l2c to membus
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system.l2c.mem_side = system.membus.slave
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# add L1 caches
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for cpu in cpus:
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# All cpus are associated with cpu_clk_domain
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cpu.clk_domain = system.cpu_clk_domain
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cpu.l1c = L1Cache(size = '32kB', assoc = 4)
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cpu.l1c.cpu_side = cpu.port
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cpu.l1c.mem_side = system.toL2Bus.slave
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system.system_port = system.membus.slave
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# connect memory to membus
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system.physmem.port = system.membus.master
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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