stats: update for snoop filter tweak
--HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
This commit is contained in:
Curtis Dunham
parent
71a02f624e
commit
62b6ff22ec
184 changed files with 39509 additions and 91985 deletions
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@ -4,11 +4,11 @@ sim_seconds 1.907083 # Nu
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sim_ticks 1907083088000 # Number of ticks simulated
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final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 20979 # Simulator instruction rate (inst/s)
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host_op_rate 20979 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 712669715 # Simulator tick rate (ticks/s)
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host_mem_usage 389460 # Number of bytes of host memory used
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host_seconds 2675.97 # Real time elapsed on the host
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host_inst_rate 20329 # Simulator instruction rate (inst/s)
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host_op_rate 20329 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 690572794 # Simulator tick rate (ticks/s)
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host_mem_usage 384580 # Number of bytes of host memory used
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host_seconds 2761.60 # Real time elapsed on the host
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sim_insts 56139550 # Number of instructions simulated
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sim_ops 56139550 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 1.876794 # Nu
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sim_ticks 1876794488000 # Number of ticks simulated
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final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 142986 # Simulator instruction rate (inst/s)
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host_op_rate 142986 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5064945596 # Simulator tick rate (ticks/s)
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host_mem_usage 335448 # Number of bytes of host memory used
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host_seconds 370.55 # Real time elapsed on the host
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host_inst_rate 156335 # Simulator instruction rate (inst/s)
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host_op_rate 156335 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5537786455 # Simulator tick rate (ticks/s)
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host_mem_usage 329540 # Number of bytes of host memory used
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host_seconds 338.91 # Real time elapsed on the host
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sim_insts 52982943 # Number of instructions simulated
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sim_ops 52982943 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 2.858505 # Nu
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sim_ticks 2858505242500 # Number of ticks simulated
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final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 187730 # Simulator instruction rate (inst/s)
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host_op_rate 226980 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4795719535 # Simulator tick rate (ticks/s)
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host_mem_usage 583724 # Number of bytes of host memory used
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host_seconds 596.05 # Real time elapsed on the host
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host_inst_rate 171882 # Simulator instruction rate (inst/s)
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host_op_rate 207819 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4390877747 # Simulator tick rate (ticks/s)
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host_mem_usage 578076 # Number of bytes of host memory used
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host_seconds 651.01 # Real time elapsed on the host
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sim_insts 111897168 # Number of instructions simulated
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sim_ops 135292215 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu
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sim_ticks 2832862976500 # Number of ticks simulated
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final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 87854 # Simulator instruction rate (inst/s)
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host_op_rate 106560 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2200515158 # Simulator tick rate (ticks/s)
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host_mem_usage 584732 # Number of bytes of host memory used
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host_seconds 1287.36 # Real time elapsed on the host
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host_inst_rate 92547 # Simulator instruction rate (inst/s)
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host_op_rate 112251 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2318051416 # Simulator tick rate (ticks/s)
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host_mem_usage 579360 # Number of bytes of host memory used
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host_seconds 1222.09 # Real time elapsed on the host
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sim_insts 113100501 # Number of instructions simulated
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sim_ops 137180951 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu
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sim_ticks 2832862976500 # Number of ticks simulated
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final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 118929 # Simulator instruction rate (inst/s)
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host_op_rate 144250 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2978848657 # Simulator tick rate (ticks/s)
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host_mem_usage 586012 # Number of bytes of host memory used
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host_seconds 950.99 # Real time elapsed on the host
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host_inst_rate 116306 # Simulator instruction rate (inst/s)
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host_op_rate 141069 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2913147103 # Simulator tick rate (ticks/s)
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host_mem_usage 578076 # Number of bytes of host memory used
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host_seconds 972.44 # Real time elapsed on the host
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sim_insts 113100501 # Number of instructions simulated
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sim_ops 137180951 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 51.660653 # Nu
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sim_ticks 51660652947000 # Number of ticks simulated
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final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 286668 # Simulator instruction rate (inst/s)
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host_op_rate 336848 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 15934426663 # Simulator tick rate (ticks/s)
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host_mem_usage 682904 # Number of bytes of host memory used
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host_seconds 3242.08 # Real time elapsed on the host
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host_inst_rate 260799 # Simulator instruction rate (inst/s)
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host_op_rate 306450 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 14496494193 # Simulator tick rate (ticks/s)
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host_mem_usage 677256 # Number of bytes of host memory used
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host_seconds 3563.67 # Real time elapsed on the host
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sim_insts 929398934 # Number of instructions simulated
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sim_ops 1092086880 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 51.327140 # Nu
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sim_ticks 51327139864000 # Number of ticks simulated
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final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 109720 # Simulator instruction rate (inst/s)
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host_op_rate 128923 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6639754669 # Simulator tick rate (ticks/s)
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host_mem_usage 687008 # Number of bytes of host memory used
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host_seconds 7730.28 # Real time elapsed on the host
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host_inst_rate 134762 # Simulator instruction rate (inst/s)
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host_op_rate 158348 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 8155197699 # Simulator tick rate (ticks/s)
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host_mem_usage 681612 # Number of bytes of host memory used
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host_seconds 6293.79 # Real time elapsed on the host
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sim_insts 848164321 # Number of instructions simulated
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sim_ops 996610207 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 51.327140 # Nu
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sim_ticks 51327139864000 # Number of ticks simulated
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final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 139449 # Simulator instruction rate (inst/s)
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host_op_rate 163855 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 8438816943 # Simulator tick rate (ticks/s)
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host_mem_usage 688284 # Number of bytes of host memory used
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host_seconds 6082.27 # Real time elapsed on the host
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host_inst_rate 181298 # Simulator instruction rate (inst/s)
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host_op_rate 213029 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 10971364807 # Simulator tick rate (ticks/s)
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host_mem_usage 680328 # Number of bytes of host memory used
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host_seconds 4678.28 # Real time elapsed on the host
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sim_insts 848164321 # Number of instructions simulated
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sim_ops 996610207 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu
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sim_ticks 51111167216500 # Number of ticks simulated
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final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1195823 # Simulator instruction rate (inst/s)
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host_op_rate 1405350 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 62227318824 # Simulator tick rate (ticks/s)
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host_mem_usage 678332 # Number of bytes of host memory used
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host_seconds 821.36 # Real time elapsed on the host
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host_inst_rate 1222140 # Simulator instruction rate (inst/s)
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host_op_rate 1436279 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 63596815146 # Simulator tick rate (ticks/s)
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host_mem_usage 673192 # Number of bytes of host memory used
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host_seconds 803.68 # Real time elapsed on the host
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sim_insts 982203438 # Number of instructions simulated
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sim_ops 1154301153 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu
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sim_ticks 51111167216500 # Number of ticks simulated
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final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1114977 # Simulator instruction rate (inst/s)
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host_op_rate 1310339 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 58020354238 # Simulator tick rate (ticks/s)
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host_mem_usage 675736 # Number of bytes of host memory used
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host_seconds 880.92 # Real time elapsed on the host
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host_inst_rate 1142928 # Simulator instruction rate (inst/s)
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host_op_rate 1343188 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 59474849541 # Simulator tick rate (ticks/s)
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host_mem_usage 670860 # Number of bytes of host memory used
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host_seconds 859.37 # Real time elapsed on the host
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sim_insts 982203438 # Number of instructions simulated
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sim_ops 1154301153 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 51.759374 # Nu
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sim_ticks 51759374264500 # Number of ticks simulated
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final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 729832 # Simulator instruction rate (inst/s)
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host_op_rate 857659 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 45135767006 # Simulator tick rate (ticks/s)
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host_mem_usage 675484 # Number of bytes of host memory used
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host_seconds 1146.75 # Real time elapsed on the host
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host_inst_rate 790659 # Simulator instruction rate (inst/s)
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host_op_rate 929140 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 48897567060 # Simulator tick rate (ticks/s)
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host_mem_usage 670860 # Number of bytes of host memory used
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host_seconds 1058.53 # Real time elapsed on the host
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sim_insts 836933434 # Number of instructions simulated
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sim_ops 983519389 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 5.230834 # Nu
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sim_ticks 5230834315000 # Number of ticks simulated
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final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 185450 # Simulator instruction rate (inst/s)
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host_op_rate 366593 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2377836678 # Simulator tick rate (ticks/s)
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host_mem_usage 757080 # Number of bytes of host memory used
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host_seconds 2199.83 # Real time elapsed on the host
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host_inst_rate 207627 # Simulator instruction rate (inst/s)
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host_op_rate 410431 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2662189440 # Simulator tick rate (ticks/s)
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host_mem_usage 751184 # Number of bytes of host memory used
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host_seconds 1964.86 # Real time elapsed on the host
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sim_insts 407959263 # Number of instructions simulated
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sim_ops 806441023 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -4,11 +4,11 @@ sim_seconds 5.220167 # Nu
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sim_ticks 5220166723500 # Number of ticks simulated
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final_tick 5220166723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 149296 # Simulator instruction rate (inst/s)
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host_op_rate 289896 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5158950187 # Simulator tick rate (ticks/s)
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host_mem_usage 785372 # Number of bytes of host memory used
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host_seconds 1011.87 # Real time elapsed on the host
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host_inst_rate 281505 # Simulator instruction rate (inst/s)
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host_op_rate 546613 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 9727443238 # Simulator tick rate (ticks/s)
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host_mem_usage 784792 # Number of bytes of host memory used
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host_seconds 536.64 # Real time elapsed on the host
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sim_insts 151067812 # Number of instructions simulated
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sim_ops 293336428 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -1,251 +0,0 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.233778 # Number of seconds simulated
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sim_ticks 4467555024 # Number of ticks simulated
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final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 2000000000 # Frequency of simulated ticks
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host_inst_rate 1658224 # Simulator instruction rate (inst/s)
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host_op_rate 1658876 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3324623 # Simulator tick rate (ticks/s)
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host_mem_usage 518260 # Number of bytes of host memory used
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host_seconds 1343.78 # Real time elapsed on the host
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sim_insts 2228284650 # Number of instructions simulated
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sim_ops 2229160714 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 2 # Clock period in ticks
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system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
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system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
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system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
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system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
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system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s)
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system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s)
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system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s)
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system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s)
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system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
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system.nvram.bytes_read::total 284 # Number of bytes read from this memory
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system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
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system.nvram.bytes_written::total 92 # Number of bytes written to this memory
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system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
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system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
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system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
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system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
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system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s)
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system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s)
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system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s)
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system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
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system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
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system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
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system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
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system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
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system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
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system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
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system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
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system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
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system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
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system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
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system.physmem0.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
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system.physmem0.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
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system.physmem0.bytes_read::total 709825348 # Number of bytes read from this memory
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system.physmem0.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
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system.physmem0.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
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system.physmem0.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
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system.physmem0.bytes_written::total 15400223 # Number of bytes written to this memory
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system.physmem0.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
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system.physmem0.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
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system.physmem0.num_reads::total 165224885 # Number of read requests responded to by this memory
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system.physmem0.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
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system.physmem0.num_writes::total 1927067 # Number of write requests responded to by this memory
|
||||
system.physmem0.num_other::cpu.data 14 # Number of other requests responded to by this memory
|
||||
system.physmem0.num_other::total 14 # Number of other requests responded to by this memory
|
||||
system.physmem0.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem0.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem0.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem1.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
|
||||
system.physmem1.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
|
||||
system.physmem1.bytes_read::total 9813991967 # Number of bytes read from this memory
|
||||
system.physmem1.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem1.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem1.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
|
||||
system.physmem1.bytes_written::total 897268422 # Number of bytes written to this memory
|
||||
system.physmem1.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
|
||||
system.physmem1.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
|
||||
system.physmem1.num_reads::total 2403489130 # Number of read requests responded to by this memory
|
||||
system.physmem1.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem1.num_writes::total 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem1.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem1.num_other::total 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem1.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem1.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem1.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
|
||||
system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 2 # Clock period in ticks
|
||||
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 2228284650 # Number of instructions committed
|
||||
system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 44037246 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1839325658 # number of integer instructions
|
||||
system.cpu.num_fp_insts 14608322 # number of float instructions
|
||||
system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 547951940 # number of memory refs
|
||||
system.cpu.num_load_insts 349807670 # Number of load instructions
|
||||
system.cpu.num_store_insts 198144270 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2233777513 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 441057355 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 49673656 2.22% 2.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1619015933 72.49% 74.71% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 0 0.00% 74.71% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 74.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 8419779 0.38% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 356274529 15.95% 91.04% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 200199782 8.96% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2233583679 # Class of executed instruction
|
||||
system.iobus.trans_dist::ReadReq 4348554 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 4348554 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 7569 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteResp 7569 # Transaction distribution
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_membnks.pio 40 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_1.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_1.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_2.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_3.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_4.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_jbi.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.puart0.pio 29218 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.hvuart.pio 36 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.disk0.pio 8682882 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::total 8712246 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_membnks.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_1.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_2.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_3.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_4.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_1.pio 16 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_2.pio 16 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_3.pio 16 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_4.pio 16 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_jbi.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.puart0.pio 14609 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.hvuart.pio 18 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.disk0.pio 34731524 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::total 34746591 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadReq 2573267624 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2573267624 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 189322556 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 189322556 # Transaction distribution
|
||||
system.membus.trans_dist::SwapReq 5403081 # Transaction distribution
|
||||
system.membus.trans_dist::SwapResp 5403081 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.rom.port 216148 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem0.port 306145662 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem1.port 4159053420 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::total 4465415230 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.t1000.iob.pio 64 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.t1000.htod.pio 32 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.bridge.slave 8712246 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.rom.port 174098 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.nvram.port 752 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.hypervisor_desc.port 18048 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.partition_desc.port 1216 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem0.port 28158270 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem1.port 1033506566 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::total 1070571292 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5535986522 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.rom.port 432296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem0.port 612291324 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem1.port 8318106840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::total 8930830460 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.t1000.iob.pio 256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.t1000.htod.pio 128 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.bridge.slave 34746591 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.rom.port 696392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.nvram.port 376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.hypervisor_desc.port 16792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.partition_desc.port 4846 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem0.port 112934471 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem1.port 2454584131 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::total 2602983983 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 11533814443 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2767993261 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.806616 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.394951 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 535285646 19.34% 19.34% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2232707615 80.66% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2767993261 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,879 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.061235 # Number of seconds simulated
|
||||
sim_ticks 61234797500 # Number of ticks simulated
|
||||
final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 283902 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 285316 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 191877896 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 404856 # Number of bytes of host memory used
|
||||
host_seconds 319.13 # Real time elapsed on the host
|
||||
sim_insts 90602850 # Number of instructions simulated
|
||||
sim_ops 91054081 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 996672 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15573 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 807907 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 15468329 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 16276236 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 807907 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 807907 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 807907 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 15468329 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 16276236 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 15573 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 15573 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 996672 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 996672 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 993 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 890 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 949 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 1027 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 1087 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 962 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 938 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 904 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 867 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 876 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 906 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 61234703000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 15573 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1535 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 648.213681 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 443.714701 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 401.012846 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 241 15.70% 15.70% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 186 12.12% 27.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 88 5.73% 33.55% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 73 4.76% 38.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 71 4.63% 42.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 84 5.47% 48.40% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 36 2.35% 50.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 51 3.32% 54.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 705 45.93% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1535 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 72594750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 364588500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 77865000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 4661.58 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 23411.58 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.13 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 14028 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 90.08 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 3932107.04 # Average gap between requests
|
||||
system.physmem.pageHitRate 90.08 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 63679200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 2519893620 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 34528365000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 41120963895 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 671.567381 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 57430990750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 2044640000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1755713000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 2548962765 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 34502857500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 41116813260 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 671.499745 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 57389143250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 2044640000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 20750031 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 8954908 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 8830467 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 98.610360 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 61988 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 26205 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.numCycles 122469595 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 90602850 # Number of instructions committed
|
||||
system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.351719 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.739799 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 91054081 # Class of committed instruction
|
||||
system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 946097 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26254404 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26254404 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26254912 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26254912 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 914926 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 914926 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 74289 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 74289 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 989215 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 989215 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 989219 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 989219 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919140000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11919140000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2539899500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2539899500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14459039500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14459039500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14459039500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14459039500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22508638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22508638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 27243619 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 27243619 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 27244131 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 27244131 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040648 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.040648 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015689 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.015689 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.036310 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.036310 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.436099 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.436099 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34189.442582 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34189.442582 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14616.680398 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14616.680398 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14616.621294 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14616.621294 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 943278 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11500 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 11500 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27525 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 27525 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 39025 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 39025 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903426 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 903426 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 950190 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865506000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865506000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1480423500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1480423500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345929500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12345929500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346086000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12346086000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040137 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040137 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034878 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034878 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034877 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12027.001658 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12027.001658 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 5 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.336476 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.336476 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 27766889 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 27766889 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 27766889 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 801 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60228000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 60228000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 60228000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 60228000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 60228000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 60228000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 27767690 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 27767690 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 27767690 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 27767690 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 27767690 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 27767690 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75191.011236 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 75191.011236 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 75191.011236 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 75191.011236 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 5 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 5 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59427000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 59427000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59427000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 59427000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59427000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 59427000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.453494 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.285496 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020572 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.312643 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15556 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1096 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903167 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 903167 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 935387 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 935413 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 935387 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 935413 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 775 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 775 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 262 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 262 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 775 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 775 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15581 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1066480500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1066480500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57929500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 57929500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22043500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 22043500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 57929500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1088524000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1146453500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 57929500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1088524000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1146453500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 943278 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 943278 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903429 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 903429 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 950193 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 950994 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 950193 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 950994 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.967541 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.967541 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967541 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967541 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73327.867162 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73327.867162 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74747.741935 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74747.741935 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84135.496183 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84135.496183 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74747.741935 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73580.225916 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74747.741935 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73580.225916 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15573 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15573 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 921040500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 921040500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50052500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50052500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19092500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19092500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50052500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 940133000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 990185500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50052500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 940133000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 990185500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016375 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016375 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63327.867162 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63327.867162 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64750.970246 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64750.970246 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846483 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2848090 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 950994 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 950828 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 950994 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1891831000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1202498 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1029 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1029 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31146 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 31146 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 996672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 15573 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 15573 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15573 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 21737000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 82128750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,520 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.361598 # Number of seconds simulated
|
||||
sim_ticks 361597758500 # Number of ticks simulated
|
||||
final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1238958 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1239009 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1837400352 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 383872 # Number of bytes of host memory used
|
||||
host_seconds 196.80 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 723195517 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 243825150 # Number of instructions committed
|
||||
system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 194726494 # number of integer instructions
|
||||
system.cpu.num_fp_insts 11630 # number of float instructions
|
||||
system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 105711441 # number of memory refs
|
||||
system.cpu.num_load_insts 82803521 # Number of load instructions
|
||||
system.cpu.num_store_insts 22907920 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 29302884 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 244431613 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 935266 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 25 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 244420617 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 882 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 25 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 25 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 15603 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15603 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,515 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.366199 # Number of seconds simulated
|
||||
sim_ticks 366199170500 # Number of ticks simulated
|
||||
final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 703769 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1239225 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1631255376 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 410416 # Number of bytes of host memory used
|
||||
host_seconds 224.49 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6528 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 102 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 732398341 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 157988548 # Number of instructions committed
|
||||
system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 8475189 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 278169482 # number of integer instructions
|
||||
system.cpu.num_fp_insts 40 # number of float instructions
|
||||
system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 122219137 # number of memory refs
|
||||
system.cpu.num_load_insts 90779385 # Number of load instructions
|
||||
system.cpu.num_store_insts 31439752 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 29309705 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 278192465 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 120152370 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2062482 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 24 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 217695356 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 808 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 24 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 24 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 313 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960503 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1960503 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2037588 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2037593 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2037588 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2037593 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 217 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 217 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 29241 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 30044 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 30044 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 808 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1960720 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000111 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000111 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014148 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.014531 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 102 # number of writebacks
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 29241 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 30044 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 313 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1020 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 102 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 14 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 30160 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 30160 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,803 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.412080 # Number of seconds simulated
|
||||
sim_ticks 412079966500 # Number of ticks simulated
|
||||
final_tick 412079966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 367276 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 367276 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 247338871 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254928 # Number of bytes of host memory used
|
||||
host_seconds 1666.05 # Real time elapsed on the host
|
||||
sim_insts 611901617 # Number of instructions simulated
|
||||
sim_ops 611901617 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 156608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 24143296 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 24299904 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 156608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 156608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 18790848 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 18790848 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2447 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 377239 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 379686 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 293607 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 293607 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 380043 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 58588861 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 58968904 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 380043 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 380043 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 45600004 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 45600004 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 45600004 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 380043 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 58588861 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 104568908 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 379686 # Number of read requests accepted
|
||||
system.physmem.writeReqs 293607 # Number of write requests accepted
|
||||
system.physmem.readBursts 379686 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 293607 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 24278080 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 21824 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 18789376 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 24299904 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 18790848 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 341 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 23685 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 23156 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 23444 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 24498 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 25450 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 23569 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 23652 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 23913 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 23182 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 23988 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 24719 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 22783 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 23722 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 24391 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 22743 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 22450 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 17782 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 17456 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 17945 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 18853 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 19514 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 18590 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 18778 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 18659 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 18440 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 18941 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 19257 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 18049 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 18261 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 18732 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 17196 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 17131 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 412079864500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 379686 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 293607 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 377956 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1374 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 6977 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 7349 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 16982 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 17402 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 17456 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 17496 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 17482 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 17480 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 17464 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 17469 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 17515 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 17450 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 17520 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 17545 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 17504 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 17668 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 17405 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 17352 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 142401 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 302.436977 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 179.883041 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 323.731419 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 50699 35.60% 35.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 38890 27.31% 62.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 13190 9.26% 72.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 8518 5.98% 78.16% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 5731 4.02% 82.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 3813 2.68% 84.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 2946 2.07% 86.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 2544 1.79% 88.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 16070 11.29% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 142401 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 17327 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 21.892595 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 236.629202 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 17319 99.95% 99.95% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 17327 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 17327 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.943729 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.871773 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 3.342990 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16-23 17278 99.72% 99.72% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::24-31 33 0.19% 99.91% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::32-39 6 0.03% 99.94% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::40-47 2 0.01% 99.95% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::48-55 2 0.01% 99.97% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::56-63 2 0.01% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::72-79 1 0.01% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::96-103 1 0.01% 99.99% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::112-119 1 0.01% 99.99% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::392-399 1 0.01% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 17327 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 4062204500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11174923250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1896725000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 10708.47 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 29458.47 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 58.92 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 45.60 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 58.97 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 45.60 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.82 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 21.44 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 314203 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 216323 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 612036.46 # Average gap between requests
|
||||
system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 547933680 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 298971750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1492662600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 956298960 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 62025350850 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 192839650500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 285075897780 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 691.797872 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 320257941500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 13760240000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 78061587250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 528617880 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 288432375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1466212800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 946125360 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 58968919935 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 195520730250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 284634068040 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 690.725678 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 324739070000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 13760240000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 73580458750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 123917421 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 87658943 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 6214661 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 71578372 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 67267052 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 93.976784 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 15041989 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 1126026 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 7056 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 4451 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 2605 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 734 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 149344684 # DTB read hits
|
||||
system.cpu.dtb.read_misses 549067 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 149893751 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 57319581 # DTB write hits
|
||||
system.cpu.dtb.write_misses 63710 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 57383291 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 206664265 # DTB hits
|
||||
system.cpu.dtb.data_misses 612777 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 207277042 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 226050668 # ITB hits
|
||||
system.cpu.itb.fetch_misses 48 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 226050716 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 485 # Number of system calls
|
||||
system.cpu.numCycles 824159933 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 611901617 # Number of instructions committed
|
||||
system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 12834895 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.346883 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.742455 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 52179272 8.53% 8.53% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 355264620 58.06% 66.59% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 152833 0.02% 66.61% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 66.61% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 144588 0.02% 66.64% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 3 0.00% 66.64% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 369991 0.06% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 2 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 3790 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.70% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 146565535 23.95% 90.65% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 57220983 9.35% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 611901617 # Class of committed instruction
|
||||
system.cpu.tickCycles 739333991 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 84825942 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 2535268 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4087.644038 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 202570428 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2539364 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 79.772111 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1636792500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.644038 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997960 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997960 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 414584966 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 414584966 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 146904269 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 146904269 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 55666159 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 55666159 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 202570428 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 202570428 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 202570428 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 202570428 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1908498 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1908498 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1543875 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1543875 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3452373 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3452373 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3452373 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3452373 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 37718879500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 37718879500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 47736374000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 47736374000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 85455253500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 85455253500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 85455253500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 85455253500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 148812767 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 148812767 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 206022801 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 206022801 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 206022801 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 206022801 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012825 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026986 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.026986 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.016757 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.016757 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.016757 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.016757 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19763.646333 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19763.646333 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30919.843899 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30919.843899 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24752.613203 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 24752.613203 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24752.613203 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 24752.613203 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 2339413 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2339413 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143957 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 143957 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769052 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 769052 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 913009 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 913009 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 913009 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 913009 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764541 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1764541 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774823 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 774823 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2539364 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2539364 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2539364 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2539364 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33202779000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33202779000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23350926000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 23350926000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56553705000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 56553705000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56553705000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 56553705000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011857 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011857 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012326 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.012326 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012326 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.012326 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18816.666204 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18816.666204 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30137.110024 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30137.110024 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 3158 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1117.678366 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 226045682 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4986 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 45336.077417 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1117.678366 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.545741 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.545741 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1828 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 452106322 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 452106322 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 226045682 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 226045682 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 226045682 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 226045682 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 226045682 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 226045682 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4986 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4986 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4986 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4986 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4986 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4986 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 233628500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 233628500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 233628500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 233628500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 233628500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 233628500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 226050668 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 226050668 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 226050668 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 226050668 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 226050668 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 226050668 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46856.899318 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 46856.899318 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 46856.899318 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 46856.899318 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 46856.899318 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 46856.899318 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 3158 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 3158 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4986 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4986 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4986 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4986 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4986 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4986 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 228642500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 228642500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 228642500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 228642500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228642500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 228642500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45856.899318 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45856.899318 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 347705 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29504.977164 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3908748 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 380135 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 10.282526 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 189119343500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 21322.016390 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.931124 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8022.029650 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.650696 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004911 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.244813 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.900420 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32430 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13172 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18756 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989685 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 41820503 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 41820503 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 2339413 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 2339413 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 3158 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 3158 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 571852 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 571852 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2539 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 2539 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590273 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1590273 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2539 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2162125 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2164664 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 2539 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2162125 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2164664 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 206308 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 206308 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2447 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2447 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 170931 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 170931 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2447 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 377239 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 379686 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2447 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 377239 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 379686 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16226611500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 16226611500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194481500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 194481500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13777909500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13777909500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 194481500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 30004521000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30199002500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 194481500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 30004521000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30199002500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2339413 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 2339413 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 3158 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 3158 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 778160 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 778160 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4986 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 4986 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1761204 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1761204 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 4986 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2539364 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2544350 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 4986 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2539364 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2544350 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265123 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.265123 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.490774 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.490774 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.097053 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.097053 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490774 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.148556 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.149227 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490774 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.148556 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.149227 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78652.362002 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78652.362002 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79477.523498 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79477.523498 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80605.095038 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80605.095038 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79477.523498 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79537.166094 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 79536.781709 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79477.523498 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79537.166094 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 79536.781709 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 293607 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 293607 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 5 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 5 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206308 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 206308 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2447 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2447 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 170931 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 170931 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2447 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 377239 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 379686 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2447 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 377239 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 379686 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14163531500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14163531500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 170011500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 170011500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12068599500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12068599500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170011500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26232131000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26402142500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170011500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26232131000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26402142500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265123 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265123 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.490774 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097053 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097053 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.149227 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.149227 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68652.362002 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68652.362002 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69477.523498 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69477.523498 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70605.095038 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70605.095038 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69477.523498 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69537.166094 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69536.781709 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69477.523498 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69537.166094 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69536.781709 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5082776 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538426 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2394 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2394 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1766190 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 2633020 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 3158 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 249953 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 778160 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 778160 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4986 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761204 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13130 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7613996 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7627126 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 521216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312241728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 312762944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 347705 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2892055 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000828 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.028759 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2889661 99.92% 99.92% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2394 0.08% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2892055 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4883959000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7479000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3809046000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 173378 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 51709 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 206308 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 206308 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 173378 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104688 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1104688 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43090752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 43090752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 725002 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 725002 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 725002 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 2021006000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2009290500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,921 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.362632 # Number of seconds simulated
|
||||
sim_ticks 362631828500 # Number of ticks simulated
|
||||
final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 263885 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 285822 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188900227 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275012 # Number of bytes of host memory used
|
||||
host_seconds 1919.70 # Real time elapsed on the host
|
||||
sim_insts 506579366 # Number of instructions simulated
|
||||
sim_ops 548692589 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 179456 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6221440 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6221440 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2804 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 141126 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 143930 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 97210 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 97210 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 494871 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 24906981 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 25401852 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 494871 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 494871 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 17156354 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 17156354 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 17156354 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 494871 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 24906981 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42558206 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 143930 # Number of read requests accepted
|
||||
system.physmem.writeReqs 97210 # Number of write requests accepted
|
||||
system.physmem.readBursts 143930 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 97210 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 9204736 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 6219456 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 9211520 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 6221440 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 9406 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 8921 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 8949 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 8657 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 9384 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 9355 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 8962 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 8101 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 8596 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 8628 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 8740 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 9454 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 9340 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 9510 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 8709 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 9112 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 6249 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 6105 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 6032 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 5882 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 6237 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 6240 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 6051 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 5508 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 5781 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 5861 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 5978 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 6494 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 6355 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 6320 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 6000 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 6086 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 362631802500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 143930 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 97210 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 143484 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 320 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 2964 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 3137 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 5692 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 5705 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 5705 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 5703 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 5710 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 5731 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 5739 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 5733 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 5740 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 5717 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 5686 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 5684 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 5636 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 5622 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 65461 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 235.617299 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 156.242018 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 241.589954 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 24858 37.97% 37.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 18413 28.13% 66.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 6961 10.63% 76.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 7914 12.09% 88.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2009 3.07% 91.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1136 1.74% 93.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 792 1.21% 94.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 657 1.00% 95.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 2721 4.16% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 65461 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 25.630191 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 380.618779 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 17.319373 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 17.223479 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 2.351913 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16-17 2643 47.10% 47.10% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18-19 2820 50.26% 97.36% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20-21 52 0.93% 98.29% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22-23 28 0.50% 98.79% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::24-25 21 0.37% 99.16% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::26-27 8 0.14% 99.30% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::30-31 9 0.16% 99.57% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::32-33 4 0.07% 99.64% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::34-35 6 0.11% 99.75% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::36-37 5 0.09% 99.84% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::40-41 1 0.02% 99.86% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::42-43 3 0.05% 99.91% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::44-45 2 0.04% 99.95% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::70-71 1 0.02% 99.96% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::90-91 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 1538291500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 4234991500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 719120000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 10695.65 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 29445.65 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 25.38 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 17.15 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 25.40 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 17.16 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.33 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 19.56 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 110801 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 64737 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 77.04 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 66.60 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1503822.69 # Average gap between requests
|
||||
system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 249185160 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 135964125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 559455000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 312906240 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 47417547600 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 175983265500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 248343488505 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 684.841129 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 292457177000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 12108980000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 58063198250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 245586600 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 134000625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 562138200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 316684080 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 46768401675 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 176552684250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 248264660310 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 684.623774 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 293406599500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 12108980000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 131880511 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 68420287 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 60518878 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 88.451658 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 9982385 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 18500 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 3889648 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 3881527 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 725263657 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 506579366 # Number of instructions committed
|
||||
system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.431688 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.698476 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 548692589 # Class of committed instruction
|
||||
system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 1141477 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168012891 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168012891 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168015632 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168015632 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 855770 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 855770 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 701221 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 701221 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1556991 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1556991 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1557007 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1557007 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14058873500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 14058873500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21921294000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21921294000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 35980167500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 35980167500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 35980167500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 35980167500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 115330833 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 115330833 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2757 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 2757 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 169569882 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 169569882 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 169572639 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 169572639 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007420 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.007420 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012928 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.012928 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005803 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.005803 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.009182 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.009182 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.009182 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.009182 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.331795 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.331795 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31261.605115 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 31261.605115 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.783224 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23108.783224 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23108.545755 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1069336 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 66650 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344781 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 344781 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 411431 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 411431 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 411431 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 411431 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789120 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 789120 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356440 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 356440 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1145560 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1145560 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1145573 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1145573 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372328000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12372328000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11135047500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11135047500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1042000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1042000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23507375500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23507375500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23508417500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23508417500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006842 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006842 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006572 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006572 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004715 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004715 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006756 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006756 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.639497 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.639497 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 18130 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.579303 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 198770599 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 198770599 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 198770599 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 20001 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 20001 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 20001 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 20001 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 20001 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 20001 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 455038500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 455038500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 455038500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 455038500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 455038500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 455038500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 198790600 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 198790600 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 198790600 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 198790600 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 198790600 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 198790600 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22750.787461 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22750.787461 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22750.787461 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22750.787461 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 18130 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 18130 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20001 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 20001 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 20001 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 20001 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 20001 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 20001 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435037500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 435037500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435037500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 435037500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435037500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 435037500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 112376 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3819.558908 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.717181 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009423 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.116564 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.843168 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31212 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 17893 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 255742 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 255742 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17196 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 17196 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748691 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 748691 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 17196 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1004433 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1021629 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 17196 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1004433 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1021629 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 100949 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 100949 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2805 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2805 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40191 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 40191 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2805 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 141140 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 143945 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2805 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 141140 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 143945 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7917540500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 7917540500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 223778500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 223778500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3305085000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3305085000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 223778500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 11222625500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 11446404000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 223778500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 11222625500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 11446404000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1069336 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1069336 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 17893 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 17893 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356691 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 356691 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20001 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 20001 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788882 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 788882 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 20001 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1145573 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1165574 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 20001 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1145573 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1165574 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283015 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.283015 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140243 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140243 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050947 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050947 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140243 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.123205 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.123497 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140243 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.123205 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.123497 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78431.093919 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78431.093919 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79778.431373 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79778.431373 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82234.455475 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82234.455475 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 79519.288617 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 79519.288617 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 97210 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100949 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 100949 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2804 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2804 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40177 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40177 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2804 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 141126 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 143930 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2804 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 141126 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 143930 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6908050500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6908050500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195670500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195670500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2902356000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2902356000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195670500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9810406500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 10006077000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195670500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9810406500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 10006077000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283015 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283015 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140193 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050929 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050929 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123484 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123484 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68431.093919 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68431.093919 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69782.631954 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69782.631954 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58132 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432623 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3490755 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141754176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 144194560 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 112376 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1277950 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.006008 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.077309 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1270275 99.40% 99.40% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 7672 0.60% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1277950 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2250056500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 30027947 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 42981 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 12558 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 100949 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 100949 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 42981 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397628 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 397628 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15432960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 15432960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 253698 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 253698 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 253698 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 685564500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 763995250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,243 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.279361 # Number of seconds simulated
|
||||
sim_ticks 279360903000 # Number of ticks simulated
|
||||
final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 505182 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 547179 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 278590581 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293956 # Number of bytes of host memory used
|
||||
host_seconds 1002.77 # Real time elapsed on the host
|
||||
sim_insts 506578818 # Number of instructions simulated
|
||||
sim_ops 548692039 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 558721807 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 506578818 # Number of instructions committed
|
||||
system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 448447005 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 749023756 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 172743505 # number of memory refs
|
||||
system.cpu.num_load_insts 115883283 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860222 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 121552863 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 548692589 # Class of executed instruction
|
||||
system.membus.trans_dist::ReadReq 630707528 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 632196069 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 54239049 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 54239049 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution
|
||||
system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 687926230 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.750965 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.432454 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 171317644 24.90% 24.90% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 516608586 75.10% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 687926230 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,658 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.708539 # Number of seconds simulated
|
||||
sim_ticks 708539449500 # Number of ticks simulated
|
||||
final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 973862 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1054649 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1366418821 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273224 # Number of bytes of host memory used
|
||||
host_seconds 518.54 # Real time elapsed on the host
|
||||
sim_insts 504984064 # Number of instructions simulated
|
||||
sim_ops 546875315 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 1417078899 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 504984064 # Number of instructions committed
|
||||
system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 448447005 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 748339662 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 172743505 # number of memory refs
|
||||
system.cpu.num_load_insts 115883283 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860222 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 121552863 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 548692589 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 1136276 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 167197620 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 167197620 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 167200190 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 167200190 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 783863 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 783863 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 356508 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 356508 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1140371 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1140372 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168337991 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168337991 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168340562 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168340562 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.006870 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.006573 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1065708 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 516597066 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 516608587 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 516608587 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 516608587 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 9788 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 9788 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 110394 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2303 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39273 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 39273 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2303 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 140061 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 142364 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 142364 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 356508 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 783864 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1140372 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1151893 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 96330 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993059500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993059500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114202000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114202000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946729000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 110394 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 41576 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 11920 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 100788 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 100788 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 250615 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 250615 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,127 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.885773 # Number of seconds simulated
|
||||
sim_ticks 885772926000 # Number of ticks simulated
|
||||
final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 376226 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 696207 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 403037674 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304140 # Number of bytes of host memory used
|
||||
host_seconds 2197.74 # Real time elapsed on the host
|
||||
sim_insts 826847304 # Number of instructions simulated
|
||||
sim_ops 1530082521 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 8546485088 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 8546485088 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 991837474 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 991837474 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1068310636 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 384083342 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1452393978 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 149158211 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 149158211 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 9648618554 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2580263190 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12228881744 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 9648618554 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 9648618554 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1119742368 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1119742368 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 1771545853 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 826847304 # Number of instructions committed
|
||||
system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1527470226 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 533241508 # number of memory refs
|
||||
system.cpu.num_load_insts 384083313 # Number of load instructions
|
||||
system.cpu.num_store_insts 149158195 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1771545852.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 149981740 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1530082521 # Class of executed instruction
|
||||
system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 149158211 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 149158211 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::total 2136621272 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3203104378 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::total 8546485088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 11823849838 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.667047 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 533241553 33.30% 33.30% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 1068310636 66.70% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1601552189 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,521 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.650501 # Number of seconds simulated
|
||||
sim_ticks 1650501252500 # Number of ticks simulated
|
||||
final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 691787 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1280153 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1380901785 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 282548 # Number of bytes of host memory used
|
||||
host_seconds 1195.23 # Real time elapsed on the host
|
||||
sim_insts 826847304 # Number of instructions simulated
|
||||
sim_ops 1530082521 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 3301002505 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 826847304 # Number of instructions committed
|
||||
system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1527470226 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 533241508 # number of memory refs
|
||||
system.cpu.num_load_insts 384083313 # Number of load instructions
|
||||
system.cpu.num_store_insts 149158195 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 149981740 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1530082521 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 2517016 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 530720441 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2521112 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2325221 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1068307822 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 2814 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 1253 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1253 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 348438 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 380855 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 293208 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 348438 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 174499 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 206356 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 206356 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 727569 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 727569 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,762 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.223533 # Number of seconds simulated
|
||||
sim_ticks 223532962500 # Number of ticks simulated
|
||||
final_tick 223532962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 349202 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 349202 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 195799110 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 258576 # Number of bytes of host memory used
|
||||
host_seconds 1141.64 # Real time elapsed on the host
|
||||
sim_insts 398664665 # Number of instructions simulated
|
||||
sim_ops 398664665 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 249088 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 503680 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 249088 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 249088 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 3892 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7870 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1114323 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1138946 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2253269 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1114323 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1114323 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1114323 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1138946 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2253269 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7870 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 7870 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 503680 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 503680 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 548 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 675 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 473 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 633 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 474 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 477 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 562 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 560 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 471 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 437 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 354 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 323 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 430 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 556 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 473 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 424 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 223532875000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 7870 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 971 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1541 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 325.149903 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 194.496255 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 330.966466 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 538 34.91% 34.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 340 22.06% 56.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 192 12.46% 69.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 106 6.88% 76.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 56 3.63% 79.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 49 3.18% 83.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 40 2.60% 85.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 36 2.34% 88.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 184 11.94% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1541 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 51693000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 199255500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 39350000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6568.36 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25318.36 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 6320 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.30 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 28403160.74 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.30 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6751080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3683625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 34125000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 14599740480 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5792542920 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 129035577000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 149472420105 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.696853 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 214662823500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7464080000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1403552000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 26933400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 14599740480 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5529545775 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 129266276250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 149430056100 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.507329 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 215046035000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7464080000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1017823750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 45898041 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 26691639 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 566044 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 25194489 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 18810772 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 74.662249 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8282157 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 322 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 2248490 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 2235007 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 13483 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 95357145 # DTB read hits
|
||||
system.cpu.dtb.read_misses 114 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 95357259 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73594596 # DTB write hits
|
||||
system.cpu.dtb.write_misses 852 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73595448 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168951741 # DTB hits
|
||||
system.cpu.dtb.data_misses 966 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 168952707 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 96790867 # ITB hits
|
||||
system.cpu.itb.fetch_misses 1237 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 96792104 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 447065925 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 398664665 # Number of instructions committed
|
||||
system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2363843 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.121408 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.891736 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 141652567 35.53% 41.33% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 94754511 23.77% 81.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 73520765 18.44% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 398664665 # Class of committed instruction
|
||||
system.cpu.tickCycles 443407678 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3658247 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 771 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3291.617120 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 167826980 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40294.593037 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.617120 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.803617 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.803617 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 335672353 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 335672353 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94312181 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94312181 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73514799 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 167826980 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 167826980 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 167826980 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 167826980 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1183 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1183 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5931 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5931 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 7114 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7114 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 7114 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7114 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88520000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 88520000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 429316500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 429316500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 517836500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 517836500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 517836500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 517836500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94313364 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94313364 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 167834094 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 167834094 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 167834094 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 167834094 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74826.711750 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 74826.711750 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72385.179565 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 72385.179565 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72791.186393 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 72791.186393 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72791.186393 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 72791.186393 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 654 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 654 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 214 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 214 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2735 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2735 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2949 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2949 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2949 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2949 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 71272000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 71272000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239421000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 239421000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310693000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 310693000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310693000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 310693000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73552.115583 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73552.115583 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74912.703379 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74912.703379 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 3190 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1919.630000 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 96785699 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 5168 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18727.882933 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.630000 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.937319 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.937319 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 193586902 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 193586902 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 96785699 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 96785699 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 96785699 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 96785699 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 96785699 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 96785699 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 5168 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 5168 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 5168 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 5168 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5168 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5168 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 316704500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 316704500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 316704500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 316704500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 316704500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 316704500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 96790867 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 96790867 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 96790867 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 96790867 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 96790867 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 96790867 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61281.830495 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61281.830495 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61281.830495 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61281.830495 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61281.830495 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61281.830495 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 3190 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 3190 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5168 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 5168 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 5168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 5168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 5168 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 5168 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311536500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 311536500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311536500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 311536500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311536500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 311536500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60281.830495 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60281.830495 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4421.902302 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4798 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5270 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.910436 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 372.081904 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3407.854115 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 641.966284 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011355 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103999 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019591 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.134946 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5270 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4439 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160828 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 114820 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 114820 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 3190 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 3190 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1276 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1276 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1276 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1463 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1276 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1463 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3892 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 3892 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 841 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 841 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3892 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 7870 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3892 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7870 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234104000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 234104000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 290385500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 290385500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 68345000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 68345000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 290385500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 302449000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 592834500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 290385500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 302449000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 592834500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 3190 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 3190 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5168 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 5168 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 5168 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9333 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 5168 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9333 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753096 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753096 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753096 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.843244 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753096 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.843244 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.713420 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.713420 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74610.868448 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74610.868448 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81266.349584 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81266.349584 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74610.868448 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76030.417295 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75328.398983 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74610.868448 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76030.417295 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75328.398983 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3892 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3892 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 841 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 841 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3892 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7870 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3892 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7870 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 202734000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 202734000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 251465500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 251465500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59935000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59935000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251465500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262669000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 514134500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251465500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262669000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 514134500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753096 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843244 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843244 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.713420 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.713420 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64610.868448 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64610.868448 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71266.349584 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71266.349584 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 13294 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3961 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 6135 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 3190 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 5168 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13526 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 22627 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 534912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 843328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 9333 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 9333 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 9333 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10491000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7752000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 4733 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3137 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3137 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15740 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 15740 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 503680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 7870 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7870 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7870 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 9176500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 41781750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,534 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.567385 # Number of seconds simulated
|
||||
sim_ticks 567385356500 # Number of ticks simulated
|
||||
final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1272231 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1272231 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1810657439 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 257040 # Number of bytes of host memory used
|
||||
host_seconds 313.36 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 459136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 361518 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 447696 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 809214 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 361518 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 361518 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 94754490 # DTB read hits
|
||||
system.cpu.dtb.read_misses 21 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 94754511 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73520730 # DTB write hits
|
||||
system.cpu.dtb.write_misses 35 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73520765 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275220 # DTB hits
|
||||
system.cpu.dtb.data_misses 56 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 168275276 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 398664666 # ITB hits
|
||||
system.cpu.itb.fetch_misses 173 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 398664839 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 1134770713 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 398664609 # Number of instructions committed
|
||||
system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 316365921 # number of integer instructions
|
||||
system.cpu.num_fp_insts 155295119 # number of float instructions
|
||||
system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 168275276 # number of memory refs
|
||||
system.cpu.num_load_insts 94754511 # Number of load instructions
|
||||
system.cpu.num_store_insts 73520765 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1134770713 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 44587535 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 141652567 35.53% 41.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 94754511 23.77% 81.56% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 398664665 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.807028 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.802931 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.802931 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4152 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 52888500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 52888500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 195593000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 195593000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 248481500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 248481500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 248481500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 248481500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 192391000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 192391000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244329500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 244329500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244329500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 244329500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.084430 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.876506 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.876506 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 398660993 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 3673 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 204815000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 204815000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 204815000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 204815000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 204815000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 204815000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 1769 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1769 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 201142000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 201142000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 201142000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 201142000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 201142000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 201142000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 371.516873 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.363420 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 630.450105 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.115122 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1769 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 468 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 123 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 123 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 651 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3205 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 3205 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 827 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 827 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7174 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 186953000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 186953000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 190709000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 190709000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49213500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 49213500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 190709000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 236166500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 426875500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 190709000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 236166500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 426875500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1769 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 3673 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 950 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 950 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.872584 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.870526 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.870526 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3205 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3205 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 827 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 827 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 155533000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 155533000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 158659000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 158659000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40943500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40943500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158659000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 196476500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 355135500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158659000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 196476500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 355135500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.872584 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.870526 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 115 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 348288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 655552 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 7825 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 7825 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 7825 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7597000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 4032 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 7174 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7174 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7196500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 35870000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,882 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.211715 # Number of seconds simulated
|
||||
sim_ticks 211714953000 # Number of ticks simulated
|
||||
final_tick 211714953000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 196459 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 235871 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 152335465 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280176 # Number of bytes of host memory used
|
||||
host_seconds 1389.79 # Real time elapsed on the host
|
||||
sim_insts 273037857 # Number of instructions simulated
|
||||
sim_ops 327812214 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 485504 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1034750 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1258447 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2293197 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1034750 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1034750 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1034750 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1258447 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2293197 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7586 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 630 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 846 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 628 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 541 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 466 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 349 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 171 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 228 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 208 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 310 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 343 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 428 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 553 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 705 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 638 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 542 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 211714708500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 7586 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1530 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 316.067974 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 186.296863 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 330.878934 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 560 36.60% 36.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 363 23.73% 60.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 160 10.46% 70.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 74 4.84% 75.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 70 4.58% 80.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 59 3.86% 84.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 34 2.22% 86.27% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 28 1.83% 88.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 182 11.90% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1530 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 52630500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 194868000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6937.85 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25687.85 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 6048 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 79.73 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 27908609.08 # Average gap between requests
|
||||
system.physmem.pageHitRate 79.73 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 5080320 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 2772000 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5529396150 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 122174691000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 141569591070 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.700877 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 203247000500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7069400000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1392729000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 28992600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5726317185 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 122001953250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 141595000110 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.820896 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 202960400000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7069400000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1682763000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 32413931 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 16919661 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 738142 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 17496692 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 12856502 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 73.479615 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 6512761 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 2303892 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 2264485 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 39407 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 128263 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 423429906 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 273037857 # Number of instructions committed
|
||||
system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2127081 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.550810 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.644824 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 104312544 31.82% 31.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 327812214 # Class of committed instruction
|
||||
system.cpu.tickCycles 420106568 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3323338 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 1355 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3085.570959 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168654881 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37379.184619 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.570959 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.753313 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.753313 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 337328856 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 337328856 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86522107 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86522107 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 63533 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 63533 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168569558 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168569558 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168633091 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168633091 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 2060 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 2060 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 7286 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7286 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 7291 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7291 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 136635000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 136635000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 394688000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 394688000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 531323000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 531323000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 531323000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 531323000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86524167 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86524167 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63538 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 63538 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168576844 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168576844 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168640382 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168640382 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66327.669903 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 66327.669903 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75523.918867 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 75523.918867 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72923.826517 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 72923.826517 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72873.817035 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 72873.817035 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1010 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 4509 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109916500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109916500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219842000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 219842000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 481000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 481000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329758500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 329758500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330239500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 330239500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67063.148261 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67063.148261 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76600 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76600 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 160333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 160333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 38168 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1923.744161 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 69641436 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 40104 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1736.520946 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1923.744161 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939328 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.939328 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1483 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 139403186 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 139403186 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 69641436 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 69641436 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 69641436 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 69641436 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 69641436 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 69641436 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 40105 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 40105 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 40105 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 40105 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 40105 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 40105 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 757528000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 757528000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 757528000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 757528000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 757528000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 757528000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 69681541 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 69681541 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 69681541 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 69681541 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 69681541 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 69681541 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000576 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000576 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000576 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000576 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000576 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000576 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18888.617379 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18888.617379 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18888.617379 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18888.617379 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 38168 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 38168 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40105 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 40105 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 40105 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 40105 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 40105 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 40105 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 717424000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 717424000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 717424000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 717424000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 717424000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 717424000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000576 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000576 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000576 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17888.642314 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17888.642314 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4199.701287 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 60529 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5648 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 10.716891 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 353.800339 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.579629 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.321319 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010797 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096667 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.128165 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5648 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 561366 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 561366 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 23251 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 23251 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36680 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 36680 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 291 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 291 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 36680 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 36987 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 36680 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 36987 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3425 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 3425 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1351 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1351 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3425 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 4205 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3425 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 4205 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 215334500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 215334500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257203500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 257203500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104684500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 104684500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 257203500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 320019000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 577222500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 257203500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 320019000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 577222500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 23251 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 23251 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40105 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 40105 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1642 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1642 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 40105 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 4512 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 44617 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 40105 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4512 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 44617 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085401 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085401 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822777 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822777 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085401 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.931959 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.171011 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085401 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931959 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.171011 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75450.070077 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75450.070077 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75095.912409 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75095.912409 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77486.676536 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77486.676536 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75095.912409 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76104.399524 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75651.703801 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75095.912409 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76104.399524 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75651.703801 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 42 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 42 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186794500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186794500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222839000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222839000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88850500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88850500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222839000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275645000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 498484000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222839000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275645000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 498484000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085351 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.170025 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.170025 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65450.070077 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65450.070077 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65100.496640 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65100.496640 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67876.623377 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67876.623377 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 84140 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 39625 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 41746 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 38168 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 40105 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118377 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 128756 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5009408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 5362816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 44617 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.339243 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.473458 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 29481 66.08% 66.08% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 15136 33.92% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 44617 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 81248000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 60156998 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 4732 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 7586 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7586 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8883500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 40266000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,243 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.201717 # Number of seconds simulated
|
||||
sim_ticks 201717314000 # Number of ticks simulated
|
||||
final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1265309 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1519144 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 934796791 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 311752 # Number of bytes of host memory used
|
||||
host_seconds 215.79 # Real time elapsed on the host
|
||||
sim_insts 273037595 # Number of instructions simulated
|
||||
sim_ops 327811950 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 1394641096 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1875350312 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1394641096 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1394641096 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 348660274 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 434960785 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 6913839315 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2383083566 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9296922881 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6913839315 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6913839315 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1983209845 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1983209845 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6913839315 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4366293411 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11280132726 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 403434629 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 273037595 # Number of instructions committed
|
||||
system.cpu.committedOps 327811950 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 258331481 # number of integer instructions
|
||||
system.cpu.num_fp_insts 114216705 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1174407516 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 985884626 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 168107829 # number of memory refs
|
||||
system.cpu.num_load_insts 85732235 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375594 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 403434628.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 30563491 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 104312493 31.82% 31.82% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 327812145 # Class of executed instruction
|
||||
system.membus.trans_dist::ReadReq 434895828 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 434906723 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 82052672 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 82052672 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution
|
||||
system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1034048704 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 517024352 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 168364078 32.56% 32.56% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 348660274 67.44% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 517024352 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,650 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.517291 # Number of seconds simulated
|
||||
sim_ticks 517291025500 # Number of ticks simulated
|
||||
final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 647052 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 776811 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1227232141 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277364 # Number of bytes of host memory used
|
||||
host_seconds 421.51 # Real time elapsed on the host
|
||||
sim_insts 272739286 # Number of instructions simulated
|
||||
sim_ops 327433744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 1034582051 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 272739286 # Number of instructions committed
|
||||
system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 258331537 # number of integer instructions
|
||||
system.cpu.num_fp_insts 114216705 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 168107847 # number of memory refs
|
||||
system.cpu.num_load_insts 85732248 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375599 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 30563503 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 327812214 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4479 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 998 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 348644750 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 13796 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13796 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 6833 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 6833 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,800 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.504258 # Number of seconds simulated
|
||||
sim_ticks 504258263000 # Number of ticks simulated
|
||||
final_tick 504258263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 386643 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 386643 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 209915985 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262852 # Number of bytes of host memory used
|
||||
host_seconds 2402.19 # Real time elapsed on the host
|
||||
sim_insts 928789150 # Number of instructions simulated
|
||||
sim_ops 928789150 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 185088 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18520000 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18705088 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 185088 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 185088 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2892 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 289375 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 292267 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 367050 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36727212 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 37094262 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 367050 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 367050 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8463346 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8463346 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8463346 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 367050 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36727212 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 45557607 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 292267 # Number of read requests accepted
|
||||
system.physmem.writeReqs 66683 # Number of write requests accepted
|
||||
system.physmem.readBursts 292267 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 18685248 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 4266176 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 18705088 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 18033 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18363 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18394 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 18341 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18245 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18249 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 18313 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 18290 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 18231 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 18232 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 18229 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 18376 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18272 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18137 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 18064 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18188 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 4160 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 4142 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 4099 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 4183 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 4150 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 4100 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 504258181000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 292267 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 66683 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 291455 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 474 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 936 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 937 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 4051 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 4049 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 4052 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 4049 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 4051 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 4051 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 103155 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 222.473443 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 144.311324 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 268.647767 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 37345 36.20% 36.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 43741 42.40% 78.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 9241 8.96% 87.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 735 0.71% 88.28% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 1396 1.35% 89.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1157 1.12% 90.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 662 0.64% 91.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 564 0.55% 91.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 8314 8.06% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 103155 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 69.893801 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 34.549322 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 747.524050 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::10240-11263 1 0.02% 99.85% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.93% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.95% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.463077 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.442287 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.845052 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 3113 76.88% 76.88% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 933 23.04% 99.93% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 3567632750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 9041826500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1459785000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 12219.72 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 30969.72 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 37.05 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 8.46 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 37.09 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 8.46 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.36 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 203404 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 52048 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 69.67 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1404814.55 # Average gap between requests
|
||||
system.physmem.pageHitRate 71.23 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 388939320 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 212218875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1140243000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 104730111945 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 210683510250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 350306824590 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 694.703966 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 349825620000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 16838120000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 137589656250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 390829320 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 213250125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1136538000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 215511840 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 105447215835 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 210054471750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 350393179590 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 694.875219 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 348773258750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 16838120000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 138643034750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 123840342 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 79869322 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 685088 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 102061444 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 68186680 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 66.809441 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 18691358 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 9446 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 14052117 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 14048642 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 3475 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 11780 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 237538322 # DTB read hits
|
||||
system.cpu.dtb.read_misses 198467 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 237736789 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 98305180 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7178 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 98312358 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 335843502 # DTB hits
|
||||
system.cpu.dtb.data_misses 205645 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 336049147 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 285763790 # ITB hits
|
||||
system.cpu.itb.fetch_misses 119 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 285763909 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 37 # Number of system calls
|
||||
system.cpu.numCycles 1008516526 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 928789150 # Number of instructions committed
|
||||
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 316849 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.085840 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.920946 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 237705247 25.59% 89.42% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 928789150 # Class of committed instruction
|
||||
system.cpu.tickCycles 957154131 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 51362395 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 776530 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4092.342308 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 321596153 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 780626 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 411.972126 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 901583500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.342308 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999107 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999107 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1398 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1472 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 645671096 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 645671096 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 223432106 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 223432106 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 321596153 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 321596153 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 321596153 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 321596153 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 849082 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25457059500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 25457059500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10110916000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10110916000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 35567975500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 35567975500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 35567975500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 35567975500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 224144035 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 224144035 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 322445235 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 322445235 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 322445235 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 322445235 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003176 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003176 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002633 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002633 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002633 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002633 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35757.862792 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 35757.862792 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73719.976960 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73719.976960 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 41889.918170 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 41889.918170 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 88489 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88489 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 68456 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 68456 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711615 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 711615 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 780626 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 780626 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 780626 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 780626 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24738054000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24738054000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5071007000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5071007000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29809061000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 29809061000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29809061000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 29809061000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003175 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003175 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002421 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002421 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34763.255412 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34763.255412 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73481.140688 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73481.140688 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 10567 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1686.158478 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 285751480 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 12309 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 23214.841173 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1686.158478 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.823320 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.823320 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 571539889 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 571539889 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 285751480 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 285751480 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 285751480 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 285751480 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 285751480 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 285751480 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 12310 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 12310 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 12310 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 12310 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 12310 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 12310 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 352350500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 352350500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 352350500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 352350500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 352350500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 352350500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 285763790 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 285763790 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 285763790 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 285763790 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 285763790 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 285763790 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28623.111292 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28623.111292 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28623.111292 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28623.111292 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 10567 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 10567 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12310 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 12310 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 12310 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 12310 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 12310 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 12310 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340041500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 340041500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340041500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 340041500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340041500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 340041500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000043 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27623.192526 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27623.192526 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 259940 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32579.649991 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1218214 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 292676 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.162330 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2630.640415 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.297977 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29869.711599 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.080281 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002420 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.911551 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994252 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29021 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 13001951 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 13001951 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 88489 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 88489 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 10567 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 10567 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9417 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 9417 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488885 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 488885 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 9417 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 491251 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 500668 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 9417 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 491251 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 500668 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2893 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2893 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222730 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222730 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2893 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 289375 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 292268 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2893 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 289375 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 292268 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942620000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4942620000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 222699500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 222699500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18537323500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 18537323500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 222699500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 23479943500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23702643000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 222699500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 23479943500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23702643000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88489 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 88489 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 10567 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 10567 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12310 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 12310 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711615 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 711615 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 12310 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 780626 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 792936 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 12310 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 780626 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 792936 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235012 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235012 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312992 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312992 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235012 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370696 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.368590 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235012 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370696 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.368590 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74163.403106 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74163.403106 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76978.741791 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76978.741791 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83227.780272 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83227.780272 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76978.741791 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81140.193521 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 81099.001601 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76978.741791 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81140.193521 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 81099.001601 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2893 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2893 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222730 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222730 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2893 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 289375 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 292268 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2893 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 289375 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 292268 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4276170000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4276170000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193779500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193779500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16310023500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16310023500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193779500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20586193500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 20779973000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193779500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20586193500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 20779973000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235012 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312992 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312992 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.368590 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.368590 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64163.403106 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64163.403106 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66982.198410 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66982.198410 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73227.780272 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73227.780272 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1580033 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 787097 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2081 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2081 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723924 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 155172 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 881298 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 12310 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 711615 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35186 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337782 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2372968 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464064 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 57087424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 259940 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1052876 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001976 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.044414 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1050795 99.80% 99.80% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2081 0.20% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1052876 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 889072500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 18463500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 225622 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 191176 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66645 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66645 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 225622 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842393 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 842393 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972800 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22972800 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 550126 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 550126 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 550126 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 918516000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1556053500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,152 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.464395 # Number of seconds simulated
|
||||
sim_ticks 464394627000 # Number of ticks simulated
|
||||
final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2843750 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2843750 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1422183537 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289848 # Number of bytes of host memory used
|
||||
host_seconds 326.54 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 98301200 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 98301200 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1264600947 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 237510597 # DTB read hits
|
||||
system.cpu.dtb.read_misses 194650 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 237705247 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 98301200 # DTB write hits
|
||||
system.cpu.dtb.write_misses 6871 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 98308071 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 335811797 # DTB hits
|
||||
system.cpu.dtb.data_misses 201521 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 336013318 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 928789150 # ITB hits
|
||||
system.cpu.itb.fetch_misses 105 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 928789255 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 37 # Number of system calls
|
||||
system.cpu.numCycles 928789255 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 928587629 # Number of instructions committed
|
||||
system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 37048314 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 822136244 # number of integer instructions
|
||||
system.cpu.num_fp_insts 33439365 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 336013318 # number of memory refs
|
||||
system.cpu.num_load_insts 237705247 # Number of load instructions
|
||||
system.cpu.num_store_insts 98308071 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 928789255 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 123111018 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 928789150 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,548 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.288319 # Number of seconds simulated
|
||||
sim_ticks 1288319411500 # Number of ticks simulated
|
||||
final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1388114 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1388114 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1925865262 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260804 # Number of bytes of host memory used
|
||||
host_seconds 668.96 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 289248 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 291389 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 106359 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14369008 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14475367 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 106359 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 106359 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3312619 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3312619 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3312619 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 237510597 # DTB read hits
|
||||
system.cpu.dtb.read_misses 194650 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 237705247 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 98301200 # DTB write hits
|
||||
system.cpu.dtb.write_misses 6871 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 98308071 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 335811797 # DTB hits
|
||||
system.cpu.dtb.data_misses 201521 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 336013318 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 928789151 # ITB hits
|
||||
system.cpu.itb.fetch_misses 105 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 928789256 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 37 # Number of system calls
|
||||
system.cpu.numCycles 2576638823 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 928587629 # Number of instructions committed
|
||||
system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 37048314 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 822136244 # number of integer instructions
|
||||
system.cpu.num_fp_insts 33439365 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 336013318 # number of memory refs
|
||||
system.cpu.num_load_insts 237705247 # Number of load instructions
|
||||
system.cpu.num_store_insts 98308071 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2576638823 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 123111018 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 928789150 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 776432 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1104319500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.180330 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999556 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999556 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 995 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 335031269 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 780528 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20157098000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 20157098000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4162936000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4162936000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 24320034000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24320034000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 24320034000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24320034000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88866 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19445584000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19445584000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4093922000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4093922000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23539506000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23539506000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23539506000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23539506000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 4618 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1474.418872 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.719931 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.719931 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 928782983 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 6168 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 185126500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 185126500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 185126500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 185126500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 185126500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 185126500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 4618 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 4618 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178958500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 178958500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178958500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 178958500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178958500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 178958500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29014.023995 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 258847 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 291581 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.139570 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2500.518191 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.895472 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.076310 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001462 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.918769 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1142 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488914 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 488914 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 491280 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 495307 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 491280 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 495307 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222600 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222600 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 289248 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 291389 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 289248 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 291389 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3965557000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3965557000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 127415500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 127415500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13244711500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13244711500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 127415500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 17210268500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 17337684000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 127415500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 17210268500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 17337684000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88866 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 88866 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 6168 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711514 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 711514 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312854 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312854 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.370396 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.370396 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222600 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222600 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 289248 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 291389 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 289248 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 291389 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3299077000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3299077000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 106005500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 106005500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11018711500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11018711500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106005500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14317788500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14423794000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106005500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14317788500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14423794000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312854 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312854 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.370396 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.370396 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 879730 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 258847 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1043825 99.84% 99.84% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1718 0.16% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1045543 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 877357000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 224741 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190447 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66648 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 224741 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839908 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 839908 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 548519 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 548519 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 548519 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 815264000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1456945000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,906 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.489946 # Number of seconds simulated
|
||||
sim_ticks 489945697500 # Number of ticks simulated
|
||||
final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 235921 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 290449 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 180421993 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280028 # Number of bytes of host memory used
|
||||
host_seconds 2715.55 # Real time elapsed on the host
|
||||
sim_insts 640655085 # Number of instructions simulated
|
||||
sim_ops 788730744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 288654 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 291212 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 334143 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 37705926 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 38040069 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 334143 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 334143 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8634165 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8634165 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8634165 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 334143 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 37705926 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 46674234 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 291212 # Number of read requests accepted
|
||||
system.physmem.writeReqs 66098 # Number of write requests accepted
|
||||
system.physmem.readBursts 291212 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 18637568 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 18282 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18130 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18217 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 18178 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18288 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18411 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 18177 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 17990 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 18028 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 18056 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 18107 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 18202 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18216 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18274 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18258 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 4171 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 4134 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 4146 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 4224 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 4095 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 489945603000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 291212 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 290509 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 903 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 903 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4014 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4017 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 4017 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 4017 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 4019 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 4017 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 110179 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 207.337369 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 135.107709 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 257.005441 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 44928 40.78% 40.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 43473 39.46% 80.23% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 9308 8.45% 88.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1919 1.74% 90.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 694 0.63% 91.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 753 0.68% 91.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 467 0.42% 92.16% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 575 0.52% 92.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 8062 7.32% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 110179 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 48.520538 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 34.272045 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 506.481387 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.449091 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.428808 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.834669 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 3115 77.55% 77.55% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 902 22.45% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 3297540750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 8751747000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 11336.00 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 30086.00 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 38.00 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 8.63 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 38.04 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 8.63 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.36 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.30 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 22.85 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 195161 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 51618 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 67.09 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 78.09 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1371205.96 # Average gap between requests
|
||||
system.physmem.pageHitRate 69.13 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 417417840 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 227757750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1136210400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 215563680 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 104435392590 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 202355359500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 340788331200 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 695.568361 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 335944764000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 16360240000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 137638069000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 415474920 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 226697625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 212608800 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 104010891930 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 202727728500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 340726427415 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 695.442012 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 336564996750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 16360240000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 144591747 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 81370677 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 61978792 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 76.168461 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 19276085 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 1317 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 15994685 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 15989167 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 673 # Number of system calls
|
||||
system.cpu.numCycles 979891395 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 640655085 # Number of instructions committed
|
||||
system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 6653282 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.529515 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.653802 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 788730744 # Class of committed instruction
|
||||
system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 778302 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 782398 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 483.702967 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 792959500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.104499 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999049 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999049 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1499 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 378433272 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 378433272 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 378436756 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 378436756 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 713841 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 713841 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 137711 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 137711 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 851552 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 851552 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 851693 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 851693 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25188260500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 25188260500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10109820000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10109820000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 35298080500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 35298080500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 35298080500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 35298080500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 250333347 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 250333347 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 379284824 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 379284824 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 379288449 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 379288449 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002852 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002852 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35285.533473 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 35285.533473 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73413.307579 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73413.307579 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41451.468025 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 41451.468025 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41444.605627 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 41444.605627 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 88712 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88712 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 904 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 69293 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 69293 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 69293 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 69293 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712937 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 712937 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 782259 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 782259 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 782398 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 782398 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24459771500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24459771500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5070040000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5070040000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29529811500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 29529811500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29531599500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 29531599500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34308.461337 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34308.461337 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 24859 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.836373 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1753 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1599 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 252585994 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 252585994 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 252585994 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 26613 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 26613 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 26613 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 26613 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 26613 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 26613 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 516729500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 516729500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 516729500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 516729500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 516729500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 516729500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 252612607 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 252612607 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 252612607 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 252612607 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 252612607 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 252612607 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000105 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000105 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000105 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000105 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000105 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000105 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19416.431819 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 19416.431819 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 19416.431819 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 19416.431819 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 24859 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 24859 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26613 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 26613 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 26613 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 26613 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 26613 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 26613 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 490117500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 490117500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 490117500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 490117500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 490117500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 490117500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000105 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000105 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000105 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 258808 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 291552 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.279820 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2632.544658 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.421700 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.783132 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.080339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002698 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.910638 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.993675 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3136 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 23528 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24049 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 24049 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490486 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 490486 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 24049 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 493717 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 517766 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 24049 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 493717 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 517766 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2564 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2564 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222590 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222590 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2564 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 288681 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 291245 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2564 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 288681 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 291245 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4932129000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4932129000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 196405000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 196405000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18239788500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 18239788500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 196405000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 23171917500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23368322500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 196405000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 23171917500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23368322500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88712 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 88712 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 23528 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 23528 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26613 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 26613 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 713076 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 713076 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 26613 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 782398 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 809011 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 26613 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 782398 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 809011 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096344 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096344 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312155 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312155 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096344 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368970 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.360001 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096344 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368970 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.360001 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.333389 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.333389 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76601.014041 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76601.014041 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81943.431870 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81943.431870 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 80235.961132 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 80235.961132 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 27 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2559 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2559 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222563 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222563 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2559 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 288654 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 291213 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2559 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288654 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 291213 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4271219000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4271219000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 170500500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 170500500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16012410500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16012410500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170500500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20283629500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 20454130000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170500500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20283629500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 20454130000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096156 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312117 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312117 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.359962 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.359962 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.333389 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.333389 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66627.784291 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66627.784291 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 882300 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 26613 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 713076 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78084 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2343098 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2421182 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3294144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55751040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 59045184 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 258808 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1067819 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.005072 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.071235 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1062418 99.49% 99.49% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5386 0.50% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1067819 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 919657000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 39920495 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 225121 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190682 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66091 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66091 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 225121 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 839204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22867840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22867840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 547992 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 547992 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 547992 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 916865000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1554037500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,243 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.395727 # Number of seconds simulated
|
||||
sim_ticks 395726778500 # Number of ticks simulated
|
||||
final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1575908 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1940150 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 973424664 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 311080 # Number of bytes of host memory used
|
||||
host_seconds 406.53 # Real time elapsed on the host
|
||||
sim_insts 640654411 # Number of instructions simulated
|
||||
sim_ops 788730070 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 673 # Number of system calls
|
||||
system.cpu.numCycles 791453558 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 640654411 # Number of instructions committed
|
||||
system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 37261296 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 682251400 # number of integer instructions
|
||||
system.cpu.num_fp_insts 24239771 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1320162254 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 381221435 # number of memory refs
|
||||
system.cpu.num_load_insts 252240938 # Number of load instructions
|
||||
system.cpu.num_store_insts 128980497 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 137364860 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 788730744 # Class of executed instruction
|
||||
system.membus.trans_dist::ReadReq 893703778 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 893709517 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 128951477 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution
|
||||
system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1022670353 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,659 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.045756 # Number of seconds simulated
|
||||
sim_ticks 1045756396500 # Number of ticks simulated
|
||||
final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 744148 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 914231 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1217137628 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277972 # Number of bytes of host memory used
|
||||
host_seconds 859.19 # Real time elapsed on the host
|
||||
sim_insts 639366787 # Number of instructions simulated
|
||||
sim_ops 785501035 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 673 # Number of system calls
|
||||
system.cpu.numCycles 2091512793 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 639366787 # Number of instructions committed
|
||||
system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 37261296 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 682251400 # number of integer instructions
|
||||
system.cpu.num_fp_insts 24239771 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 381221435 # number of memory refs
|
||||
system.cpu.num_load_insts 252240938 # Number of load instructions
|
||||
system.cpu.num_store_insts 128980497 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 137364860 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 788730744 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 778046 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 378498833 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 782143 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88995 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 8769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 643367692 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 10208 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 8769 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 8769 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 257772 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 501982 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 290368 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 257772 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 224275 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190094 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 546561 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 546561 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,799 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.059447 # Number of seconds simulated
|
||||
sim_ticks 59447065000 # Number of ticks simulated
|
||||
final_tick 59447065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 371878 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 371878 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 249972170 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 261720 # Number of bytes of host memory used
|
||||
host_seconds 237.81 # Real time elapsed on the host
|
||||
sim_insts 88438073 # Number of instructions simulated
|
||||
sim_ops 88438073 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 432832 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10149568 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10582400 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 432832 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 432832 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7326016 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7326016 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 6763 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 158587 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 165350 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 114469 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 114469 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7280965 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 170732870 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 178013835 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7280965 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7280965 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 123235958 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 123235958 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 123235958 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7280965 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 170732870 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 301249793 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 165350 # Number of read requests accepted
|
||||
system.physmem.writeReqs 114469 # Number of write requests accepted
|
||||
system.physmem.readBursts 165350 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 114469 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 10581952 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 7323968 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 10582400 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 7326016 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 10315 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 10360 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 10206 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 10057 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 10348 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 10343 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 9775 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 10207 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 10536 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 10606 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 10500 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 10228 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 10273 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 10559 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 10465 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 10565 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 7163 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 7274 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 7296 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 7002 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 7127 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 7186 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 6833 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 7099 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 7226 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 6999 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 7117 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 7034 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 6992 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 7299 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 7307 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 7483 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 59447041000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 165350 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 114469 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 163735 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1580 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 750 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 772 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 7002 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 7044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 7073 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 7064 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 7070 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 7073 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 7076 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 7124 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 7113 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 7242 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 7218 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 7356 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 7098 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 7043 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 54692 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 327.365172 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 194.328231 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 330.549756 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 19615 35.86% 35.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 11787 21.55% 57.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 5586 10.21% 67.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 3666 6.70% 74.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2860 5.23% 79.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 2087 3.82% 83.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1603 2.93% 86.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1458 2.67% 88.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 6030 11.03% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 54692 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 23.476853 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 336.379045 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 7039 99.96% 99.96% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.250639 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.234557 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.758479 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 6275 89.11% 89.11% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 11 0.16% 89.26% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 574 8.15% 97.42% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 150 2.13% 99.55% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 18 0.26% 99.80% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 9 0.13% 99.93% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 1988923000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 5089104250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 826715000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 12029.07 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 30779.07 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 178.01 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 123.20 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 178.01 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 123.24 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 2.35 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 23.77 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 143858 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 81218 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 87.01 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 70.95 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 212448.19 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.44 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 199274040 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 108730875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 636347400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 369068400 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3882347040 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 12411408285 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 24777095250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 42384271290 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 713.053838 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 41070575000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1984840000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 16385091250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 213940440 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 116733375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 652860000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 372152880 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3882347040 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 13085746785 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 24185582250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 42509362770 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 715.158080 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 40083292000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1984840000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 17372590500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 14660042 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9484785 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 381684 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 9866507 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 6346497 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 64.323646 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1708762 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 84355 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 37443 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 31778 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 5665 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 7605 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20565775 # DTB read hits
|
||||
system.cpu.dtb.read_misses 97355 # DTB read misses
|
||||
system.cpu.dtb.read_acv 8 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20663130 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14665271 # DTB write hits
|
||||
system.cpu.dtb.write_misses 9409 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 14674680 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35231046 # DTB hits
|
||||
system.cpu.dtb.data_misses 106764 # DTB misses
|
||||
system.cpu.dtb.data_acv 8 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 35337810 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 25585531 # ITB hits
|
||||
system.cpu.itb.fetch_misses 5208 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 25590739 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 118894130 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 88438073 # Number of instructions committed
|
||||
system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1097381 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.344377 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.743839 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 60.14% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 20366786 23.03% 83.47% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 88438073 # Class of committed instruction
|
||||
system.cpu.tickCycles 91425505 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 27468625 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 200766 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4070.673886 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 34612040 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204862 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 168.952954 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 687650500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.673886 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.993817 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993817 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3360 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 70168000 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 70168000 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20278781 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20278781 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 14333259 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 14333259 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 34612040 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 34612040 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 34612040 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 34612040 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 89411 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 89411 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 280118 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 280118 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 369529 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 369529 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 369529 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 369529 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4770299000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4770299000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21700228000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21700228000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 26470527000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 26470527000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 26470527000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 26470527000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20368192 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20368192 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 34981569 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 34981569 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 34981569 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 34981569 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019169 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.019169 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.010564 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010564 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.010564 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010564 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53352.484594 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 53352.484594 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77468.166987 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 77468.166987 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71633.151931 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 71633.151931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 71633.151931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 71633.151931 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 168424 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168424 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28112 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 28112 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136555 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 136555 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 164667 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 164667 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 164667 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 164667 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61299 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 61299 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143563 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 143563 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 204862 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 204862 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204862 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204862 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2681247500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2681247500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10975422500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10975422500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13656670000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 13656670000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13656670000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 13656670000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43740.477006 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43740.477006 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76450.216978 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76450.216978 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 152872 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1932.382407 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 25430610 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 154920 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 164.153176 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 42235793500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1932.382407 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.943546 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.943546 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1039 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 51325982 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 51325982 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 25430610 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 25430610 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 25430610 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 25430610 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 25430610 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 25430610 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 154921 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 154921 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 154921 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 154921 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 154921 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 154921 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2483739000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 2483739000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 2483739000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 2483739000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 2483739000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 2483739000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 25585531 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 25585531 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 25585531 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 25585531 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 25585531 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 25585531 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006055 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.006055 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.006055 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.006055 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.006055 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.006055 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16032.293879 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16032.293879 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16032.293879 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16032.293879 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16032.293879 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16032.293879 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 152872 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 152872 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154921 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 154921 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 154921 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 154921 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 154921 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 154921 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2328819000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 2328819000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2328819000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 2328819000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2328819000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 2328819000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15032.300334 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15032.300334 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 133382 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30429.048447 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 403995 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 165492 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.441175 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26350.763451 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2094.967777 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1983.317219 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.804161 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.063933 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.060526 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.928621 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32110 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1093 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11874 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18854 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 124 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979919 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 6016424 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 6016424 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 168424 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 168424 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 152872 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 152872 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 12681 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12681 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 148157 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 148157 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33594 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 33594 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 148157 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 46275 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 194432 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 148157 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 46275 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 194432 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 130883 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 130883 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6764 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 6764 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27704 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 27704 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 6764 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 158587 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 165351 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 6764 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 158587 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 165351 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10626878000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 10626878000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 540586000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 540586000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2236085500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2236085500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 540586000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 12862963500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 13403549500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 540586000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 12862963500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 13403549500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 168424 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 168424 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 152872 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 152872 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143564 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143564 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 154921 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 154921 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61298 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 61298 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 154921 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 204862 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 359783 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 154921 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 204862 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 359783 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911670 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911670 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043661 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043661 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.451956 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.451956 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043661 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.774116 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.459585 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043661 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.774116 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.459585 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81193.722638 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81193.722638 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79921.052632 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79921.052632 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80713.452931 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80713.452931 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79921.052632 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81109.822999 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 81061.194066 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79921.052632 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81109.822999 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 81061.194066 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 114469 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 114469 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 115 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 115 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130883 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 130883 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6764 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6764 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27704 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27704 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 158587 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 165351 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 158587 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 165351 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9318048000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9318048000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 472956000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 472956000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1959045500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1959045500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 472956000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11277093500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11750049500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472956000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11277093500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11750049500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911670 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911670 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043661 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451956 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451956 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774116 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.459585 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774116 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.459585 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71193.722638 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71193.722638 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69922.531047 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69922.531047 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70713.452931 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70713.452931 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69922.531047 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71109.822999 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71061.254543 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.531047 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71109.822999 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71061.254543 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 713421 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 353638 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 4037 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4037 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 216218 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 282893 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 152872 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 51255 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 143564 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 143564 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 154921 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 61298 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462713 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610490 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1073203 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19698688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23890304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 43588992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 133382 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 493165 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.008186 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.090105 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 489128 99.18% 99.18% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 4037 0.82% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 493165 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 678006500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 232381497 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 307297491 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 34467 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 114469 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 14990 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130883 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130883 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 34467 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460159 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 460159 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17908416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 17908416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 294809 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 294809 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 294809 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 822950500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 872961750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,916 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.056803 # Number of seconds simulated
|
||||
sim_ticks 56802974500 # Number of ticks simulated
|
||||
final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 222036 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 283951 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 177850276 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280068 # Number of bytes of host memory used
|
||||
host_seconds 319.39 # Real time elapsed on the host
|
||||
sim_insts 70915150 # Number of instructions simulated
|
||||
sim_ops 90690106 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 285504 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 5517760 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 5517760 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 4461 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 128284 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 86215 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 86215 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 5026216 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 139511567 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 144537783 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 5026216 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 5026216 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 97138575 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 97138575 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 97138575 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 5026216 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 139511567 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 241676358 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 128284 # Number of read requests accepted
|
||||
system.physmem.writeReqs 86215 # Number of write requests accepted
|
||||
system.physmem.readBursts 128284 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 86215 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 8209792 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 5515904 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 8210176 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 5517760 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 8062 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 8315 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 8233 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 8142 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 8284 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 8403 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 8055 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 7916 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 8035 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 7587 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 7763 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 7815 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 7871 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 7867 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 7968 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 7962 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 5395 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 5541 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 5468 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 5336 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 5366 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 5560 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 5257 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 5179 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 5154 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 5105 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 5292 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 5270 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 5531 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 5703 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 5432 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 56802942500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 128284 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 86215 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 116125 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 12132 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 631 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 643 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4122 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 5183 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 5277 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 5318 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 5309 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 5314 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 5321 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 5353 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 5464 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 5436 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 5495 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 5447 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 5305 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 38880 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 352.990947 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 214.489872 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 335.589979 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 12269 31.56% 31.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 8336 21.44% 53.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4191 10.78% 63.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2845 7.32% 71.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2490 6.40% 77.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1681 4.32% 81.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1302 3.35% 85.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1149 2.96% 88.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 4617 11.88% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 38880 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 24.227616 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 352.423208 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 5291 99.94% 99.94% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.279940 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.260845 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.856304 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 4659 88.01% 88.01% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 4 0.08% 88.08% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 483 9.12% 97.20% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 119 2.25% 99.45% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 16 0.30% 99.75% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 8 0.15% 99.91% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 3 0.06% 99.96% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::42 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 1681541750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 4086754250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 641390000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 13108.57 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 31858.57 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 144.53 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 97.11 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 144.54 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 97.14 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 1.89 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 23.24 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 111837 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 63741 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 73.93 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 264816.82 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 153127800 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 83551875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 510073200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 11545672905 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 23952789000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 40234383180 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 708.339923 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 39720213500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1896700000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 15184054000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 140767200 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 76807500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 490315800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 279158400 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 11005773750 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 24426384750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 40129152600 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 706.487303 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 40510168000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1896700000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 14774616 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 9548677 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 6547888 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 68.573772 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1714315 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 174550 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 157999 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 113605949 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 70915150 # Number of instructions committed
|
||||
system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1137741 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.601998 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.624220 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 90690106 # Class of committed instruction
|
||||
system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 156448 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 265.474350 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 820768500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4067.225830 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992975 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992975 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 19642172 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 83401 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 83401 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 42505075 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 42505075 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 42588476 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 42588476 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 51661 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 51661 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 207729 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 207729 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 44584 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 44584 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 259390 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 259390 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 303974 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 303974 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1490194000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1490194000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16811157000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 16811157000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 18301351000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 18301351000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 18301351000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 18301351000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22914564 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22914564 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 127985 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 127985 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 42764465 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 42764465 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 42892450 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 42892450 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002255 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002255 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348353 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.348353 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28845.628230 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 28845.628230 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80928.310443 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 80928.310443 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70555.345233 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 70555.345233 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60206.961780 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60206.961780 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 128389 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 128389 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22138 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 22138 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100695 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 100695 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 122833 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 122833 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 122833 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 122833 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29523 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 29523 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23987 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 23987 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 136557 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 136557 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 160544 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 160544 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578329500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 578329500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8490118500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8490118500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713467500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713467500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9068448000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9068448000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10781915500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10781915500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187420 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187420 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003743 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003743 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19589.116960 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19589.116960 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 43497 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.904627 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24844377 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24844377 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24844377 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 45540 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 45540 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 45540 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 45540 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 45540 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 45540 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 905103000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 905103000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 905103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 905103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 905103000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 905103000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 24889917 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 24889917 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 24889917 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 24889917 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 24889917 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 24889917 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001830 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001830 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001830 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001830 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001830 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001830 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19874.901186 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 19874.901186 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 19874.901186 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 19874.901186 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 43497 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 43497 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45540 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 45540 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 45540 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 45540 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 45540 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 45540 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 859564000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 859564000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 859564000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 859564000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 859564000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 859564000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001830 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.001830 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 96391 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1656.072920 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.817316 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043735 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.050539 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.911590 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31151 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12725 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15781 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 39908 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41065 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 41065 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31907 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 31907 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 41065 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 77724 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 41065 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 77724 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 102282 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 102282 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4475 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 4475 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21603 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 21603 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 4475 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 123885 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 128360 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 4475 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 123885 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 128360 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8279623500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 8279623500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356201500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 356201500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1872087500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1872087500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 356201500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10151711000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 10507912500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 356201500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10151711000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 10507912500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 128389 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 128389 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 39908 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 39908 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45540 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 45540 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 45540 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 160544 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 206084 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 45540 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 160544 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 206084 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955603 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955603 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098265 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098265 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403719 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403719 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098265 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.771658 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.622853 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098265 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.771658 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.622853 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80948.979293 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80948.979293 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79598.100559 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79598.100559 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86658.681665 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86658.681665 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 81862.827205 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 81862.827205 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 86215 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 86215 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102282 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 102282 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4462 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4462 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21541 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21541 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 4462 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 128285 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4462 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 128285 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7256803500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7256803500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310457000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310457000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1652012000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1652012000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310457000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8908815500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9219272500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310457000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8908815500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9219272500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955603 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955603 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097980 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402560 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402560 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.622489 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.622489 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70948.979293 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70948.979293 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69577.991932 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69577.991932 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76691.518500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76691.518500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 38235 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 45540 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134576 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 612112 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5698304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 24190016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 96391 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 302475 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.037210 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.189781 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 291249 96.29% 96.29% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 11197 3.70% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 302475 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 374900500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 68328959 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 26002 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 86215 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 6912 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 102282 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 102282 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 26002 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349695 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 349695 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 13727936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 221411 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 221411 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 221411 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 590704500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 676958000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,807 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.208778 # Number of seconds simulated
|
||||
sim_ticks 1208777694500 # Number of ticks simulated
|
||||
final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 390102 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 390102 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 258186532 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253640 # Number of bytes of host memory used
|
||||
host_seconds 4681.80 # Real time elapsed on the host
|
||||
sim_insts 1826378509 # Number of instructions simulated
|
||||
sim_ops 1826378509 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 124970112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 125031424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65416896 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65416896 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1952658 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1953616 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1022139 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1022139 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 50722 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 103385521 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 103436244 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 50722 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 50722 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 54118219 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 54118219 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 54118219 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 50722 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 103385521 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 157554463 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1953616 # Number of read requests accepted
|
||||
system.physmem.writeReqs 1022139 # Number of write requests accepted
|
||||
system.physmem.readBursts 1953616 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 1022139 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 124948416 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 83008 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 65415616 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 125031424 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 65416896 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 1297 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 118316 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 113525 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 115740 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 117258 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 117310 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 117126 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 119402 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 124113 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 126650 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 129582 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 128169 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 129917 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 125580 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 124837 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 122150 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 122644 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 61421 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 61661 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 60724 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 61398 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 61819 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 63309 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 64356 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 65855 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 65577 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 66031 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 65643 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 65945 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 64508 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 64526 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 64900 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 64446 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 1208777578000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 1953616 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 1022139 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 1830097 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 122205 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 30602 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 32045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 55307 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 59695 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 60116 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 60223 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 60190 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 60196 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 60182 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 60140 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 60199 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 60169 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 60684 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 61042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 60657 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 61101 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 59828 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 59617 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1831457 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 103.940817 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 81.136003 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 130.529919 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 1452947 79.33% 79.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 261995 14.31% 93.64% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 48664 2.66% 96.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 20593 1.12% 97.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 13175 0.72% 98.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 7238 0.40% 98.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 5438 0.30% 98.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 4580 0.25% 99.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 16827 0.92% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1831457 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 59614 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 32.747643 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 146.947369 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-511 59453 99.73% 99.73% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::512-1023 115 0.19% 99.92% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-1535 9 0.02% 99.94% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1536-2047 9 0.02% 99.95% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::2560-3071 3 0.01% 99.97% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::3584-4095 3 0.01% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 59614 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 59614 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 17.145620 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 17.109391 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 1.119268 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 27453 46.05% 46.05% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 1268 2.13% 48.18% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 26337 44.18% 92.36% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 4007 6.72% 99.08% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 455 0.76% 99.84% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 71 0.12% 99.96% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 15 0.03% 99.99% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 59614 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 36537628750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 73143610000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 9761595000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 18714.99 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 37464.99 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 103.37 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 54.12 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 103.44 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 54.12 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 1.23 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 723773 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 419204 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 41.01 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 406208.70 # Average gap between requests
|
||||
system.physmem.pageHitRate 38.43 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6714376200 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3663598125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 7353738600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 3243518640 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 78951397200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 415074736440 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 361165338750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 876166703955 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 724.837554 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 598070170000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 40363700000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 570342873000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 7131423600 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 3891153750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 7874224800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 3379812480 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 78951397200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 426560774805 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 351089866500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 878878653135 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 727.081103 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 581228871000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 40363700000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 587184084000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 246097965 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 186356162 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 15588061 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 167640085 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 165196337 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 98.542265 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 18413332 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 104391 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 297 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 67 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 230 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 98 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 452860657 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4979867 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 457840524 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 161378231 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1709431 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 163087662 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 614238888 # DTB hits
|
||||
system.cpu.dtb.data_misses 6689298 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 620928186 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 597989612 # ITB hits
|
||||
system.cpu.itb.fetch_misses 19 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 597989631 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||
system.cpu.numCycles 2417555389 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1826378509 # Number of instructions committed
|
||||
system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 51811935 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.323688 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.755465 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 66.45% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 805244 0.04% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 13 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 100 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 11 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 24 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.50% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 449492741 24.61% 91.11% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 1826378509 # Class of committed instruction
|
||||
system.cpu.tickCycles 2075251932 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 342303457 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 9121974 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4080.726355 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 601538856 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9126070 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.914337 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 16821281500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4080.726355 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.996271 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1562 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2407 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1231275880 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1231275880 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 443056865 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 443056865 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 158481991 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 158481991 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 601538856 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 601538856 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 601538856 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 601538856 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7289538 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7289538 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2246511 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2246511 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9536049 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9536049 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9536049 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9536049 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 185480529000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 185480529000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 108417025500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 108417025500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 293897554500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 293897554500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 293897554500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 293897554500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 450346403 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 450346403 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 611074905 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 611074905 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 611074905 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 611074905 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016187 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013977 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.013977 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.015605 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.015605 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.015605 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.015605 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25444.757816 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 25444.757816 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48260.180119 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 48260.180119 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 30819.635522 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 30819.635522 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 3686603 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3686603 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50808 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 50808 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359171 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 359171 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 409979 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 409979 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 409979 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 409979 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238730 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7238730 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887340 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1887340 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9126070 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9126070 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9126070 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9126070 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 177011068000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 177011068000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83258719000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83258719000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260269787000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 260269787000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260269787000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 260269787000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016074 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016074 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.014934 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.014934 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24453.332007 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24453.332007 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44114.319095 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44114.319095 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 3 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 624205.275574 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 750.173547 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.366296 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.366296 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 1195980182 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1195980182 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 597988654 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 597988654 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 597988654 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 597988654 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 597988654 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 597988654 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 958 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 76338000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 76338000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 76338000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 76338000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 76338000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 76338000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 597989612 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 597989612 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 597989612 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 597989612 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 597989612 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 597989612 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79684.759916 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 79684.759916 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 79684.759916 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 79684.759916 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 79684.759916 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 79684.759916 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 3 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 3 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75380000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 75380000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75380000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 75380000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75380000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 75380000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78684.759916 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78684.759916 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 1920891 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1950696 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.386949 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 89219766000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 14798.392410 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.817395 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.106083 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.451611 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001307 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.485965 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.938883 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29805 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1217 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12865 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15532 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 149830076 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149830076 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3686603 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3686603 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1106830 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1106830 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6066582 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6066582 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7173412 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7173412 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7173412 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7173412 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 780510 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 780510 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 958 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 958 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1172148 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1172148 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 958 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1952658 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1953616 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 958 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1952658 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1953616 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68734828000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 68734828000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 73941000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 73941000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102426227000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 102426227000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 73941000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 171161055000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 171234996000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 73941000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 171161055000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 171234996000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3686603 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3686603 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887340 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1887340 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 958 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 958 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7238730 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 7238730 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 958 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9126070 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9127028 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 958 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9126070 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9127028 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413550 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.413550 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161927 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161927 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.213965 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.214047 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.213965 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214047 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88063.994055 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88063.994055 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77182.672234 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77182.672234 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87383.356880 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87383.356880 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77182.672234 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87655.418921 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 87650.283372 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77182.672234 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87655.418921 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 87650.283372 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 1022139 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1022139 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780510 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 780510 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 958 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 958 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1172148 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1172148 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1952658 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1953616 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1952658 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1953616 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60929728000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60929728000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64361000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64361000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90704747000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90704747000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64361000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151634475000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 151698836000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64361000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151634475000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 151698836000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413550 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413550 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161927 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161927 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214047 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214047 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78063.994055 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78063.994055 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67182.672234 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67182.672234 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77383.356880 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77383.356880 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18249005 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121977 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7239688 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4708742 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6334123 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1887340 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1887340 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 958 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238730 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374114 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27376033 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820011072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 820072576 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1920891 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11047919 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.010713 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11046651 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1268 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11047919 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12811108500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1437000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13689105000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1173106 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1022139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 897726 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 780510 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 780510 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1173106 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827097 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5827097 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190448320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190448320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3873481 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3873481 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3873481 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8428417500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 10685410500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,152 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.913189 # Number of seconds simulated
|
||||
sim_ticks 913189263000 # Number of ticks simulated
|
||||
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2928853 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2928852 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1469736098 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 279876 # Number of bytes of host memory used
|
||||
host_seconds 621.33 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 7305514036 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 7305514036 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 827777307 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 827777307 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1826378509 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 444595663 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 2270974172 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 160728502 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 160728502 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7999999926 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2162526450 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 10162526375 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7999999926 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7999999926 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 906468506 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 906468506 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 160728502 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 160728502 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3652757018 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1210648330 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4863405348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 7305514036 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2802573242 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 10108087278 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.751070 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.432393 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 605324165 24.89% 24.89% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 1826378509 75.11% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2431702674 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 444595663 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160728502 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605324165 # DTB hits
|
||||
system.cpu.dtb.data_misses 6598382 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 611922547 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 1826378509 # ITB hits
|
||||
system.cpu.itb.fetch_misses 18 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 1826378527 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||
system.cpu.numCycles 1826378527 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1819780127 # Number of instructions committed
|
||||
system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1725565901 # number of integer instructions
|
||||
system.cpu.num_fp_insts 805526 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 611922547 # number of memory refs
|
||||
system.cpu.num_load_insts 449492741 # Number of load instructions
|
||||
system.cpu.num_store_insts 162429806 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1826378527 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 214632552 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1826378509 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,543 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.636720 # Number of seconds simulated
|
||||
sim_ticks 2636719559500 # Number of ticks simulated
|
||||
final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1392133 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1392132 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2017091448 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252104 # Number of bytes of host memory used
|
||||
host_seconds 1307.19 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65405568 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65405568 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1951440 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 19467 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 47366494 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 47385960 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 19467 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 19467 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 24805660 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 24805660 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 24805660 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 444595663 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160728502 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605324165 # DTB hits
|
||||
system.cpu.dtb.data_misses 6598382 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 611922547 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 1826378510 # ITB hits
|
||||
system.cpu.itb.fetch_misses 18 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||
system.cpu.numCycles 5273439119 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1819780127 # Number of instructions committed
|
||||
system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1725565901 # number of integer instructions
|
||||
system.cpu.num_fp_insts 805526 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 611922547 # number of memory refs
|
||||
system.cpu.num_load_insts 449492741 # Number of load instructions
|
||||
system.cpu.num_store_insts 162429806 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5273439119 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 214632552 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1826378509 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 41036287500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.293901 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995921 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995921 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 596212431 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151181633000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151181633000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62898029000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 62898029000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 214079662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 214079662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 214079662000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 214079662000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20932.285660 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20932.285660 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33291.358266 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 33291.358266 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 3679426 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3679426 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143959219000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 143959219000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61008709000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 61008709000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204967928000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 204967928000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204967928000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 204967928000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19932.285660 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19932.285660 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32291.358266 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32291.358266 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 612.605858 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.299124 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.299124 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1826377708 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1826377708 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1826377708 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 802 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49759500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 49759500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 49759500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 49759500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 49759500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 49759500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1826378510 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62044.264339 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62044.264339 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48957500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 48957500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48957500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 48957500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48957500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 48957500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61044.264339 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61044.264339 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 1919525 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1949317 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.377074 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 218471945000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15091.675189 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.824340 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15410.326183 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.460561 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001185 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.470286 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.932032 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1058 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1106935 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1106935 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6053359 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6053359 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7160294 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7160294 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7160294 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7160294 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 782385 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 782385 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 802 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 802 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1169055 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1169055 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1951440 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1952242 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1951440 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1952242 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46551911500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 46551911500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47746500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 47746500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69565328500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 69565328500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 47746500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 116117240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 116164986500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 47746500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 116117240000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 116164986500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3679426 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3679426 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222414 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 7222414 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9111734 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9112536 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414109 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414109 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161865 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161865 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214168 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.214237 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214168 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214237 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.005113 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.005113 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59534.289277 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59534.289277 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.607948 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.607948 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59503.374326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59503.374326 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 1021962 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1021962 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782385 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 782385 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 802 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1169055 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1169055 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951440 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1952242 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951440 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1952242 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38728061500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38728061500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39726500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39726500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57874778500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57874778500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39726500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96602840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 96642566500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39726500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96602840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 96642566500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414109 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414109 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161865 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161865 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214237 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214237 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.005113 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.005113 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49534.289277 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49534.289277 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.607948 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.607948 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 818685632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919525 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11032061 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000102 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.010084 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11030939 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11032061 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12789514500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1169857 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 896683 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 782385 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 782385 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1169857 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5823129 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5823129 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3870887 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3870887 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3870887 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7958742500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9761210000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,917 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.116866 # Number of seconds simulated
|
||||
sim_ticks 1116865668500 # Number of ticks simulated
|
||||
final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 304077 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 327597 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 219876370 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272296 # Number of bytes of host memory used
|
||||
host_seconds 5079.52 # Real time elapsed on the host
|
||||
sim_insts 1544563088 # Number of instructions simulated
|
||||
sim_ops 1664032481 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2045808 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 44868 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 117231388 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 44868 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 44868 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 44868 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 117231388 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 2046591 # Number of read requests accepted
|
||||
system.physmem.writeReqs 1050123 # Number of write requests accepted
|
||||
system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 130898176 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 83648 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 1307 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 127279 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 124661 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 121601 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 123656 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 122620 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 122679 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 123247 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 123770 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 131396 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 133511 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 132081 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 133308 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 133249 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 133362 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 129309 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 129555 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 66136 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 64410 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 62576 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 63006 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 63000 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 63100 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 64443 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 65436 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 67310 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 67797 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 67549 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 67882 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 67326 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 67793 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 66482 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 65854 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 1116865574000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 2046591 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 1050123 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 1916619 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 128648 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 32746 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 33984 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 56911 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 61204 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 61629 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 61690 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 61591 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 61663 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 61651 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 61697 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 61747 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 61696 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 62170 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 62557 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 62067 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 62573 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 61138 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 84 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 5 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1910138 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 103.711175 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 81.836423 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 125.540224 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 1485349 77.76% 77.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 305158 15.98% 93.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 52532 2.75% 96.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 21047 1.10% 97.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 13374 0.70% 98.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 7565 0.40% 98.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 5491 0.29% 98.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 5162 0.27% 99.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 14460 0.76% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1910138 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 61136 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 33.411672 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 159.590236 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 61090 99.92% 99.92% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 21 0.03% 99.96% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 61136 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 61136 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 17.176459 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 17.141461 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 1.097536 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 27008 44.18% 44.18% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 1128 1.85% 46.02% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 28688 46.92% 92.95% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 3895 6.37% 99.32% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 363 0.59% 99.91% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 46 0.08% 99.99% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 6 0.01% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 61136 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 38124700750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 76473775750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 10226420000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 18640.30 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 37390.30 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 60.18 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 1.39 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 773341 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 411895 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 360661.52 # Average gap between requests
|
||||
system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 7039078200 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3840766875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 7717881600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 420697412235 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 301083150000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 816644588670 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 731.196952 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 498171344000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 581396539000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 7401549960 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 4038544125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 8234959200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 429293377035 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 293542830000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 818945301360 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 733.256935 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 485580062750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 239639355 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 130646338 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 122079091 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 93.442413 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 15657057 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 537 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 230 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 307 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 2233731337 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1544563088 # Number of instructions committed
|
||||
system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 41470388 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.446190 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.691472 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 1664032481 # Class of committed instruction
|
||||
system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 9221041 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 67.665004 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616095 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 170331073 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 624218805 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 624218805 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 624218806 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 624218806 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7334498 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7334498 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2254974 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2254974 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9589472 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9589472 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9589474 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9589474 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 190926660000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 190926660000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 109083916000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 109083916000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 300010576000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 300010576000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 300010576000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 300010576000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 461222230 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 461222230 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 633808277 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 633808277 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 633808280 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 633808280 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.319390 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.319390 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48374.799887 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 48374.799887 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.411334 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31285.411334 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.404809 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31285.404809 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 3684567 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3684567 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364121 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 364121 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 364336 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 364336 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 364336 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 364336 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334283 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7334283 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890853 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1890853 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9225136 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9225136 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9225137 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9225137 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183586477500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 183586477500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84779361000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84779361000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268365838500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 268365838500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268365912500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 268365912500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.278109 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.278109 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 29 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.322454 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 465281510 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 465281510 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 465281510 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 819 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 819 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 819 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 819 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 62402500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 62402500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 62402500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 62402500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 62402500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 62402500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 465282329 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 465282329 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 465282329 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 465282329 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 465282329 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 465282329 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76193.528694 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 76193.528694 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 76193.528694 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 76193.528694 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 29 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 29 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61583500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 61583500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61583500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 61583500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61583500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 61583500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 2013919 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 16398.892088 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.452664 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000807 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.500454 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.953926 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1250 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 29 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1089694 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1089694 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7179324 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7179360 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7179324 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7179360 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 801159 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 801159 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 783 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 783 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244654 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1244654 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 2045813 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 2046596 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2045813 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70441435500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 70441435500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59945000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 59945000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108637226500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 108637226500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 59945000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 179078662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 179138607000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 59945000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 179078662000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 179138607000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3684567 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3684567 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 29 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 29 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890853 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1890853 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 819 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 819 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7334284 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 7334284 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 819 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9225137 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9225956 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 819 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9225137 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9225956 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423702 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.423702 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.956044 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.956044 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169704 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169704 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956044 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.221765 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.221830 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956044 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87924.413880 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87924.413880 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76558.109834 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76558.109834 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87283.073449 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87283.073449 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 87530.028887 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 87530.028887 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1050123 # number of writebacks
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 214 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 214 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801159 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 801159 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 783 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 783 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 2045808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2045808 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 2046591 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62429845500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62429845500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52115000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52115000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96190393500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96190393500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52115000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158620239000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 158672354000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52115000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158620239000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 158672354000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423702 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423702 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956044 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77924.413880 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77924.413880 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66558.109834 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66558.109834 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77283.148502 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77283.148502 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6500270 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1667 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671315 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27672982 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826221056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 2013919 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11239875 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.016088 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11236983 99.97% 99.97% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2886 0.03% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11239875 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12908109000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1245432 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 962724 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 801159 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 801159 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1245432 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106029 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6106029 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 4059438 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 4059438 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 4059438 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8663216000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 11191487250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,243 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.832017 # Number of seconds simulated
|
||||
sim_ticks 832017490500 # Number of ticks simulated
|
||||
final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1936914 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2086731 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1043366913 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303348 # Number of bytes of host memory used
|
||||
host_seconds 797.44 # Real time elapsed on the host
|
||||
sim_insts 1544563042 # Number of instructions simulated
|
||||
sim_ops 1664032434 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 6178262360 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 6178262360 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1544565590 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1999474787 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1900666379 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9326306381 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 1664034982 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1544563042 # Number of instructions committed
|
||||
system.cpu.committedOps 1664032434 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 27330256 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1477900422 # number of integer instructions
|
||||
system.cpu.num_fp_insts 36 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2605402942 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 4992096239 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 633153380 # number of memory refs
|
||||
system.cpu.num_load_insts 458306334 # Number of load instructions
|
||||
system.cpu.num_store_insts 174847046 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1664034981.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 213462427 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1664032481 # Class of executed instruction
|
||||
system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 172586047 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 172586047 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFResp 1 # Transaction distribution
|
||||
system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondReq 61 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondResp 61 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4344121790 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 627495305 28.89% 28.89% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 1544565590 71.11% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2172060895 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,655 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.377030 # Number of seconds simulated
|
||||
sim_ticks 2377029670500 # Number of ticks simulated
|
||||
final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1034140 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1114431 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1597508455 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269992 # Number of bytes of host memory used
|
||||
host_seconds 1487.96 # Real time elapsed on the host
|
||||
sim_insts 1538759602 # Number of instructions simulated
|
||||
sim_ops 1658228915 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 4754059341 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1538759602 # Number of instructions committed
|
||||
system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 27330256 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1477900422 # number of integer instructions
|
||||
system.cpu.num_fp_insts 36 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 633153380 # number of memory refs
|
||||
system.cpu.num_load_insts 458306334 # Number of load instructions
|
||||
system.cpu.num_store_insts 174847046 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 213462427 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1664032481 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 9111140 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 618379947 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3681379 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 7 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1544564953 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1544564953 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 638 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1544565591 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1544565591 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1544565591 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 7 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 7 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 1919027 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.473115 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000722 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.472578 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.946414 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107015 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1107015 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6057123 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6057123 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7164138 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7164160 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7164138 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7164160 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 782134 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 782134 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 616 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 616 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168964 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1168964 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1951098 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1951714 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1951098 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1951714 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46537233000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 46537233000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 36689000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 36689000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69569093500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 69569093500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 36689000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 116106326500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 116143015500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 36689000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 638 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 638 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7226087 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 7226087 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214048 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.214101 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1021127 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919027 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1169580 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 897056 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 782134 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 782134 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3869897 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3869897 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,127 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.846007 # Number of seconds simulated
|
||||
sim_ticks 2846007227500 # Number of ticks simulated
|
||||
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1464727 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2282177 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1385807923 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304512 # Number of bytes of host memory used
|
||||
host_seconds 2053.68 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1239184746 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5252417628 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 11281019509 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 13046253376 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 11281019509 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 11281019509 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 5692014456 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 3008081022 # Number of instructions committed
|
||||
system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 33534539 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4684368009 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 1677713084 # number of memory refs
|
||||
system.cpu.num_load_insts 1239184746 # Number of load instructions
|
||||
system.cpu.num_store_insts 438528338 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5692014455.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 248500691 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 4686862596 # Class of executed instruction
|
||||
system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 438528338 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 438528338 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.705196 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 1677713084 29.48% 29.48% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 4013232882 70.52% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5690945966 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,515 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.895948 # Number of seconds simulated
|
||||
sim_ticks 5895947852500 # Number of ticks simulated
|
||||
final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 781389 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1217475 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1531550481 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272448 # Number of bytes of host memory used
|
||||
host_seconds 3849.66 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 11791895705 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 3008081022 # Number of instructions committed
|
||||
system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 33534539 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4684368009 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 1677713084 # number of memory refs
|
||||
system.cpu.num_load_insts 1239184746 # Number of load instructions
|
||||
system.cpu.num_store_insts 438528338 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 248500691 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 4686862596 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3682716 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 10 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 4013232207 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 675 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 10 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 10 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41184500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 41184500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41184500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 41184500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41184500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 41184500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 1919169 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7161482 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7161482 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7161482 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7161482 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168762 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1168762 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1951195 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1951870 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1951195 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1951870 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46554770500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 46554770500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40170500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 40170500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69541354000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1022289 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919169 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1169437 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 896090 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 782433 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 782433 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3870249 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3870249 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,764 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.051906 # Number of seconds simulated
|
||||
sim_ticks 51905634500 # Number of ticks simulated
|
||||
final_tick 51905634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 330127 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 330127 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 186451175 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 257296 # Number of bytes of host memory used
|
||||
host_seconds 278.39 # Real time elapsed on the host
|
||||
sim_insts 91903089 # Number of instructions simulated
|
||||
sim_ops 91903089 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 340480 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5320 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 3907399 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2652198 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6559596 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3907399 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3907399 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3907399 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2652198 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6559596 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 5320 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 5320 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 340480 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 340480 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 469 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 295 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 308 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 524 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 224 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 238 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 222 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 289 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 252 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 282 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 254 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 261 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 410 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 344 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 500 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 448 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 51905547000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 5320 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 4923 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 378 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 346.395112 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 212.989816 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 328.326928 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 308 31.36% 31.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 213 21.69% 53.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 101 10.29% 63.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 90 9.16% 72.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 71 7.23% 79.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 37 3.77% 83.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 21 2.14% 85.64% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 29 2.95% 88.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 112 11.41% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 32661000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 132411000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 26600000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6139.29 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24889.29 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 4334 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.47 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9756681.77 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.47 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3515400 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1918125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 19983600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 1736098875 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 29619147750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 34770724710 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 669.912241 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 49270880000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 899376250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 3885840 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2120250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 21309600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 1812535875 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 29552097750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 34782010275 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 670.129676 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 49159142250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1011440250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 11440185 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 8207191 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 765027 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 6076858 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 5316207 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 87.482824 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1173724 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 26312 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 24255 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 2057 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20416195 # DTB read hits
|
||||
system.cpu.dtb.read_misses 43360 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20459555 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6579893 # DTB write hits
|
||||
system.cpu.dtb.write_misses 278 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 6580171 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26996088 # DTB hits
|
||||
system.cpu.dtb.data_misses 43638 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 27039726 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 22951506 # ITB hits
|
||||
system.cpu.itb.fetch_misses 90 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 22951596 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 103811269 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 91903089 # Number of instructions committed
|
||||
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2181586 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.129573 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.885290 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 19996208 21.76% 92.93% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 91903089 # Class of committed instruction
|
||||
system.cpu.tickCycles 102098443 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 1712826 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1447.414267 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26572424 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11915.885202 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.414267 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.353373 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.353373 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 53153936 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 53153936 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20074229 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20074229 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6498195 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26572424 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26572424 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26572424 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26572424 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 521 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 521 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2908 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2908 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3429 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3429 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3429 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3429 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40464500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 40464500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 214055500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 214055500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 254520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 254520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 254520000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 254520000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20074750 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20074750 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 26575853 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 26575853 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 26575853 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 26575853 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77666.986564 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 77666.986564 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73609.181568 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73609.181568 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 74225.721785 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 74225.721785 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1163 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1163 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1199 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1199 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1199 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1199 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2230 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36953000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36953000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131397000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131397000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168350000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 168350000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168350000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 168350000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76191.752577 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76191.752577 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75299.140401 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75299.140401 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 13853 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15818 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1449.973891 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1642.330146 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.801919 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.801919 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 672 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 946 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 45918830 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 45918830 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22935687 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22935687 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22935687 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 22935687 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 22935687 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 22935687 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 15819 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 15819 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 15819 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 15819 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15819 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15819 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 406827000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 406827000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 406827000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 406827000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 406827000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 406827000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22951506 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 22951506 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 22951506 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 22951506 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 22951506 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 22951506 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25717.618054 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25717.618054 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25717.618054 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25717.618054 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 13853 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13853 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15819 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 15819 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 15819 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 15819 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15819 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15819 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 391009000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 391009000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 391009000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 391009000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 391009000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 391009000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24717.681269 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24717.681269 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2479.710860 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 26619 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3667 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.259067 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.780381 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.965355 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 359.965124 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064147 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010985 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.075675 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3667 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2507 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111908 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 261876 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 261876 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 13853 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 13853 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12649 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 12649 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 12649 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 12728 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 12649 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 12728 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1719 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3169 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 3169 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 432 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 432 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3169 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 2151 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 5320 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3169 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5320 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128506000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 128506000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 234465500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 234465500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35663000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 35663000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 234465500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 164169000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 398634500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 234465500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 164169000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 398634500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 13853 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 13853 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15818 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 15818 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 485 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 485 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 15818 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2230 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 18048 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 15818 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2230 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 18048 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985100 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200341 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200341 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.890722 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.890722 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200341 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964574 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.294770 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200341 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.294770 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74756.253636 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74756.253636 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73987.219943 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73987.219943 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82553.240741 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82553.240741 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74931.296992 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74931.296992 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3169 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3169 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 432 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 432 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111316000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111316000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202775500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202775500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31343000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31343000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202775500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 142659000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 345434500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202775500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 142659000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 345434500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200341 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294770 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294770 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64756.253636 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64756.253636 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63987.219943 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63987.219943 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72553.240741 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72553.240741 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 32058 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14010 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 16303 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 13853 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15818 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45489 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 50106 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2048512 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18048 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18048 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18048 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 29989000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 23727000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 3601 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1719 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1719 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 3601 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10640 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10640 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 340480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 5320 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 5320 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5320 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 6419000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 28167750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,882 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.130383 # Number of seconds simulated
|
||||
sim_ticks 130382890500 # Number of ticks simulated
|
||||
final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 248771 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 262245 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188230845 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275588 # Number of bytes of host memory used
|
||||
host_seconds 692.68 # Real time elapsed on the host
|
||||
sim_insts 172317810 # Number of instructions simulated
|
||||
sim_ops 181650743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 247424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1059280 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 838392 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1897672 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1059280 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1059280 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1059280 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 838392 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1897672 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 3866 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 247424 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 247424 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 305 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 217 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 135 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 313 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 306 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 305 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 273 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 222 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 248 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 218 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 295 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 200 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 183 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 218 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 224 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 204 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 130382796000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 3866 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 915 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 268.939891 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 176.781102 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 276.529935 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 273 29.84% 29.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 347 37.92% 67.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 83 9.07% 76.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 59 6.45% 83.28% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 35 3.83% 87.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 24 2.62% 89.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 16 1.75% 91.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 20 2.19% 93.66% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 58 6.34% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 915 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 27071500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 99559000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7002.46 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25752.46 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.01 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 2948 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 33725503.36 # Average gap between requests
|
||||
system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3144960 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1716000 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 3562127505 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 75103936500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 87202954965 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.831686 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 124939990750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 4353700000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1087339250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 3764880 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2054250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 3544157970 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.803682 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 49622074 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 260765781 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 172317810 # Number of instructions committed
|
||||
system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.513284 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.660815 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 181650743 # Class of committed instruction
|
||||
system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 42 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 40709197 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 40709197 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 40709659 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 40709659 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2441 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 59629000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 59629000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 126003000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 126003000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 185632000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 185632000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 185632000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 185632000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 28347350 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 28347350 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 40711637 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 40711637 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 40712100 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 40712100 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 76078.688525 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 16 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52555500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 52555500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85213000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85213000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137768500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 137768500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137838500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 137838500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 2881 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 70779397 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4678 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4678 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4678 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 198432500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 198432500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 198432500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 198432500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 198432500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 198432500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 70784075 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 70784075 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 70784075 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 70784075 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 70784075 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 70784075 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42418.234288 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 42418.234288 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 42418.234288 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 2881 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2881 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4678 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4678 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4678 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4678 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4678 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4678 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193755500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 193755500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 193755500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 193755500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 193755500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 193755500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 489.811820 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045981 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.061021 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2783 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 2559 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2517 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 2517 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 81 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 81 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2517 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 89 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2606 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 2517 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 89 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2606 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2161 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2161 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 631 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 631 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2161 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 3883 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 3883 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83479000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 83479000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 159937500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 159937500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50622000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 50622000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 159937500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 134101000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 294038500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 159937500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 134101000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 294038500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 2559 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 2559 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4678 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 4678 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 4678 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 6489 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 4678 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 6489 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461950 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461950 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886236 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886236 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461950 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.950856 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.598397 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461950 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.950856 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.598397 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75724.568633 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2159 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2159 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72569000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72569000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 138134000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 138134000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43490000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43490000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138134000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116059000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 254193000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138134000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116059000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 254193000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461522 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.595932 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.595932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12236 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 15900 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 600640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6489 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.071197 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.257174 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 6027 92.88% 92.88% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 462 7.12% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 2775 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1091 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1091 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 247424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3866 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3866 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3866 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4516500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 20548250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.869358 # Number of seconds simulated
|
||||
sim_ticks 1869357988000 # Number of ticks simulated
|
||||
final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 1869357999000 # Number of ticks simulated
|
||||
final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1670594 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1670593 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 48045239456 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332628 # Number of bytes of host memory used
|
||||
host_seconds 38.91 # Real time elapsed on the host
|
||||
host_inst_rate 1770526 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1770526 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 50919239991 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 331076 # Number of bytes of host memory used
|
||||
host_seconds 36.71 # Real time elapsed on the host
|
||||
sim_insts 64999904 # Number of instructions simulated
|
||||
sim_ops 64999904 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -49,7 +49,7 @@ system.physmem.bw_total::cpu0.data 35592763 # To
|
|||
system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 40657621 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 40657620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -83,7 +83,7 @@ system.cpu0.itb.data_hits 0 # DT
|
|||
system.cpu0.itb.data_misses 0 # DTB misses
|
||||
system.cpu0.itb.data_acv 0 # DTB access violations
|
||||
system.cpu0.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu0.numCycles 3738722771 # number of cpu cycles simulated
|
||||
system.cpu0.numCycles 3738722793 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
@ -101,12 +101,12 @@ system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # nu
|
|||
system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::0 1853222732000 99.14% 99.14% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::total 1869357791500 # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
|
|
@ -172,7 +172,7 @@ system.cpu0.kern.mode_switch_good::kernel 0.177764 # f
|
|||
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::kernel 1868349163500 99.95% 99.95% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.swap_context 2744 # number of times the context was actually changed
|
||||
|
|
@ -191,7 +191,7 @@ system.cpu0.num_fp_register_writes 98967 # nu
|
|||
system.cpu0.num_mem_refs 12536107 # number of memory refs
|
||||
system.cpu0.num_load_insts 7783754 # Number of load instructions
|
||||
system.cpu0.num_store_insts 4752353 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles
|
||||
system.cpu0.num_idle_cycles 3689239810.666409 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles
|
||||
|
|
@ -231,13 +231,13 @@ system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Cl
|
|||
system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::total 49485886 # Class of executed instruction
|
||||
system.cpu0.dcache.tags.replacements 1781371 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.replacements 1781367 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 506.187330 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187330 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
|
|
@ -245,32 +245,32 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446
|
|||
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits
|
||||
system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 4360085 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 4360085 # number of WriteReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132849 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 132849 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 10428966 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 10428966 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 10428966 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 10428966 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 10428970 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 10428970 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 10428970 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 10428970 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 1560065 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 1560065 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 236538 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::total 236538 # number of WriteReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6921 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 6921 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 1796607 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 1796607 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 1796607 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 1796607 # number of overall misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 1796603 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 1796603 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 1796603 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 1796603 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -301,8 +301,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.writebacks::writebacks 633127 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 633127 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::writebacks 633126 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 633126 # number of writebacks
|
||||
system.cpu0.icache.tags.replacements 618292 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks.
|
||||
|
|
@ -383,7 +383,7 @@ system.cpu1.itb.data_hits 0 # DT
|
|||
system.cpu1.itb.data_misses 0 # DTB misses
|
||||
system.cpu1.itb.data_acv 0 # DTB access violations
|
||||
system.cpu1.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu1.numCycles 3738296587 # number of cpu cycles simulated
|
||||
system.cpu1.numCycles 3738296609 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
@ -399,11 +399,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu
|
|||
system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::0 1856123501500 99.30% 99.30% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::total 1869146939500 # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
||||
|
|
@ -457,7 +457,7 @@ system.cpu1.kern.mode_switch_good::idle 0.177356 # fr
|
|||
system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::idle 1862102413500 99.66% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.swap_context 2507 # number of times the context was actually changed
|
||||
system.cpu1.committedInsts 15522159 # Number of instructions committed
|
||||
system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed
|
||||
|
|
@ -474,8 +474,8 @@ system.cpu1.num_fp_register_writes 104129 # nu
|
|||
system.cpu1.num_mem_refs 4961786 # number of memory refs
|
||||
system.cpu1.num_load_insts 2849090 # Number of load instructions
|
||||
system.cpu1.num_store_insts 2112696 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles
|
||||
system.cpu1.num_idle_cycles 3722773671.474783 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 15522937.525217 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles
|
||||
system.cpu1.Branches 2214163 # Number of branches fetched
|
||||
|
|
@ -515,12 +515,12 @@ system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Cl
|
|||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 15525875 # Class of executed instruction
|
||||
system.cpu1.dcache.tags.replacements 201757 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.tagsinuse 497.601962 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601962 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
|
||||
|
|
@ -590,7 +590,7 @@ system.cpu1.icache.tags.tagsinuse 453.133719 # Cy
|
|||
system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.tags.warmup_cycle 1859777195500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy
|
||||
|
|
@ -679,7 +679,7 @@ system.iocache.tags.tagsinuse 0.434096 # Cy
|
|||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.warmup_cycle 1685787164517 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy
|
||||
|
|
@ -721,16 +721,16 @@ system.iocache.avg_blocked_cycles::no_targets nan
|
|||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
system.iocache.writebacks::total 41520 # number of writebacks
|
||||
system.l2c.tags.replacements 999922 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65337.856722 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4259784 # Total number of references to valid blocks.
|
||||
system.l2c.tags.tagsinuse 65337.856710 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4259780 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1064972 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 3.999902 # Average number of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 3.999899 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 55997.404251 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4860.296117 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4190.275222 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 175.171528 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 114.709605 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::writebacks 55997.404382 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4860.296070 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4190.275138 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 175.171519 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 114.709600 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.854453 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.063939 # Average percentage of cache occupancy
|
||||
|
|
@ -744,37 +744,37 @@ system.l2c.tags.age_task_id_blocks_1024::2 6047 #
|
|||
system.l2c.tags.age_task_id_blocks_1024::3 5933 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 49031 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 46377222 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 46377222 # Number of data accesses
|
||||
system.l2c.WritebackDirty_hits::writebacks 777663 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 777663 # number of WritebackDirty hits
|
||||
system.l2c.WritebackClean_hits::writebacks 721478 # number of WritebackClean hits
|
||||
system.l2c.WritebackClean_hits::total 721478 # number of WritebackClean hits
|
||||
system.l2c.tags.tag_accesses 46377199 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 46377199 # Number of data accesses
|
||||
system.l2c.WritebackDirty_hits::writebacks 777662 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 777662 # number of WritebackDirty hits
|
||||
system.l2c.WritebackClean_hits::writebacks 721480 # number of WritebackClean hits
|
||||
system.l2c.WritebackClean_hits::total 721480 # number of WritebackClean hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 604 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 56605 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 168080 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 168081 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 626719 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 755730 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 626716 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 129010 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 755726 # number of ReadSharedReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 738194 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 738192 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1910410 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 185615 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1910407 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 738194 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 738192 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 185616 # number of overall hits
|
||||
system.l2c.overall_hits::total 1910410 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 185615 # number of overall hits
|
||||
system.l2c.overall_hits::total 1910407 # number of overall hits
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 2989 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 2147 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 5136 # number of UpgradeReq misses
|
||||
|
|
@ -800,57 +800,57 @@ system.l2c.overall_misses::cpu0.data 1040486 # nu
|
|||
system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 12101 # number of overall misses
|
||||
system.l2c.overall_misses::total 1066093 # number of overall misses
|
||||
system.l2c.WritebackDirty_accesses::writebacks 777663 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 777663 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::writebacks 721478 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::total 721478 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::writebacks 777662 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 777662 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::writebacks 721480 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::total 721480 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 3119 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 5870 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu0.data 1209 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 2332 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 225347 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 293018 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu0.data 1553334 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::total 1683380 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu0.data 1553331 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.data 130045 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::total 1683376 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 1778680 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 1778678 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2976503 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 197716 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2976500 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 1778680 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 1778678 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2976503 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 197716 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2976500 # number of overall (read+write) accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.958320 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780443 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.874957 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963606 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975067 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.969125 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.505316 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.505314 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.163526 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.426381 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.426380 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596533 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596534 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.551064 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.551065 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.584976 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.584977 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.358170 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.584976 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.584977 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.358170 # miss rate for overall accesses
|
||||
|
|
@ -862,6 +862,12 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
|
|||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.writebacks::writebacks 80923 # number of writebacks
|
||||
system.l2c.writebacks::total 80923 # number of writebacks
|
||||
system.membus.snoop_filter.tot_requests 2182334 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 1076327 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 430 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.trans_dist::ReadReq 7449 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948784 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||
|
|
@ -871,17 +877,17 @@ system.membus.trans_dist::CleanEvict 918012 # Tr
|
|||
system.membus.trans_dist::UpgradeReq 19594 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 14154 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 8111 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 125245 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 125244 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 124222 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941335 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172394 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 3216468 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172393 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 3216467 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3341629 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3341628 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 73449426 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -889,61 +895,61 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736
|
|||
system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 76118162 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2204372 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 2204371 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.000517 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.022725 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2204372 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2203232 99.95% 99.95% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 1139 0.05% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2204372 # Request fanout histogram
|
||||
system.toL2Bus.snoop_filter.tot_requests 6035855 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 3018704 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 374458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_fanout::total 2204371 # Request fanout histogram
|
||||
system.toL2Bus.snoop_filter.tot_requests 6035847 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 3018700 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 374456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 777663 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 777662 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1205465 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1205462 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 19613 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 14226 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 33839 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadSharedReq 1724580 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450139 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450127 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684385 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 9133717 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 9133705 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766779 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766459 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23358423 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 307065426 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1083516 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 7141244 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.105534 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.307488 # Request fanout histogram
|
||||
system.toL2Bus.pkt_size::total 307065106 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1000943 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 7058663 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.106768 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.309067 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 6388144 89.45% 89.45% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 752560 10.54% 99.99% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 6305567 89.33% 89.33% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 752556 10.66% 99.99% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 7141244 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 7058663 # Request fanout histogram
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu
|
|||
sim_ticks 1829331993500 # Number of ticks simulated
|
||||
final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1840131 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1840130 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56067507873 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 330836 # Number of bytes of host memory used
|
||||
host_seconds 32.63 # Real time elapsed on the host
|
||||
host_inst_rate 1838030 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1838029 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56003449171 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 325188 # Number of bytes of host memory used
|
||||
host_seconds 32.66 # Real time elapsed on the host
|
||||
sim_insts 60038469 # Number of instructions simulated
|
||||
sim_ops 60038469 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 1.941276 # Nu
|
|||
sim_ticks 1941275996000 # Number of ticks simulated
|
||||
final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1048317 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1048317 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 36222399744 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 330588 # Number of bytes of host memory used
|
||||
host_seconds 53.59 # Real time elapsed on the host
|
||||
host_inst_rate 855166 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 855166 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29548473540 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 325188 # Number of bytes of host memory used
|
||||
host_seconds 65.70 # Real time elapsed on the host
|
||||
sim_insts 56182685 # Number of instructions simulated
|
||||
sim_ops 56182685 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
|
|||
sim_ticks 2783854535000 # Number of ticks simulated
|
||||
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1211130 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1474356 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 23615387886 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 581436 # Number of bytes of host memory used
|
||||
host_seconds 117.88 # Real time elapsed on the host
|
||||
host_inst_rate 1008697 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1227927 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 19668230366 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 576064 # Number of bytes of host memory used
|
||||
host_seconds 141.54 # Real time elapsed on the host
|
||||
sim_insts 142771651 # Number of instructions simulated
|
||||
sim_ops 173801592 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
|
|||
sim_ticks 2783854535000 # Number of ticks simulated
|
||||
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1225194 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1491477 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 23889629831 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 578692 # Number of bytes of host memory used
|
||||
host_seconds 116.53 # Real time elapsed on the host
|
||||
host_inst_rate 888036 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1081042 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 17315504636 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 573724 # Number of bytes of host memory used
|
||||
host_seconds 160.77 # Real time elapsed on the host
|
||||
sim_insts 142771651 # Number of instructions simulated
|
||||
sim_ops 173801592 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.909587 # Nu
|
|||
sim_ticks 2909586837500 # Number of ticks simulated
|
||||
final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 812558 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 979692 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 21023218607 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 578440 # Number of bytes of host memory used
|
||||
host_seconds 138.40 # Real time elapsed on the host
|
||||
host_inst_rate 581636 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 701272 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15048595995 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 573724 # Number of bytes of host memory used
|
||||
host_seconds 193.35 # Real time elapsed on the host
|
||||
sim_insts 112457033 # Number of instructions simulated
|
||||
sim_ops 135588117 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu
|
|||
sim_ticks 5112151729000 # Number of ticks simulated
|
||||
final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1369712 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2804100 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34999130987 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 614748 # Number of bytes of host memory used
|
||||
host_seconds 146.07 # Real time elapsed on the host
|
||||
host_inst_rate 1314225 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2690507 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33581335470 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 609616 # Number of bytes of host memory used
|
||||
host_seconds 152.23 # Real time elapsed on the host
|
||||
sim_insts 200067055 # Number of instructions simulated
|
||||
sim_ops 409581065 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.194946 # Nu
|
|||
sim_ticks 5194946000500 # Number of ticks simulated
|
||||
final_tick 5194946000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 910377 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1754736 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 36822413305 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 616280 # Number of bytes of host memory used
|
||||
host_seconds 141.08 # Real time elapsed on the host
|
||||
host_inst_rate 930999 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1794485 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 37656529565 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 609616 # Number of bytes of host memory used
|
||||
host_seconds 137.96 # Real time elapsed on the host
|
||||
sim_insts 128436892 # Number of instructions simulated
|
||||
sim_ops 247560077 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu
|
|||
sim_ticks 200409271000 # Number of ticks simulated
|
||||
final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 7747436 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 7747432 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2964324473 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 475456 # Number of bytes of host memory used
|
||||
host_seconds 67.61 # Real time elapsed on the host
|
||||
host_inst_rate 17114164 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 17114158 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6548224120 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 490760 # Number of bytes of host memory used
|
||||
host_seconds 30.61 # Real time elapsed on the host
|
||||
sim_insts 523780905 # Number of instructions simulated
|
||||
sim_ops 523780905 # Number of ops (including micro ops) simulated
|
||||
drivesys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -619,11 +619,11 @@ sim_seconds 0.000407 # Nu
|
|||
sim_ticks 407341500 # Number of ticks simulated
|
||||
final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3441354505 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3440623178 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2674872126 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 475456 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 9054438128 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 9052667837 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 7037972394 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 490760 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 523853183 # Number of instructions simulated
|
||||
sim_ops 523853183 # Number of ops (including micro ops) simulated
|
||||
drivesys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000037 # Nu
|
|||
sim_ticks 37494000 # Number of ticks simulated
|
||||
final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 141195 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 141164 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 825166364 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252900 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_inst_rate 176621 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 176529 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1031613588 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248004 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 6413 # Number of instructions simulated
|
||||
sim_ops 6413 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
|
|||
sim_ticks 22019000 # Number of ticks simulated
|
||||
final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 140516 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 140486 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 484379589 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253664 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_inst_rate 115969 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 115940 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 399737091 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249288 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 6385 # Number of instructions simulated
|
||||
sim_ops 6385 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
|
|||
sim_ticks 3214500 # Number of ticks simulated
|
||||
final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 21023 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 21020 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 10551583 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 216888 # Number of bytes of host memory used
|
||||
host_seconds 0.30 # Real time elapsed on the host
|
||||
host_inst_rate 1011674 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1009913 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 506215370 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237756 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6403 # Number of instructions simulated
|
||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu
|
|||
sim_ticks 121535 # Number of ticks simulated
|
||||
final_tick 121535 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 23854 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 23852 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 452710 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 387364 # Number of bytes of host memory used
|
||||
host_seconds 0.27 # Real time elapsed on the host
|
||||
host_inst_rate 71837 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 71828 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1363198 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 407704 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 6403 # Number of instructions simulated
|
||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000109 # Nu
|
|||
sim_ticks 108878 # Number of ticks simulated
|
||||
final_tick 108878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 17471 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 17470 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 297052 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 393472 # Number of bytes of host memory used
|
||||
host_seconds 0.37 # Real time elapsed on the host
|
||||
host_inst_rate 68389 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 68380 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1162621 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 413676 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 6403 # Number of instructions simulated
|
||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu
|
|||
sim_ticks 108253 # Number of ticks simulated
|
||||
final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 39556 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 39552 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 668635 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 388512 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_inst_rate 4411 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 4411 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 74577 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 409256 # Number of bytes of host memory used
|
||||
host_seconds 1.45 # Real time elapsed on the host
|
||||
sim_insts 6403 # Number of instructions simulated
|
||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000087 # Nu
|
|||
sim_ticks 86770 # Number of ticks simulated
|
||||
final_tick 86770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 43915 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 43910 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 594975 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 388108 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 99240 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 99218 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1344283 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 407932 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 6403 # Number of instructions simulated
|
||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu
|
|||
sim_ticks 107065 # Number of ticks simulated
|
||||
final_tick 107065 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 18652 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 18652 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 311861 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 390536 # Number of bytes of host memory used
|
||||
host_seconds 0.34 # Real time elapsed on the host
|
||||
host_inst_rate 109103 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 109072 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1823360 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 411068 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 6403 # Number of instructions simulated
|
||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000036 # Nu
|
|||
sim_ticks 35682500 # Number of ticks simulated
|
||||
final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 421865 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 421312 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2345119890 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251096 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_inst_rate 581025 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 580437 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3231677275 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247496 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6403 # Number of instructions simulated
|
||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu
|
|||
sim_ticks 20320000 # Number of ticks simulated
|
||||
final_tick 20320000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 183657 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 183501 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1441333472 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251592 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 154508 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 154391 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1212791416 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 246696 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 2585 # Number of instructions simulated
|
||||
sim_ops 2585 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue