1195 lines
138 KiB
Text
1195 lines
138 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.907083 # Number of seconds simulated
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sim_ticks 1907083088000 # Number of ticks simulated
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final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 20329 # Simulator instruction rate (inst/s)
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host_op_rate 20329 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 690572794 # Simulator tick rate (ticks/s)
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host_mem_usage 384580 # Number of bytes of host memory used
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host_seconds 2761.60 # Real time elapsed on the host
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sim_insts 56139550 # Number of instructions simulated
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sim_ops 56139550 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 1045632 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24852608 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 25899200 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 1045632 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1045632 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7558144 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7558144 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 16338 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 388322 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 404675 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 118096 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 118096 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 548289 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 13031738 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13580530 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 548289 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 548289 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3963196 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 3963196 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3963196 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 548289 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 13031738 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17543726 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 404675 # Number of read requests accepted
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system.physmem.writeReqs 118096 # Number of write requests accepted
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system.physmem.readBursts 404675 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 118096 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 25892096 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7556352 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 25899200 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7558144 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 25475 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25702 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25824 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25771 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25094 # Per bank write bursts
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system.physmem.perBankRdBursts::5 25022 # Per bank write bursts
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system.physmem.perBankRdBursts::6 24642 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24532 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25301 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25195 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25365 # Per bank write bursts
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system.physmem.perBankRdBursts::11 25031 # Per bank write bursts
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system.physmem.perBankRdBursts::12 24528 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25559 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25792 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25731 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7824 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7667 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8078 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7735 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7199 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7011 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6644 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6403 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7407 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6813 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7251 # Per bank write bursts
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system.physmem.perBankWrBursts::11 7009 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7080 # Per bank write bursts
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system.physmem.perBankWrBursts::13 8008 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7995 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7944 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
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system.physmem.totGap 1907074301500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 404675 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 118096 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 402295 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 2190 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1480 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2865 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 7261 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5935 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 6910 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 6065 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5979 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 6478 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 6947 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 6490 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 8391 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 8689 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 7302 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 7698 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 6991 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 7145 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5952 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5549 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 210 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 174 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 118 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 199 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 118 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 164 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 131 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 191 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 172 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 207 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 158 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 161 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 116 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 113 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 76 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 114 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 91 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 64552 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 518.162845 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 316.762326 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 407.336965 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 15022 23.27% 23.27% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 11126 17.24% 40.51% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 5008 7.76% 48.26% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 3170 4.91% 53.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2578 3.99% 57.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1854 2.87% 60.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 4219 6.54% 66.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1366 2.12% 68.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 20209 31.31% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 64552 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5276 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 76.676839 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 2890.632458 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-8191 5273 99.94% 99.94% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5276 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5276 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 22.378317 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 19.075849 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 20.638302 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::16-23 4671 88.53% 88.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-31 37 0.70% 89.23% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-39 29 0.55% 89.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-47 43 0.82% 90.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-55 200 3.79% 94.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-63 11 0.21% 94.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-71 10 0.19% 94.79% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-79 32 0.61% 95.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-87 177 3.35% 98.75% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-95 7 0.13% 98.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-103 14 0.27% 99.15% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-111 4 0.08% 99.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-135 4 0.08% 99.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-159 1 0.02% 99.43% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-167 3 0.06% 99.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::168-175 6 0.11% 99.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-183 5 0.09% 99.70% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::184-191 5 0.09% 99.79% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-199 1 0.02% 99.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::200-207 3 0.06% 99.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-215 4 0.08% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::256-263 3 0.06% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5276 # Writes before turning the bus around for reads
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system.physmem.totQLat 2650883750 # Total ticks spent queuing
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system.physmem.totMemAccLat 10236458750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2022820000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 6552.45 # Average queueing delay per DRAM burst
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|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 25302.45 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 13.58 # Average DRAM read bandwidth in MiByte/s
|
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system.physmem.avgWrBW 3.96 # Average achieved write bandwidth in MiByte/s
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|
system.physmem.avgRdBWSys 13.58 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 3.96 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.14 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 21.50 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 362672 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 95408 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3648010.89 # Average gap between requests
|
|
system.physmem.pageHitRate 87.64 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 238359240 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 130057125 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1576083600 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 379475280 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 124561092240 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 67798389510 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1084774932000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1279458388995 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 670.899637 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 1804362652750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 63681540000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 39034493500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 249653880 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 136219875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1579515600 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 385605360 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 124561092240 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 68553947025 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1084112170500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1279578204480 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 670.962459 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 1803261638750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 63681540000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 40135521250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 15213605 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 13089935 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 512661 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 11946485 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 4550663 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 38.092066 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 861069 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 32299 # Number of incorrect RAS predictions.
|
|
system.cpu.branchPred.indirectLookups 6536873 # Number of indirect predictor lookups.
|
|
system.cpu.branchPred.indirectHits 544356 # Number of indirect target hits.
|
|
system.cpu.branchPred.indirectMisses 5992517 # Number of indirect misses.
|
|
system.cpu.branchPredindirectMispredicted 219108 # Number of mispredicted indirect branches.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 9320625 # DTB read hits
|
|
system.cpu.dtb.read_misses 17559 # DTB read misses
|
|
system.cpu.dtb.read_acv 211 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 766669 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6392876 # DTB write hits
|
|
system.cpu.dtb.write_misses 2428 # DTB write misses
|
|
system.cpu.dtb.write_acv 159 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 298894 # DTB write accesses
|
|
system.cpu.dtb.data_hits 15713501 # DTB hits
|
|
system.cpu.dtb.data_misses 19987 # DTB misses
|
|
system.cpu.dtb.data_acv 370 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1065563 # DTB accesses
|
|
system.cpu.itb.fetch_hits 4013626 # ITB hits
|
|
system.cpu.itb.fetch_misses 6348 # ITB misses
|
|
system.cpu.itb.fetch_acv 677 # ITB acv
|
|
system.cpu.itb.fetch_accesses 4019974 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 223105667 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 56139550 # Number of instructions committed
|
|
system.cpu.committedOps 56139550 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 2984225 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 5570 # Number of times Execute suspended instruction fetching
|
|
system.cpu.quiesceCycles 3591060509 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.cpi 3.974126 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.251628 # IPC: instructions per cycle
|
|
system.cpu.op_class_0::No_OpClass 3199335 5.70% 5.70% # Class of committed instruction
|
|
system.cpu.op_class_0::IntAlu 36193553 64.47% 70.17% # Class of committed instruction
|
|
system.cpu.op_class_0::IntMult 60844 0.11% 70.28% # Class of committed instruction
|
|
system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.op_class_0::MemRead 9319847 16.60% 86.95% # Class of committed instruction
|
|
system.cpu.op_class_0::MemWrite 6372583 11.35% 98.30% # Class of committed instruction
|
|
system.cpu.op_class_0::IprAccess 951665 1.70% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::total 56139550 # Class of committed instruction
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211602 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74817 40.93% 40.93% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105924 57.95% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 182777 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73450 49.32% 49.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73450 49.32% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 148936 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1838095236500 96.38% 96.38% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 85937000 0.00% 96.39% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 709530500 0.04% 96.42% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 68191372500 3.58% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1907082076500 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981729 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.693422 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::total 0.814851 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175610 91.22% 93.43% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5130 2.66% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 192505 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5879 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1907
|
|
system.cpu.kern.mode_good::user 1738
|
|
system.cpu.kern.mode_good::idle 169
|
|
system.cpu.kern.mode_switch_good::kernel 0.324375 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.392750 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 38852804500 2.04% 2.04% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 4558296500 0.24% 2.28% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1863670965500 97.72% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
|
system.cpu.tickCycles 85299333 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 137806334 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 1394573 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.976747 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 13828974 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1395085 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 9.912639 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.976747 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 63880747 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 63880747 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7869575 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7869575 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 5576818 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 5576818 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183500 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 183500 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 199049 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 199049 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 13446393 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 13446393 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 13446393 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 13446393 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1201253 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1201253 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 574650 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 574650 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 16570 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 16570 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1775903 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1775903 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1775903 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1775903 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 46959686500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 46959686500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 33959629000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 33959629000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 226795500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 226795500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 80919315500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 80919315500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 80919315500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 80919315500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9070828 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9070828 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6151468 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6151468 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200070 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 200070 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199049 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 199049 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15222296 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15222296 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15222296 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15222296 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132430 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.132430 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093417 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.093417 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082821 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082821 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.116665 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.116665 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.116665 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.116665 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.253256 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.253256 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59096.195945 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 59096.195945 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13687.115269 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13687.115269 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45565.166284 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 45565.166284 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45565.166284 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 45565.166284 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.writebacks::writebacks 837991 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 837991 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 126783 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 126783 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270556 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 270556 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 397339 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 397339 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 397339 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 397339 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074470 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1074470 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304094 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 304094 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16567 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 16567 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1378564 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1378564 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1378564 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1378564 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43809627000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 43809627000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17274972500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17274972500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 209962500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 209962500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61084599500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 61084599500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61084599500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 61084599500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528608000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528608000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528608000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528608000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118453 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118453 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049434 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049434 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082806 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082806 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090562 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.090562 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090562 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.090562 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40773.243553 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40773.243553 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56808.001802 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56808.001802 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12673.537756 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12673.537756 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641 # average overall mshr uncacheable latency
|
|
system.cpu.icache.tags.replacements 1471396 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 508.107952 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 19138982 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1471907 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 13.002847 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 50134801500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 508.107952 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.992398 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.992398 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 22083145 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 22083145 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 19138985 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 19138985 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 19138985 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 19138985 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 19138985 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 19138985 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1472080 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1472080 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1472080 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1472080 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1472080 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1472080 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21152422000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 21152422000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 21152422000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 21152422000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 21152422000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 21152422000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 20611065 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 20611065 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 20611065 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 20611065 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 20611065 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 20611065 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071422 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.071422 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.071422 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.071422 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.071422 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.071422 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14369.070974 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14369.070974 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14369.070974 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 14369.070974 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14369.070974 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 14369.070974 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.writebacks::writebacks 1471396 # number of writebacks
|
|
system.cpu.icache.writebacks::total 1471396 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1472080 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1472080 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1472080 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1472080 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1472080 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1472080 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19680342000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 19680342000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19680342000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 19680342000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19680342000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 19680342000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071422 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.071422 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.071422 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13369.070974 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13369.070974 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency
|
|
system.cpu.l2cache.tags.replacements 339491 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65257.604073 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 5020229 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 404654 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 12.406226 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 9688326000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 54061.905720 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5741.199661 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 5454.498692 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.824919 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087604 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.083229 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.995752 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 883 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5606 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2934 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55510 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 46558497 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 46558497 # Number of data accesses
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 837991 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 837991 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 1470820 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 1470820 # number of WritebackClean hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 187526 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 187526 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1455685 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 1455685 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818815 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 818815 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1455685 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1006341 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2462026 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1455685 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1006341 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2462026 # number of overall hits
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 15 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 15 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 116580 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 116580 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16339 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 16339 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272190 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 272190 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 16339 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 388770 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 405109 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 16339 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 388770 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 405109 # number of overall misses
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 396000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 396000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14843351000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 14843351000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2147420500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2147420500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33672693000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 33672693000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 2147420500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 48516044000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 50663464500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 2147420500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 48516044000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 50663464500 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 837991 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 837991 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 1470820 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 1470820 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304106 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 304106 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1472024 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 1472024 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091005 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 1091005 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1472024 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1395111 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2867135 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1472024 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1395111 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2867135 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383353 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383353 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011100 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011100 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249486 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249486 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011100 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.278666 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.141294 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011100 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.278666 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.141294 # miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 26400 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 26400 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127323.305884 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127323.305884 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131429.126630 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131429.126630 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123710.250193 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123710.250193 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131429.126630 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124793.692929 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 125061.315597 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131429.126630 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124793.692929 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 125061.315597 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.writebacks::writebacks 76584 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 76584 # number of writebacks
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 15 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 15 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116580 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 116580 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16339 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16339 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272190 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272190 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16339 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 388770 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 405109 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16339 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 388770 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 405109 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1037000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1037000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13677551000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13677551000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1984030500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1984030500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30953906500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30953906500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1984030500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631457500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 46615488000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1984030500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631457500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 46615488000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1441963500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1441963500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1441963500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1441963500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383353 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383353 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011100 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249486 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249486 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278666 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.141294 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278666 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.141294 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69133.333333 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69133.333333 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117323.305884 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117323.305884 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121429.126630 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121429.126630 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113721.688894 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113721.688894 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208075.541126 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208075.541126 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87111.913248 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87111.913248 # average overall mshr uncacheable latency
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 5733180 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2866165 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2570147 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 956097 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 1471396 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 819662 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 304106 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 304106 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1472080 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091178 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4415500 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4218097 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 8633597 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 188378880 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142971324 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 331350204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 423123 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 3306675 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.001025 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.031993 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 3303287 99.90% 99.90% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 3388 0.10% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 3306675 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5189065000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 2208337564 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2104397493 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51175 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 51175 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33106 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 116556 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20408 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 5407500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 805000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 10000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 188500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 14677500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 2309500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 6005500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 93000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 215722666 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.298739 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1748617417000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.298739 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.081171 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.081171 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375525 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
|
system.iocache.overall_misses::total 41725 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245324283 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 5245324283 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 5267241666 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 5267241666 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 5267241666 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 5267241666 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126235.182013 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 126235.182013 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 126237.068089 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 126237.068089 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 83 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 13.833333 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
|
system.iocache.writebacks::total 41512 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165924983 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 3165924983 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 3179192366 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 3179192366 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 3179192366 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 3179192366 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency
|
|
system.membus.trans_dist::ReadReq 6930 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 295608 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9623 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9623 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 118096 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 262242 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 167 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 116428 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 116428 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 288702 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 24 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148413 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181567 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1264992 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30799616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30843964 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 33501692 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 433 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 843750 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 843750 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 843750 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 29507500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1318874217 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 29500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2159448000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
|
|
---------- End Simulation Statistics ----------
|