1988 lines
226 KiB
Text
1988 lines
226 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.841599 # Number of seconds simulated
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sim_ticks 1841599161000 # Number of ticks simulated
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final_tick 1841599161000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 245408 # Simulator instruction rate (inst/s)
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host_op_rate 245408 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6773643024 # Simulator tick rate (ticks/s)
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host_mem_usage 331844 # Number of bytes of host memory used
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host_seconds 271.88 # Real time elapsed on the host
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sim_insts 66720805 # Number of instructions simulated
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sim_ops 66720805 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 472448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 20115392 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 2145088 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 298752 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 2611904 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 25791552 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 472448 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 298752 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 918208 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7488832 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7488832 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.inst 7382 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 314303 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 33517 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 4668 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 40811 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 402993 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 117013 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 117013 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 256542 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 10922785 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 79826 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 1164796 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 162224 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 1418280 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 14004976 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 256542 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 79826 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 162224 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 498593 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4066483 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4066483 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4066483 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 256542 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 10922785 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 79826 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 1164796 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 162224 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 1418280 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 18071459 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 81308 # Number of read requests accepted
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system.physmem.writeReqs 46917 # Number of write requests accepted
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system.physmem.readBursts 81308 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 46917 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 5202560 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue
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system.physmem.bytesWritten 3000896 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 5203712 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 3002688 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 4879 # Per bank write bursts
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system.physmem.perBankRdBursts::1 4860 # Per bank write bursts
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system.physmem.perBankRdBursts::2 4840 # Per bank write bursts
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system.physmem.perBankRdBursts::3 5116 # Per bank write bursts
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system.physmem.perBankRdBursts::4 5145 # Per bank write bursts
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system.physmem.perBankRdBursts::5 5201 # Per bank write bursts
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system.physmem.perBankRdBursts::6 5134 # Per bank write bursts
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system.physmem.perBankRdBursts::7 5033 # Per bank write bursts
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system.physmem.perBankRdBursts::8 5242 # Per bank write bursts
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system.physmem.perBankRdBursts::9 4887 # Per bank write bursts
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system.physmem.perBankRdBursts::10 5474 # Per bank write bursts
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system.physmem.perBankRdBursts::11 5136 # Per bank write bursts
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system.physmem.perBankRdBursts::12 4904 # Per bank write bursts
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system.physmem.perBankRdBursts::13 4973 # Per bank write bursts
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system.physmem.perBankRdBursts::14 5564 # Per bank write bursts
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system.physmem.perBankRdBursts::15 4902 # Per bank write bursts
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system.physmem.perBankWrBursts::0 2770 # Per bank write bursts
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system.physmem.perBankWrBursts::1 2825 # Per bank write bursts
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system.physmem.perBankWrBursts::2 2866 # Per bank write bursts
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system.physmem.perBankWrBursts::3 3058 # Per bank write bursts
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system.physmem.perBankWrBursts::4 2994 # Per bank write bursts
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system.physmem.perBankWrBursts::5 2828 # Per bank write bursts
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system.physmem.perBankWrBursts::6 3105 # Per bank write bursts
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system.physmem.perBankWrBursts::7 2723 # Per bank write bursts
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system.physmem.perBankWrBursts::8 3290 # Per bank write bursts
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system.physmem.perBankWrBursts::9 2741 # Per bank write bursts
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system.physmem.perBankWrBursts::10 3262 # Per bank write bursts
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system.physmem.perBankWrBursts::11 2912 # Per bank write bursts
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system.physmem.perBankWrBursts::12 2689 # Per bank write bursts
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system.physmem.perBankWrBursts::13 2734 # Per bank write bursts
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system.physmem.perBankWrBursts::14 3349 # Per bank write bursts
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system.physmem.perBankWrBursts::15 2743 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
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system.physmem.totGap 1840587284000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 81308 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 46917 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 63682 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 7542 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 5539 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 4493 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 50 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 762 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1293 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 1745 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 1920 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 2366 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 2522 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 2976 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 3539 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 2746 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 3095 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 3372 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 3090 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 2791 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 2903 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 2624 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 2247 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 2267 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 2163 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 143 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 94 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 60 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 74 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 67 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 51 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 52 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 72 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 83 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 102 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 89 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 52 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 40 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 68 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 85 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 37 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 21624 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 379.368110 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 215.960357 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 378.240859 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 7179 33.20% 33.20% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 4878 22.56% 55.76% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 1948 9.01% 64.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 1045 4.83% 69.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 873 4.04% 73.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 450 2.08% 75.72% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 417 1.93% 77.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 373 1.72% 79.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 4461 20.63% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 21624 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 2049 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 39.666179 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 981.071588 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-2047 2047 99.90% 99.90% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 2049 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 2049 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 22.883846 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 18.590123 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 22.999579 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::0-3 33 1.61% 1.61% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::4-7 8 0.39% 2.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::8-11 1 0.05% 2.05% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::12-15 3 0.15% 2.20% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-19 1695 82.72% 84.92% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20-23 48 2.34% 87.26% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24-27 10 0.49% 87.75% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::28-31 15 0.73% 88.48% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::32-35 91 4.44% 92.92% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::36-39 8 0.39% 93.31% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::40-43 1 0.05% 93.36% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::44-47 4 0.20% 93.56% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::48-51 2 0.10% 93.66% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::52-55 3 0.15% 93.80% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::56-59 2 0.10% 93.90% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::60-63 2 0.10% 94.00% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::64-67 2 0.10% 94.09% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 1 0.05% 94.14% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 2 0.10% 94.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 13 0.63% 94.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 4 0.20% 95.07% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 77 3.76% 98.83% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 1 0.05% 98.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 2 0.10% 98.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 2 0.10% 99.07% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-123 1 0.05% 99.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 2 0.10% 99.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.05% 99.27% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-139 1 0.05% 99.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 1 0.05% 99.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 1 0.05% 99.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-163 1 0.05% 99.46% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::172-175 4 0.20% 99.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::184-187 1 0.05% 99.71% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::188-191 1 0.05% 99.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::196-199 1 0.05% 99.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-227 4 0.20% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 2049 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 885699750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 2409887250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 406450000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 10895.56 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 29645.56 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 2.83 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.63 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 2.83 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.63 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 69553 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 37002 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 85.56 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 78.87 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 14354355.89 # Average gap between requests
|
|
system.physmem.pageHitRate 83.11 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 80733240 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 43918875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 313622400 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 150135120 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 89060552880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 35737868835 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 798596823000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 923983654350 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 667.983586 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 1308907007000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 45531980000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 9262769000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 82744200 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 44962500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 320439600 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 153705600 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 89060552880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 35470252125 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 802756182000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 927888838905 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 667.649647 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 1309307344000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 45531980000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 8896844750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu0.dtb.read_hits 4808616 # DTB read hits
|
|
system.cpu0.dtb.read_misses 6111 # DTB read misses
|
|
system.cpu0.dtb.read_acv 122 # DTB read access violations
|
|
system.cpu0.dtb.read_accesses 428608 # DTB read accesses
|
|
system.cpu0.dtb.write_hits 3411554 # DTB write hits
|
|
system.cpu0.dtb.write_misses 685 # DTB write misses
|
|
system.cpu0.dtb.write_acv 84 # DTB write access violations
|
|
system.cpu0.dtb.write_accesses 164458 # DTB write accesses
|
|
system.cpu0.dtb.data_hits 8220170 # DTB hits
|
|
system.cpu0.dtb.data_misses 6796 # DTB misses
|
|
system.cpu0.dtb.data_acv 206 # DTB access violations
|
|
system.cpu0.dtb.data_accesses 593066 # DTB accesses
|
|
system.cpu0.itb.fetch_hits 2729287 # ITB hits
|
|
system.cpu0.itb.fetch_misses 3056 # ITB misses
|
|
system.cpu0.itb.fetch_acv 101 # ITB acv
|
|
system.cpu0.itb.fetch_accesses 2732343 # ITB accesses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
|
system.cpu0.numCycles 928788202 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 6425 # number of quiesce instructions executed
|
|
system.cpu0.kern.inst.hwrei 211368 # number of hwrei instructions executed
|
|
system.cpu0.kern.ipl_count::0 74795 40.97% 40.97% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::31 105681 57.89% 100.00% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_good::0 73428 49.30% 49.30% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::31 73428 49.30% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::total 148937 # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_ticks::0 1818752965500 98.76% 98.76% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::21 39793500 0.00% 98.76% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::22 370197000 0.02% 98.78% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::31 22435471000 1.22% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::total 1841598427000 # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::31 0.694808 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::total 0.815838 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu0.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpctx 4175 2.17% 2.17% # number of callpals executed
|
|
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpipl 175300 91.20% 93.41% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
|
|
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
|
|
system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed
|
|
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::total 192212 # number of callpals executed
|
|
system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches
|
|
system.cpu0.kern.mode_good::kernel 1906
|
|
system.cpu0.kern.mode_good::user 1737
|
|
system.cpu0.kern.mode_good::idle 169
|
|
system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::total 0.390854 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_ticks::kernel 29766458500 1.62% 1.62% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::user 2570000000 0.14% 1.76% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::idle 1809261966500 98.24% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.swap_context 4176 # number of times the context was actually changed
|
|
system.cpu0.committedInsts 30028359 # Number of instructions committed
|
|
system.cpu0.committedOps 30028359 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 27949209 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 163605 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 796078 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 3573160 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 27949209 # number of integer instructions
|
|
system.cpu0.num_fp_insts 163605 # number of float instructions
|
|
system.cpu0.num_int_register_reads 38472094 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 20603467 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 84586 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 86140 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 8249833 # number of memory refs
|
|
system.cpu0.num_load_insts 4829697 # Number of load instructions
|
|
system.cpu0.num_store_insts 3420136 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 907169648.432742 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 21618553.567258 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.023276 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.976724 # Percentage of idle cycles
|
|
system.cpu0.Branches 4625246 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 1572413 5.24% 5.24% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 19517057 64.98% 70.22% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 31821 0.11% 70.32% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 70.32% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 12868 0.04% 70.36% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 70.36% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 70.36% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 70.36% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 1602 0.01% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.37% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 4960051 16.51% 86.88% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 3423231 11.40% 98.28% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 516318 1.72% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 30035361 # Class of executed instruction
|
|
system.cpu0.dcache.tags.replacements 1394566 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 13521910 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 1395078 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 9.692583 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 257.707457 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 77.564418 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.725941 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.503335 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.151493 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.345168 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 64423039 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 64423039 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 3984765 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 1069804 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu2.data 2772856 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 7827425 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3123452 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 820342 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu2.data 1358314 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 5302108 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113859 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19272 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 59831 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 192962 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122665 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21310 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55350 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 199325 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 7108217 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 1890146 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu2.data 4131170 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 13129533 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 7108217 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 1890146 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu2.data 4131170 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 13129533 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 711198 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 95313 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu2.data 558903 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 1365414 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 164044 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 43456 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu2.data 643142 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 850642 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9353 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2169 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7565 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 19087 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 26 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 875242 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 138769 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu2.data 1202045 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 2216056 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 875242 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 138769 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu2.data 1202045 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 2216056 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2254809000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8236813000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 10491622000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1752799000 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19370305557 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 21123104557 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28695000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 118437000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 147132000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 416000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 416000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 4007608000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu2.data 27607118557 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 31614726557 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 4007608000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu2.data 27607118557 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 31614726557 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 4695963 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1165117 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu2.data 3331759 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 9192839 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3287496 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 863798 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2001456 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 6152750 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123212 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21441 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 67396 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 212049 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122666 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21310 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55376 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 199352 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 7983459 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 2028915 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu2.data 5333215 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 15345589 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 7983459 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 2028915 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu2.data 5333215 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 15345589 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151449 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.081806 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.167750 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.148530 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049899 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050308 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.321337 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.138254 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075910 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101161 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.112247 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090012 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000470 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000135 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109632 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.068396 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.225388 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.144410 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109632 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.068396 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.225388 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.144410 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23656.888357 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14737.464283 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 7683.839480 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40335.028535 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30118.240695 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 24831.955813 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13229.598893 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15655.915400 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7708.492691 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15407.407407 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28879.706563 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 22966.792888 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 14266.212838 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28879.706563 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22966.792888 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 14266.212838 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 997927 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 2476 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 58775 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 19 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.978766 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 130.315789 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.writebacks::writebacks 836681 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 836681 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 289767 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 289767 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 548232 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 548232 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2018 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 2018 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu2.data 837999 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 837999 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu2.data 837999 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 837999 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 95313 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 269136 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 364449 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43456 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 94910 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 138366 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2169 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5547 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7716 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 26 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 138769 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu2.data 364046 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 502815 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 138769 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 364046 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 502815 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1131 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1724 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2855 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1430 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2033 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3463 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2561 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3757 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6318 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2159496000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4442371500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6601867500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1709343000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3045178740 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4754521740 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26526000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69860500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96386500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 390000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 390000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3868839000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7487550240 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 11356389240 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3868839000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7487550240 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 11356389240 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 248693500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 375591500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 624285000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 248693500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 375591500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 624285000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081806 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.080779 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039645 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050308 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047420 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022488 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101161 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.082305 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036388 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000470 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068396 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.068260 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.032766 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068396 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.068260 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.032766 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22656.888357 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16506.047129 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 18114.653902 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39335.028535 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32084.909282 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34361.922293 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12229.598893 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12594.285199 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12491.770347 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27879.706563 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20567.593766 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22585.621431 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27879.706563 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20567.593766 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22585.621431 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 219888.152078 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 217860.498840 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218663.747811 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97107.965638 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 99971.120575 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98810.541311 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.tags.replacements 969876 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.205246 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 39683030 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 970387 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 40.894025 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 10200405500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.920563 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.077972 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu2.inst 184.206711 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.511564 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.127105 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.359779 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.998448 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 41646260 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 41646260 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 29526010 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 7417850 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu2.inst 2739170 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 39683030 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 29526010 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 7417850 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu2.inst 2739170 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 39683030 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 29526010 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 7417850 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu2.inst 2739170 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 39683030 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 509351 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 126603 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu2.inst 356690 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 992644 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 509351 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 126603 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu2.inst 356690 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 992644 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 509351 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 126603 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu2.inst 356690 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 992644 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1812461000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4955400483 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 6767861483 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 1812461000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu2.inst 4955400483 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 6767861483 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 1812461000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu2.inst 4955400483 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 6767861483 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30035361 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 7544453 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3095860 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 40675674 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 30035361 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 7544453 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu2.inst 3095860 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 40675674 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 30035361 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 7544453 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu2.inst 3095860 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 40675674 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016958 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016781 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.115215 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.024404 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016958 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016781 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115215 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.024404 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016958 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016781 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.115215 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.024404 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14316.098355 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13892.737343 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 6818.014800 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14316.098355 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13892.737343 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 6818.014800 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14316.098355 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13892.737343 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 6818.014800 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 4716 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 235 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.068085 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.writebacks::writebacks 969876 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 969876 # number of writebacks
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22058 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 22058 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu2.inst 22058 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 22058 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu2.inst 22058 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 22058 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126603 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 334632 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 461235 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 126603 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu2.inst 334632 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 461235 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 126603 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu2.inst 334632 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 461235 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1685858000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4399066985 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 6084924985 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1685858000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4399066985 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 6084924985 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1685858000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4399066985 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 6084924985 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011339 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.011339 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.011339 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13192.678320 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13192.678320 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13192.678320 # average overall mshr miss latency
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.read_hits 1184324 # DTB read hits
|
|
system.cpu1.dtb.read_misses 1316 # DTB read misses
|
|
system.cpu1.dtb.read_acv 34 # DTB read access violations
|
|
system.cpu1.dtb.read_accesses 141546 # DTB read accesses
|
|
system.cpu1.dtb.write_hits 885341 # DTB write hits
|
|
system.cpu1.dtb.write_misses 169 # DTB write misses
|
|
system.cpu1.dtb.write_acv 22 # DTB write access violations
|
|
system.cpu1.dtb.write_accesses 57820 # DTB write accesses
|
|
system.cpu1.dtb.data_hits 2069665 # DTB hits
|
|
system.cpu1.dtb.data_misses 1485 # DTB misses
|
|
system.cpu1.dtb.data_acv 56 # DTB access violations
|
|
system.cpu1.dtb.data_accesses 199366 # DTB accesses
|
|
system.cpu1.itb.fetch_hits 852668 # ITB hits
|
|
system.cpu1.itb.fetch_misses 656 # ITB misses
|
|
system.cpu1.itb.fetch_acv 33 # ITB acv
|
|
system.cpu1.itb.fetch_accesses 853324 # ITB accesses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.numCycles 953375365 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
|
|
system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::user 0 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches
|
|
system.cpu1.kern.mode_good::kernel 0
|
|
system.cpu1.kern.mode_good::user 0
|
|
system.cpu1.kern.mode_good::idle 0
|
|
system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
|
|
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
|
|
system.cpu1.committedInsts 7542911 # Number of instructions committed
|
|
system.cpu1.committedOps 7542911 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 7009980 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 44709 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 205791 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 911955 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 7009980 # number of integer instructions
|
|
system.cpu1.num_fp_insts 44709 # number of float instructions
|
|
system.cpu1.num_int_register_reads 9753806 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 5113025 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 24116 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 24503 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 2076660 # number of memory refs
|
|
system.cpu1.num_load_insts 1189039 # Number of load instructions
|
|
system.cpu1.num_store_insts 887621 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 923368497.825425 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 30006867.174575 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.031474 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.968526 # Percentage of idle cycles
|
|
system.cpu1.Branches 1183564 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 404590 5.36% 5.36% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 4887103 64.78% 70.14% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 8470 0.11% 70.25% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 70.25% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 5131 0.07% 70.32% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 810 0.01% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 1217523 16.14% 86.47% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 888839 11.78% 98.25% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 131986 1.75% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 7544452 # Class of executed instruction
|
|
system.cpu2.branchPred.lookups 10195062 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 9245801 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 194837 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 7645666 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 5489178 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 71.794635 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 367323 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 14555 # Number of incorrect RAS predictions.
|
|
system.cpu2.branchPred.indirectLookups 1840410 # Number of indirect predictor lookups.
|
|
system.cpu2.branchPred.indirectHits 186758 # Number of indirect target hits.
|
|
system.cpu2.branchPred.indirectMisses 1653652 # Number of indirect misses.
|
|
system.cpu2.branchPredindirectMispredicted 86236 # Number of mispredicted indirect branches.
|
|
system.cpu2.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu2.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu2.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu2.dtb.read_hits 3794321 # DTB read hits
|
|
system.cpu2.dtb.read_misses 14980 # DTB read misses
|
|
system.cpu2.dtb.read_acv 154 # DTB read access violations
|
|
system.cpu2.dtb.read_accesses 231448 # DTB read accesses
|
|
system.cpu2.dtb.write_hits 2188085 # DTB write hits
|
|
system.cpu2.dtb.write_misses 3764 # DTB write misses
|
|
system.cpu2.dtb.write_acv 156 # DTB write access violations
|
|
system.cpu2.dtb.write_accesses 84759 # DTB write accesses
|
|
system.cpu2.dtb.data_hits 5982406 # DTB hits
|
|
system.cpu2.dtb.data_misses 18744 # DTB misses
|
|
system.cpu2.dtb.data_acv 310 # DTB access violations
|
|
system.cpu2.dtb.data_accesses 316207 # DTB accesses
|
|
system.cpu2.itb.fetch_hits 533759 # ITB hits
|
|
system.cpu2.itb.fetch_misses 2736 # ITB misses
|
|
system.cpu2.itb.fetch_acv 191 # ITB acv
|
|
system.cpu2.itb.fetch_accesses 536495 # ITB accesses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.read_acv 0 # DTB read access violations
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.write_acv 0 # DTB write access violations
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.data_hits 0 # DTB hits
|
|
system.cpu2.itb.data_misses 0 # DTB misses
|
|
system.cpu2.itb.data_acv 0 # DTB access violations
|
|
system.cpu2.itb.data_accesses 0 # DTB accesses
|
|
system.cpu2.numCycles 30327275 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 9354335 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 40099246 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 10195062 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 6043259 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 18967134 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 549482 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.TlbCycles 7 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu2.fetch.MiscStallCycles 11119 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.PendingDrainCycles 1939 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu2.fetch.PendingTrapStallCycles 54610 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.PendingQuiesceStallCycles 90342 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu2.fetch.IcacheWaitRetryStallCycles 596 # Number of stall cycles due to full MSHR
|
|
system.cpu2.fetch.CacheLines 3095865 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 133552 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 28754585 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.394534 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.444600 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 19879004 69.13% 69.13% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 339943 1.18% 70.32% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 516791 1.80% 72.11% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 4053539 14.10% 86.21% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 887171 3.09% 89.30% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 213563 0.74% 90.04% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 261735 0.91% 90.95% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 444517 1.55% 92.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 2158322 7.51% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 28754585 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.336168 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 1.322217 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 7569976 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 12996616 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 7107544 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 570612 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 263955 # Number of cycles decode is squashing
|
|
system.cpu2.decode.BranchResolved 225265 # Number of times decode resolved a branch
|
|
system.cpu2.decode.BranchMispred 11264 # Number of times decode detected a branch misprediction
|
|
system.cpu2.decode.DecodedInsts 36283979 # Number of instructions handled by decode
|
|
system.cpu2.decode.SquashedInsts 35882 # Number of squashed instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 263955 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 7872857 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 4931794 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 5918579 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 7355041 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 2166486 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 35279837 # Number of instructions processed by rename
|
|
system.cpu2.rename.ROBFullEvents 60983 # Number of times rename has blocked due to ROB full
|
|
system.cpu2.rename.IQFullEvents 402801 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LQFullEvents 76926 # Number of times rename has blocked due to LQ full
|
|
system.cpu2.rename.SQFullEvents 1084115 # Number of times rename has blocked due to SQ full
|
|
system.cpu2.rename.RenamedOperands 23748051 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 43586446 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 43526101 # Number of integer rename lookups
|
|
system.cpu2.rename.fp_rename_lookups 56436 # Number of floating rename lookups
|
|
system.cpu2.rename.CommittedMaps 20540056 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 3207995 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 542145 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 75307 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 3912291 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 3917277 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 2333144 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 542030 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 329847 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 32377023 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 701408 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 31676973 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 27053 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 3928896 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 1754776 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 507029 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 28754585 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 1.101632 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.635117 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 17376990 60.43% 60.43% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 2804831 9.75% 70.19% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 1408095 4.90% 75.08% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 4807285 16.72% 91.80% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 1079199 3.75% 95.55% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 630267 2.19% 97.75% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 421060 1.46% 99.21% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 175258 0.61% 99.82% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 51600 0.18% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 28754585 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 83759 19.66% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 19.66% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 210235 49.34% 69.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 132097 31.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 2450 0.01% 0.01% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 25141274 79.37% 79.38% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 20994 0.07% 79.44% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 79.44% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 20528 0.06% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 3966361 12.52% 92.03% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 2221145 7.01% 99.04% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 302997 0.96% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 31676973 # Type of FU issued
|
|
system.cpu2.iq.rate 1.044504 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 426091 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.013451 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 92299555 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 36885759 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 30885842 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 262120 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 128344 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 120451 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 31960571 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 140043 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 222851 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 843917 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 1448 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 6897 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 272853 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 4760 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 213103 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 263955 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 4308277 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 202891 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 34565468 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 70386 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 3917277 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 2333144 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 625709 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 13182 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 148814 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 6897 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 76158 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 205534 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 281692 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 31394525 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 3819678 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 282448 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 1487037 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 6017890 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 6848661 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 2198212 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 1.035191 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 31083503 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 31006293 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 17785830 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 21615859 # num instructions consuming a value
|
|
system.cpu2.iew.wb_rate 1.022390 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.822814 # average fanout of values written-back
|
|
system.cpu2.commit.commitSquashedInsts 4127890 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 194379 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 252373 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 28042775 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 1.083004 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 1.865926 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 18161783 64.76% 64.76% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 2276613 8.12% 72.88% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 1151869 4.11% 76.99% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 4491226 16.02% 93.01% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 562178 2.00% 95.01% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 204579 0.73% 95.74% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 167176 0.60% 96.34% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 177068 0.63% 96.97% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 850283 3.03% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 28042775 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 30370432 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 30370432 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 5133651 # Number of memory references committed
|
|
system.cpu2.commit.loads 3073360 # Number of loads committed
|
|
system.cpu2.commit.membars 68499 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 6541282 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 116010 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 28852886 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 241096 # Number of function calls committed.
|
|
system.cpu2.commit.op_class_0::No_OpClass 1223345 4.03% 4.03% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntAlu 23598567 77.70% 81.73% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntMult 20428 0.07% 81.80% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatAdd 20084 0.07% 81.86% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.86% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.86% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.86% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatDiv 1224 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemRead 3141859 10.35% 92.21% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemWrite 2061928 6.79% 99.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IprAccess 302997 1.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::total 30370432 # Class of committed instruction
|
|
system.cpu2.commit.bw_lim_events 850283 # number cycles where commit BW limit reached
|
|
system.cpu2.rob.rob_reads 61616016 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 69709723 # The number of ROB writes
|
|
system.cpu2.timesIdled 166720 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 1572690 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 1745481695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 29149535 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 29149535 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.cpi 1.040403 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 1.040403 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 0.961166 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 0.961166 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 41087551 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 22005301 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_reads 71153 # number of floating regfile reads
|
|
system.cpu2.fp_regfile_writes 74234 # number of floating regfile writes
|
|
system.cpu2.misc_regfile_reads 4377642 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 272877 # number of misc regfile writes
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.trans_dist::ReadReq 7317 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7317 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51362 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 51362 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 2373500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 135500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 56000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 5872500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 2528000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 89904673 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 9173000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.254561 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1693898501000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.254561 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.078410 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.078410 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375525 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
|
system.iocache.overall_misses::total 41725 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 9598462 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 9598462 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::tsunami.ide 2019796211 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 2019796211 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 2029394673 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 2029394673 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 2029394673 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 2029394673 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55482.439306 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 55482.439306 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 48608.880704 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 48608.880704 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 48637.379820 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 48637.379820 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 48637.379820 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 48637.379820 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
|
system.iocache.writebacks::total 41512 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17280 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 17280 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 17350 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 17350 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 17350 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 17350 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6098462 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 6098462 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1154802593 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 1154802593 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 1160901055 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 1160901055 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 1160901055 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 1160901055 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 0.415818 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 0.415818 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87120.885714 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 87120.885714 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66828.853762 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66828.853762 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66910.723631 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 66910.723631 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66910.723631 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 66910.723631 # average overall mshr miss latency
|
|
system.l2c.tags.replacements 337756 # number of replacements
|
|
system.l2c.tags.tagsinuse 65421.322565 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 4020988 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 402918 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 9.979668 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 54641.026539 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 2330.416055 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 2713.129703 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 574.927105 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 600.162086 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 2250.445944 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 2311.215132 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.833756 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.035559 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.041399 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.008773 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.009158 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.034339 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.035266 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.998250 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 987 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 5975 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 2686 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 55336 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 38533534 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 38533534 # Number of data accesses
|
|
system.l2c.WritebackDirty_hits::writebacks 836681 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 836681 # number of WritebackDirty hits
|
|
system.l2c.WritebackClean_hits::writebacks 969577 # number of WritebackClean hits
|
|
system.l2c.WritebackClean_hits::total 969577 # number of WritebackClean hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu2.data 10 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 14 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu2.data 23 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 90271 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 25531 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu2.data 71080 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 186882 # number of ReadExReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 501948 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 124306 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu2.inst 329876 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 956130 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 479737 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 81841 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu2.data 257555 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 819133 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 501948 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 570008 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 124306 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 107372 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 329876 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 328635 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1962145 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 501948 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 570008 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 124306 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 107372 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 329876 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 328635 # number of overall hits
|
|
system.l2c.overall_hits::total 1962145 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 9 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 8 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 17 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu2.data 3 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 73761 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 17924 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 23905 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 115590 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 7382 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 2297 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu2.inst 4668 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 14347 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 240814 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 15641 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu2.data 17035 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 273490 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 7382 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 314575 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 2297 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 33565 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 4668 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 40940 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 403427 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 7382 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 314575 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 2297 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 33565 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 4668 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 40940 # number of overall misses
|
|
system.l2c.overall_misses::total 403427 # number of overall misses
|
|
system.l2c.UpgradeReq_miss_latency::cpu2.data 329500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 329500 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu2.data 59000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 59000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1375697500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 2138065000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 3513762500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 189024500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 390327000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 579351500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 1178798000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu2.data 1287807000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 2466605000 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 189024500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 2554495500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 390327000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 3425872000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 6559719000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 189024500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 2554495500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 390327000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 3425872000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 6559719000 # number of overall miss cycles
|
|
system.l2c.WritebackDirty_accesses::writebacks 836681 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 836681 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::writebacks 969577 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::total 969577 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 12 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 31 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu2.data 26 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 27 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 164032 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 43455 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 94985 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 302472 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 509330 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 126603 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu2.inst 334544 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 970477 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 720551 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 97482 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu2.data 274590 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 1092623 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 509330 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 884583 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 126603 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 140937 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 334544 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 369575 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2365572 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 509330 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 884583 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 126603 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 140937 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 334544 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 369575 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2365572 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.750000 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.444444 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.548387 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.115385 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.148148 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.449674 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.412473 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 0.251671 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.382151 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014494 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.018143 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.013953 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.014783 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.334208 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.160450 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.062038 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.250306 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.014494 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.355620 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.018143 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.238156 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.013953 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.110776 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.170541 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.014494 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.355620 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.018143 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.238156 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.013953 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.110776 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.170541 # miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 41187.500000 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 19382.352941 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 19666.666667 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 14750 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76751.701629 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 89440.075298 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 30398.499005 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82291.902481 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83617.609254 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 40381.368927 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 75365.897321 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 75597.710596 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 9018.995210 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 82291.902481 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 76105.928795 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 83617.609254 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 83680.312653 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 16259.990035 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 82291.902481 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 76105.928795 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 83617.609254 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 83680.312653 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 16259.990035 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.writebacks::writebacks 75501 # number of writebacks
|
|
system.l2c.writebacks::total 75501 # number of writebacks
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 8 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 3 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 17924 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 23905 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 41829 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2297 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 4668 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 6965 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 15641 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 17035 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 32676 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 2297 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 33565 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 4668 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 40940 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 81470 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 2297 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 33565 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 4668 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 40940 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 81470 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1131 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1724 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 2855 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 1430 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 2033 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 3463 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2561 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3757 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 6318 # number of overall MSHR uncacheable misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 307500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 307500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 58500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 58500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1196457500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1899015000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 3095472500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 166054500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 343647000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 509701500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1022388000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1119548000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 2141936000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 166054500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 2218845500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 343647000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 3018563000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 5747110000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 166054500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 2218845500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 343647000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 3018563000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 5747110000 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 234549500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 354037500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 588587000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 234549500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 354037500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 588587000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.444444 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.258065 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.115385 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.111111 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.412473 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.251671 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.138290 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018143 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007177 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.160450 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.062038 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.029906 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018143 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.238156 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.110776 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.034440 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018143 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.238156 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.110776 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.034440 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 38437.500000 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 38437.500000 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 19500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66751.701629 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79440.075298 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 74003.024218 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72291.902481 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73617.609254 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73180.402010 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 65365.897321 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 65720.457881 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 65550.740605 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72291.902481 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66105.928795 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73617.609254 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73731.387396 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 70542.653738 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72291.902481 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66105.928795 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73617.609254 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73731.387396 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 70542.653738 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 207382.404951 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 205358.178654 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 206160.070053 # average ReadReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91585.122999 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 94234.096353 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 93160.335549 # average overall mshr uncacheable latency
|
|
system.membus.snoop_filter.tot_requests 823896 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 379632 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 408 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.trans_dist::ReadReq 7144 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 295138 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9810 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9810 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 117013 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 261704 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 179 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 113 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 115428 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 115428 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 288010 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 16 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 24272 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143724 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 1177664 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 107800 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 107800 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1285464 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633664 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 30679232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 33343552 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 157 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 742227 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0.001296 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0.035978 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 741265 99.87% 99.87% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 962 0.13% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 742227 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 10965500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 390337877 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 19000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 436169750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 370538 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.snoop_filter.tot_requests 4730181 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 2364664 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 1672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 1038 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 1038 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2070392 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 866358 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackClean 969876 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 609667 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 31 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 58 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 302472 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 302472 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 970586 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 1092680 # Transaction distribution
|
|
system.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 41 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2910960 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4218835 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7129795 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124183936 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142881728 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 267065664 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 338688 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 4114055 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.000998 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.031568 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 4109951 99.90% 99.90% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 4104 0.10% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 4114055 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 1826321500 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 100962 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 692196311 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 770446828 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
|
|
system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches
|
|
system.cpu2.kern.mode_switch::user 0 # number of protection mode switches
|
|
system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches
|
|
system.cpu2.kern.mode_good::kernel 0
|
|
system.cpu2.kern.mode_good::user 0
|
|
system.cpu2.kern.mode_good::idle 0
|
|
system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
|
|
system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches
|
|
system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
|
system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches
|
|
system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
|
|
system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode
|
|
system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
|
|
system.cpu2.kern.swap_context 0 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
|