misc: Clean up and complete the gem5<->SystemC-TLM bridge [2/10]
The current TLM bridge only provides a Slave Port that allows the gem5 world to send request to the SystemC world. This patch series refractors and cleans up the existing code, and adds a Master Port that allows the SystemC world to send requests to the gem5 world. This patch: * Add the Master Port. Add an example application that isslustrates its * use. Testing Done: A simple example application consisting of a TLM traffic generator and a gem5 memory is part of the patch. Reviewed at http://reviews.gem5.org/r/3528/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Christian Menard
parent
b25ea094d4
commit
55f5c4dd8a
8 changed files with 982 additions and 0 deletions
77
util/tlm/examples/master_port/SConstruct
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77
util/tlm/examples/master_port/SConstruct
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#!python
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# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
|
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# modification, are permitted provided that the following conditions are
|
||||
# met:
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||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
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# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
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# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
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# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Christian Menard
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import os
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gem5_arch = 'ARM'
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gem5_variant = 'opt'
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#gem5_variant = 'debug'
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gem5_root = '#../../../..'
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target = 'gem5.' + gem5_variant + '.sc'
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env = Environment()
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# Import PKG_CONFIG_PATH from the external environment
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if os.environ.has_key('PKG_CONFIG_PATH'):
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env['ENV']['PKG_CONFIG_PATH'] = os.environ['PKG_CONFIG_PATH']
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# search for SystemC
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env.ParseConfig('pkg-config --cflags --libs systemc')
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# add include dirs
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env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch,
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gem5_root + '/util/systemc',
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gem5_root + '/util/tlm'])
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env.Append(LIBS=['gem5_' + gem5_variant])
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env.Append(LIBPATH=[gem5_root + '/build/' + gem5_arch])
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env.Append(CXXFLAGS=['-std=c++11',
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'-DSC_INCLUDE_DYNAMIC_PROCESSES',
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'-DTRACING_ON'])
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if gem5_variant == 'debug':
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env.Append(CXXFLAGS=['-g', '-DDEBUG'])
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src_systemc = [gem5_root + '/util/systemc/sc_gem5_control.cc',
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gem5_root + '/util/systemc/sc_logger.cc',
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gem5_root + '/util/systemc/sc_module.cc',
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gem5_root + '/util/systemc/stats.cc']
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src_tlm = Glob(gem5_root + '/util/tlm/*.cc')
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src_main = Glob('*.cc')
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main = env.Program(target, src_systemc + src_tlm + src_main)
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98
util/tlm/examples/master_port/main.cc
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98
util/tlm/examples/master_port/main.cc
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@ -0,0 +1,98 @@
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/*
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* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Christian Menard
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*/
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#include <systemc>
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#include <tlm>
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#include "sc_master_port.hh"
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#include "sim_control.hh"
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#include "stats.hh"
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#include "traffic_generator.hh"
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// Defining global string variable decalred in stats.hh
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std::string filename;
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void
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reportHandler(const sc_core::sc_report& report,
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const sc_core::sc_actions& actions)
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{
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uint64_t systemc_time = report.get_time().value();
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uint64_t gem5_time = curTick();
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std::cerr << report.get_time();
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if (gem5_time < systemc_time) {
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std::cerr << " (<) ";
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} else if (gem5_time > systemc_time) {
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std::cerr << " (!) ";
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} else {
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std::cerr << " (=) ";
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}
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std::cerr << ": " << report.get_msg_type() << ' ' << report.get_msg()
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<< '\n';
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}
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int
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sc_main(int argc, char** argv)
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{
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sc_core::sc_report_handler::set_handler(reportHandler);
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SimControl simControl("gem5", argc, argv);
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TrafficGenerator trafficGenerator("traffic_generator");
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filename = "m5out/stats-systemc.txt";
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tlm::tlm_target_socket<>* mem_port =
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dynamic_cast<tlm::tlm_target_socket<>*>(
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sc_core::sc_find_object("gem5.memory"));
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if (mem_port) {
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SC_REPORT_INFO("sc_main", "Port Found");
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trafficGenerator.socket.bind(*mem_port);
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} else {
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SC_REPORT_FATAL("sc_main", "Port Not Found");
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std::exit(EXIT_FAILURE);
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}
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std::cout << "Starting sc_main" << std::endl;
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sc_core::sc_start(); // Run to end of simulation
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SC_REPORT_INFO("sc_main", "End of Simulation");
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CxxConfig::statsDump();
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return EXIT_SUCCESS;
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}
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75
util/tlm/examples/master_port/tlm.py
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75
util/tlm/examples/master_port/tlm.py
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@ -0,0 +1,75 @@
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#
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# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
|
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright
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||||
# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
|
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# contributors may be used to endorse or promote products derived from
|
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# this software without specific prior written permission.
|
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#
|
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
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# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
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# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Christian Menard
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#
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import m5
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from m5.objects import *
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import os
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# Base System Architecture:
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# +-----+ ^
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# | TLM | | TLM World
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# +--+--+ | (see main.cc)
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# | v
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# +----------v-----------+ External Port (see sc_master_port.*)
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# | Membus | ^
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# +----------+-----------+ |
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# | | gem5 World
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# +---v----+ |
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# | Memory | |
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# +--------+ v
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#
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# Create a system with a Crossbar and a simple Memory:
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system = System()
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system.membus = IOXBar(width = 16)
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system.physmem = SimpleMemory(range = AddrRange('512MB'))
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system.clk_domain = SrcClockDomain(clock = '1.5GHz',
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voltage_domain = VoltageDomain(voltage = '1V'))
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# Create a external TLM port:
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system.tlm = ExternalMaster()
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system.tlm.port_type = "tlm_master"
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system.tlm.port_data = "memory"
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# Route the connections:
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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system.tlm.port = system.membus.slave
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system.mem_mode = 'timing'
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# Start the simulation:
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root = Root(full_system = False, system = system)
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m5.instantiate()
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m5.simulate()
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154
util/tlm/examples/master_port/traffic_generator.cc
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154
util/tlm/examples/master_port/traffic_generator.cc
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@ -0,0 +1,154 @@
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/*
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* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
|
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
|
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Christian Menard
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*/
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#include "base/random.hh"
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#include "traffic_generator.hh"
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TrafficGenerator::TrafficGenerator(sc_core::sc_module_name name)
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: sc_core::sc_module(name),
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requestInProgress(0),
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peq(this, &TrafficGenerator::peq_cb)
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{
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socket.register_nb_transport_bw(this, &TrafficGenerator::nb_transport_bw);
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SC_THREAD(process);
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}
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void
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TrafficGenerator::process()
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{
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auto rnd = Random(time(NULL));
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unsigned const memSize = (1 << 10); // 512 MB
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while (true) {
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wait(sc_core::sc_time((double)rnd.random(1,100), sc_core::SC_NS));
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auto trans = mm.allocate();
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trans->acquire();
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std::string cmdStr;
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if (rnd.random(0,1)) // Generate a write request?
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{
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cmdStr = "write";
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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dataBuffer = rnd.random(0,0xffff);
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} else {
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cmdStr = "read";
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trans->set_command(tlm::TLM_READ_COMMAND);
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}
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trans->set_data_ptr(reinterpret_cast<unsigned char*>(&dataBuffer));
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trans->set_address(rnd.random(0, (int)(memSize-1)));
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trans->set_data_length(4);
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trans->set_streaming_width(4);
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trans->set_byte_enable_ptr(0);
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trans->set_dmi_allowed(0);
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trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
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// honor the BEGIN_REQ/END_REQ exclusion rule
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if (requestInProgress)
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sc_core::wait(endRequestEvent);
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std::stringstream ss;
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ss << "Send " << cmdStr << " request @0x" << std::hex
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<< trans->get_address();
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SC_REPORT_INFO("Traffic Generator", ss.str().c_str());
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// send the request
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requestInProgress = trans;
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tlm::tlm_phase phase = tlm::BEGIN_REQ;
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auto delay = sc_core::SC_ZERO_TIME;
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auto status = socket->nb_transport_fw(*trans, phase, delay);
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// Check status
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if (status == tlm::TLM_UPDATED) {
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peq.notify(*trans, phase, delay);
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} else if (status == tlm::TLM_COMPLETED) {
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requestInProgress = 0;
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checkTransaction(*trans);
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SC_REPORT_INFO("Traffic Generator", "request completed");
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trans->release();
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}
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}
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}
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void
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TrafficGenerator::peq_cb(tlm::tlm_generic_payload& trans,
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const tlm::tlm_phase& phase)
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{
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if (phase == tlm::END_REQ ||
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(&trans == requestInProgress && phase == tlm::BEGIN_RESP)) {
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// The end of the BEGIN_REQ phase
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requestInProgress = 0;
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endRequestEvent.notify();
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} else if (phase == tlm::BEGIN_REQ || phase == tlm::END_RESP)
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SC_REPORT_FATAL("TLM-2",
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"Illegal transaction phase received by initiator");
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if (phase == tlm::BEGIN_RESP) {
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checkTransaction(trans);
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SC_REPORT_INFO("Traffic Generator", "received response");
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// Send end response
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tlm::tlm_phase fw_phase = tlm::END_RESP;
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// stress the retry mechanism by deferring the response
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auto delay = sc_core::sc_time(5.0, sc_core::SC_NS);
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socket->nb_transport_fw(trans, fw_phase, delay);
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trans.release();
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}
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}
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void
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TrafficGenerator::checkTransaction(tlm::tlm_generic_payload& trans)
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{
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if (trans.is_response_error()) {
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std::stringstream ss;
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ss << "Transaction returned with error, response status = %s"
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<< trans.get_response_string();
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SC_REPORT_ERROR("TLM-2", ss.str().c_str());
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}
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}
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tlm::tlm_sync_enum
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TrafficGenerator::nb_transport_bw(tlm::tlm_generic_payload& trans,
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tlm::tlm_phase& phase,
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sc_core::sc_time& delay)
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{
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trans.acquire();
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peq.notify(trans, phase, delay);
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return tlm::TLM_ACCEPTED;
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}
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77
util/tlm/examples/master_port/traffic_generator.hh
Normal file
77
util/tlm/examples/master_port/traffic_generator.hh
Normal file
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/*
|
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* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Christian Menard
|
||||
*/
|
||||
|
||||
#ifndef __TRAFFIC_GENERATOR_HH__
|
||||
#define __TRAFFIC_GENERATOR_HH__
|
||||
|
||||
#include <tlm_utils/peq_with_cb_and_phase.h>
|
||||
#include <tlm_utils/simple_initiator_socket.h>
|
||||
|
||||
#include <systemc>
|
||||
#include <tlm>
|
||||
|
||||
#include "sc_mm.hh"
|
||||
|
||||
class TrafficGenerator : public sc_core::sc_module
|
||||
{
|
||||
private:
|
||||
Gem5SystemC::MemoryManager mm;
|
||||
|
||||
tlm::tlm_generic_payload* requestInProgress;
|
||||
|
||||
uint32_t dataBuffer;
|
||||
|
||||
sc_core::sc_event endRequestEvent;
|
||||
|
||||
tlm_utils::peq_with_cb_and_phase<TrafficGenerator> peq;
|
||||
|
||||
public:
|
||||
tlm_utils::simple_initiator_socket<TrafficGenerator> socket;
|
||||
|
||||
SC_HAS_PROCESS(TrafficGenerator);
|
||||
|
||||
TrafficGenerator(sc_core::sc_module_name name);
|
||||
|
||||
void process();
|
||||
|
||||
void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
|
||||
|
||||
void checkTransaction(tlm::tlm_generic_payload& trans);
|
||||
|
||||
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans,
|
||||
tlm::tlm_phase& phase,
|
||||
sc_core::sc_time& delay);
|
||||
};
|
||||
|
||||
#endif
|
||||
362
util/tlm/sc_master_port.cc
Normal file
362
util/tlm/sc_master_port.cc
Normal file
|
|
@ -0,0 +1,362 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Christian Menard
|
||||
*/
|
||||
|
||||
#include <sstream>
|
||||
|
||||
#include "params/ExternalMaster.hh"
|
||||
#include "sc_master_port.hh"
|
||||
#include "sim/system.hh"
|
||||
|
||||
namespace Gem5SystemC
|
||||
{
|
||||
|
||||
PacketPtr
|
||||
SCMasterPort::generatePacket(tlm::tlm_generic_payload& trans)
|
||||
{
|
||||
Request::Flags flags;
|
||||
auto req = new Request(trans.get_address(), trans.get_data_length(), flags,
|
||||
owner.masterId);
|
||||
|
||||
MemCmd cmd;
|
||||
|
||||
switch (trans.get_command()) {
|
||||
case tlm::TLM_READ_COMMAND:
|
||||
cmd = MemCmd::ReadReq;
|
||||
break;
|
||||
case tlm::TLM_WRITE_COMMAND:
|
||||
cmd = MemCmd::WriteReq;
|
||||
break;
|
||||
default:
|
||||
SC_REPORT_FATAL("SCMasterPort",
|
||||
"received transaction with unsupported command");
|
||||
}
|
||||
|
||||
/*
|
||||
* Allocate a new Packet. The packet will be deleted when it returns from
|
||||
* the gem5 world as a response.
|
||||
*/
|
||||
auto pkt = new Packet(req, cmd);
|
||||
pkt->dataStatic(trans.get_data_ptr());
|
||||
|
||||
return pkt;
|
||||
}
|
||||
|
||||
void
|
||||
SCMasterPort::destroyPacket(PacketPtr pkt)
|
||||
{
|
||||
delete pkt;
|
||||
}
|
||||
|
||||
SCMasterPort::SCMasterPort(const std::string& name_,
|
||||
const std::string& systemc_name,
|
||||
ExternalMaster& owner_,
|
||||
Module& module)
|
||||
: ExternalMaster::Port(name_, owner_),
|
||||
tSocket(systemc_name.c_str()),
|
||||
peq(this, &SCMasterPort::peq_cb),
|
||||
waitForRetry(false),
|
||||
pendingRequest(nullptr),
|
||||
needToSendRetry(false),
|
||||
responseInProgress(false),
|
||||
module(module)
|
||||
{
|
||||
auto system =
|
||||
dynamic_cast<const ExternalMasterParams*>(owner_.params())->system;
|
||||
|
||||
/*
|
||||
* Register the TLM non-blocking interface when using gem5 Timing mode and
|
||||
* the TLM blocking interface when using the gem5 Atomic mode.
|
||||
* Then the magic (TM) in simple_target_socket automatically transforms
|
||||
* non-blocking in blocking transactions and vice versa.
|
||||
*
|
||||
* NOTE: The mode may change during execution.
|
||||
*/
|
||||
if (system->isTimingMode()) {
|
||||
SC_REPORT_INFO("SCMasterPort", "register non-blocking interface");
|
||||
tSocket.register_nb_transport_fw(this,
|
||||
&SCMasterPort::nb_transport_fw);
|
||||
} else if (system->isAtomicMode()) {
|
||||
SC_REPORT_INFO("SCMasterPort", "register blocking interface");
|
||||
tSocket.register_b_transport(this, &SCMasterPort::b_transport);
|
||||
} else {
|
||||
panic("gem5 operates neither in Timing nor in Atomic mode");
|
||||
}
|
||||
|
||||
tSocket.register_transport_dbg(this, &SCMasterPort::transport_dbg);
|
||||
}
|
||||
|
||||
void
|
||||
SCMasterPort::checkTransaction(tlm::tlm_generic_payload& trans)
|
||||
{
|
||||
if (trans.is_response_error()) {
|
||||
std::stringstream ss;
|
||||
ss << "Transaction returned with error, response status = "
|
||||
<< trans.get_response_string();
|
||||
SC_REPORT_ERROR("TLM-2", ss.str().c_str());
|
||||
}
|
||||
}
|
||||
|
||||
tlm::tlm_sync_enum
|
||||
SCMasterPort::nb_transport_fw(tlm::tlm_generic_payload& trans,
|
||||
tlm::tlm_phase& phase, sc_core::sc_time& delay)
|
||||
{
|
||||
uint64_t adr = trans.get_address();
|
||||
unsigned len = trans.get_data_length();
|
||||
unsigned char* byteEnable = trans.get_byte_enable_ptr();
|
||||
unsigned width = trans.get_streaming_width();
|
||||
|
||||
// check the transaction attributes for unsupported features ...
|
||||
if (byteEnable != 0) {
|
||||
trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE);
|
||||
return tlm::TLM_COMPLETED;
|
||||
}
|
||||
if (width < len) { // is this a burst request?
|
||||
trans.set_response_status(tlm::TLM_BURST_ERROR_RESPONSE);
|
||||
return tlm::TLM_COMPLETED;
|
||||
}
|
||||
|
||||
// ... and queue the valid transaction
|
||||
peq.notify(trans, phase, delay);
|
||||
return tlm::TLM_ACCEPTED;
|
||||
}
|
||||
|
||||
void
|
||||
SCMasterPort::peq_cb(tlm::tlm_generic_payload& trans,
|
||||
const tlm::tlm_phase& phase)
|
||||
{
|
||||
// catch up with SystemC time
|
||||
module.catchup();
|
||||
assert(curTick() == sc_core::sc_time_stamp().value());
|
||||
|
||||
switch (phase) {
|
||||
case tlm::BEGIN_REQ:
|
||||
handleBeginReq(trans);
|
||||
break;
|
||||
case tlm::END_RESP:
|
||||
handleEndResp(trans);
|
||||
break;
|
||||
default:
|
||||
panic("unimplemented phase in callback");
|
||||
}
|
||||
|
||||
// the functions called above may have scheduled gem5 events
|
||||
// -> notify the event loop handler
|
||||
module.notify();
|
||||
}
|
||||
|
||||
void
|
||||
SCMasterPort::handleBeginReq(tlm::tlm_generic_payload& trans)
|
||||
{
|
||||
sc_assert(!waitForRetry);
|
||||
sc_assert(pendingRequest == nullptr);
|
||||
|
||||
trans.acquire();
|
||||
auto pkt = generatePacket(trans);
|
||||
|
||||
auto tlmSenderState = new TlmSenderState(trans);
|
||||
pkt->pushSenderState(tlmSenderState);
|
||||
|
||||
if (sendTimingReq(pkt)) { // port is free -> send END_REQ immediately
|
||||
sendEndReq(trans);
|
||||
} else { // port is blocked -> wait for retry before sending END_REQ
|
||||
waitForRetry = true;
|
||||
pendingRequest = &trans;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
SCMasterPort::handleEndResp(tlm::tlm_generic_payload& trans)
|
||||
{
|
||||
sc_assert(responseInProgress);
|
||||
|
||||
responseInProgress = false;
|
||||
|
||||
checkTransaction(trans);
|
||||
|
||||
if (needToSendRetry) {
|
||||
sendRetryResp();
|
||||
needToSendRetry = false;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
SCMasterPort::sendEndReq(tlm::tlm_generic_payload& trans)
|
||||
{
|
||||
tlm::tlm_phase phase = tlm::END_REQ;
|
||||
auto delay = sc_core::SC_ZERO_TIME;
|
||||
|
||||
auto status = tSocket->nb_transport_bw(trans, phase, delay);
|
||||
panic_if(status != tlm::TLM_ACCEPTED,
|
||||
"Unexpected status after sending END_REQ");
|
||||
}
|
||||
|
||||
void
|
||||
SCMasterPort::b_transport(tlm::tlm_generic_payload& trans,
|
||||
sc_core::sc_time& t)
|
||||
{
|
||||
auto pkt = generatePacket(trans);
|
||||
|
||||
// send an atomic request to gem5
|
||||
Tick ticks = sendAtomic(pkt);
|
||||
panic_if(!pkt->isResponse(), "Packet sending failed!\n");
|
||||
|
||||
// one tick is a pico second
|
||||
auto delay =
|
||||
sc_core::sc_time((double)(ticks / SimClock::Int::ps), sc_core::SC_PS);
|
||||
|
||||
// update time
|
||||
t += delay;
|
||||
|
||||
destroyPacket(pkt);
|
||||
|
||||
trans.set_response_status(tlm::TLM_OK_RESPONSE);
|
||||
}
|
||||
|
||||
unsigned int
|
||||
SCMasterPort::transport_dbg(tlm::tlm_generic_payload& trans)
|
||||
{
|
||||
auto pkt = generatePacket(trans);
|
||||
|
||||
sendFunctional(pkt);
|
||||
|
||||
destroyPacket(pkt);
|
||||
|
||||
return trans.get_data_length();
|
||||
}
|
||||
|
||||
bool
|
||||
SCMasterPort::get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
|
||||
tlm::tlm_dmi& dmi_data)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
bool
|
||||
SCMasterPort::recvTimingResp(PacketPtr pkt)
|
||||
{
|
||||
// exclusion rule
|
||||
// We need to Wait for END_RESP before sending next BEGIN_RESP
|
||||
if (responseInProgress) {
|
||||
sc_assert(!needToSendRetry);
|
||||
needToSendRetry = true;
|
||||
return false;
|
||||
}
|
||||
|
||||
sc_assert(pkt->isResponse());
|
||||
|
||||
// pay for annotaded transport delays
|
||||
auto delay =
|
||||
sc_core::sc_time::from_value(pkt->payloadDelay + pkt->headerDelay);
|
||||
|
||||
auto tlmSenderState = dynamic_cast<TlmSenderState*>(pkt->popSenderState());
|
||||
auto& trans = tlmSenderState->trans;
|
||||
|
||||
// clean up
|
||||
delete tlmSenderState;
|
||||
destroyPacket(pkt);
|
||||
|
||||
sendBeginResp(trans, delay);
|
||||
trans.release();
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void
|
||||
SCMasterPort::sendBeginResp(tlm::tlm_generic_payload& trans,
|
||||
sc_core::sc_time& delay)
|
||||
{
|
||||
tlm::tlm_phase phase = tlm::BEGIN_RESP;
|
||||
|
||||
trans.set_response_status(tlm::TLM_OK_RESPONSE);
|
||||
|
||||
auto status = tSocket->nb_transport_bw(trans, phase, delay);
|
||||
|
||||
if (status == tlm::TLM_COMPLETED ||
|
||||
status == tlm::TLM_UPDATED && phase == tlm::END_RESP) {
|
||||
// transaction completed -> no need to wait for tlm::END_RESP
|
||||
responseInProgress = false;
|
||||
} else if (status == tlm::TLM_ACCEPTED) {
|
||||
// we need to wait for tlm::END_RESP
|
||||
responseInProgress = true;
|
||||
} else {
|
||||
panic("Unexpected status after sending BEGIN_RESP");
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
SCMasterPort::recvReqRetry()
|
||||
{
|
||||
sc_assert(waitForRetry);
|
||||
sc_assert(pendingRequest != nullptr);
|
||||
|
||||
auto& trans = *pendingRequest;
|
||||
|
||||
waitForRetry = false;
|
||||
pendingRequest = nullptr;
|
||||
|
||||
// retry
|
||||
handleBeginReq(trans);
|
||||
}
|
||||
|
||||
void
|
||||
SCMasterPort::recvRangeChange()
|
||||
{
|
||||
SC_REPORT_WARNING("SCMasterPort",
|
||||
"received address range change but ignored it");
|
||||
}
|
||||
|
||||
class SCMasterPortHandler : public ExternalMaster::Handler
|
||||
{
|
||||
Module& module;
|
||||
|
||||
public:
|
||||
SCMasterPortHandler(Module& module) : module(module) {}
|
||||
|
||||
ExternalMaster::Port* getExternalPort(const std::string& name,
|
||||
ExternalMaster& owner,
|
||||
const std::string& port_data)
|
||||
{
|
||||
// This will make a new initiatiator port
|
||||
return new SCMasterPort(name, port_data, owner, module);
|
||||
}
|
||||
};
|
||||
|
||||
void
|
||||
SCMasterPort::registerPortHandler(Module& module)
|
||||
{
|
||||
ExternalMaster::registerHandler("tlm_master",
|
||||
new SCMasterPortHandler(module));
|
||||
}
|
||||
|
||||
} // namespace Gem5SystemC
|
||||
137
util/tlm/sc_master_port.hh
Normal file
137
util/tlm/sc_master_port.hh
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Christian Menard
|
||||
*/
|
||||
|
||||
#ifndef __SC_MASTER_PORT_HH__
|
||||
#define __SC_MASTER_PORT_HH__
|
||||
|
||||
#include <tlm_utils/peq_with_cb_and_phase.h>
|
||||
#include <tlm_utils/simple_target_socket.h>
|
||||
|
||||
#include <tlm>
|
||||
|
||||
#include <mem/external_master.hh>
|
||||
#include <sc_module.hh>
|
||||
#include <sc_peq.hh>
|
||||
|
||||
namespace Gem5SystemC
|
||||
{
|
||||
|
||||
/**
|
||||
* This is a gem5 master port that translates TLM transactions to gem5 packets.
|
||||
*
|
||||
* Upon receiving a TLM transaction (b_transport, nb_transport_fw,
|
||||
* dbg_transport) the port generates a gem5 packet and initializes the packet
|
||||
* with information from the transaction payload. The original TLM payload is
|
||||
* added as a sender state to the gem5 packet. This way the payload can be
|
||||
* restored when the response packet arrives at the port.
|
||||
*
|
||||
* If gem5 operates in atomic mode, the master port registers the TLM blocking
|
||||
* interface and automatically translates non-blocking requests to blocking.
|
||||
* If gem5 operates in timing mode, the transactor registers the non-blocking
|
||||
* interface. Then, the transactor automatically translated blocking requests.
|
||||
* It is assumed that the mode (atomic/timing) does not change during
|
||||
* execution.
|
||||
*/
|
||||
class SCMasterPort : public ExternalMaster::Port
|
||||
{
|
||||
private:
|
||||
struct TlmSenderState : public Packet::SenderState
|
||||
{
|
||||
tlm::tlm_generic_payload& trans;
|
||||
TlmSenderState(tlm::tlm_generic_payload& trans)
|
||||
: trans(trans)
|
||||
{
|
||||
}
|
||||
};
|
||||
|
||||
tlm_utils::peq_with_cb_and_phase<SCMasterPort> peq;
|
||||
|
||||
bool waitForRetry;
|
||||
tlm::tlm_generic_payload* pendingRequest;
|
||||
|
||||
bool needToSendRetry;
|
||||
|
||||
bool responseInProgress;
|
||||
|
||||
// Keep a reference to the gem5 SystemC module
|
||||
Module& module;
|
||||
|
||||
public:
|
||||
tlm_utils::simple_target_socket<SCMasterPort> tSocket;
|
||||
|
||||
protected:
|
||||
// payload event call back
|
||||
void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
|
||||
|
||||
// The TLM target interface
|
||||
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
|
||||
tlm::tlm_phase& phase,
|
||||
sc_core::sc_time& t);
|
||||
void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& t);
|
||||
unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
|
||||
bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
|
||||
tlm::tlm_dmi& dmi_data);
|
||||
|
||||
// Gem5 SCMasterPort interface
|
||||
bool recvTimingResp(PacketPtr pkt);
|
||||
void recvReqRetry();
|
||||
void recvRangeChange();
|
||||
|
||||
public:
|
||||
SCMasterPort(const std::string& name_,
|
||||
const std::string& systemc_name,
|
||||
ExternalMaster& owner_,
|
||||
Module& module);
|
||||
|
||||
static void registerPortHandler(Module& module);
|
||||
|
||||
friend PayloadEvent<SCMasterPort>;
|
||||
|
||||
private:
|
||||
void sendEndReq(tlm::tlm_generic_payload& trans);
|
||||
void sendBeginResp(tlm::tlm_generic_payload& trans,
|
||||
sc_core::sc_time& delay);
|
||||
|
||||
void handleBeginReq(tlm::tlm_generic_payload& trans);
|
||||
void handleEndResp(tlm::tlm_generic_payload& trans);
|
||||
|
||||
PacketPtr generatePacket(tlm::tlm_generic_payload& trans);
|
||||
void destroyPacket(PacketPtr pkt);
|
||||
|
||||
void checkTransaction(tlm::tlm_generic_payload& trans);
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -46,6 +46,7 @@
|
|||
#include <systemc>
|
||||
#include <tlm>
|
||||
|
||||
#include "sc_master_port.hh"
|
||||
#include "sc_slave_port.hh"
|
||||
#include "sim/cxx_config_ini.hh"
|
||||
#include "sim/init_signals.hh"
|
||||
|
|
@ -90,6 +91,7 @@ SimControl::SimControl(sc_core::sc_module_name name, int argc_, char** argv_)
|
|||
|
||||
cxxConfigInit();
|
||||
Gem5SystemC::SCSlavePort::registerPortHandler();
|
||||
Gem5SystemC::SCMasterPort::registerPortHandler(*this);
|
||||
|
||||
Trace::setDebugLogger(&logger);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue