55f5c4dd8a
The current TLM bridge only provides a Slave Port that allows the gem5 world to send request to the SystemC world. This patch series refractors and cleans up the existing code, and adds a Master Port that allows the SystemC world to send requests to the gem5 world. This patch: * Add the Master Port. Add an example application that isslustrates its * use. Testing Done: A simple example application consisting of a TLM traffic generator and a gem5 memory is part of the patch. Reviewed at http://reviews.gem5.org/r/3528/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
75 lines
2.7 KiB
Python
75 lines
2.7 KiB
Python
#
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# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Christian Menard
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#
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import m5
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from m5.objects import *
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import os
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# Base System Architecture:
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# +-----+ ^
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# | TLM | | TLM World
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# +--+--+ | (see main.cc)
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# | v
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# +----------v-----------+ External Port (see sc_master_port.*)
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# | Membus | ^
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# +----------+-----------+ |
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# | | gem5 World
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# +---v----+ |
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# | Memory | |
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# +--------+ v
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#
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# Create a system with a Crossbar and a simple Memory:
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system = System()
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system.membus = IOXBar(width = 16)
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system.physmem = SimpleMemory(range = AddrRange('512MB'))
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system.clk_domain = SrcClockDomain(clock = '1.5GHz',
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voltage_domain = VoltageDomain(voltage = '1V'))
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# Create a external TLM port:
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system.tlm = ExternalMaster()
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system.tlm.port_type = "tlm_master"
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system.tlm.port_data = "memory"
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# Route the connections:
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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system.tlm.port = system.membus.slave
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system.mem_mode = 'timing'
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# Start the simulation:
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root = Root(full_system = False, system = system)
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m5.instantiate()
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m5.simulate()
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