MIPS is back to compiling and building now!

arch/alpha/isa_traits.hh:
    used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs
    so other archs. can use SimpleCPU
arch/mips/SConscript:
    dont include common_syscall or tru64
arch/mips/faults.cc:
arch/mips/faults.hh:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
    Change Faults to new format
arch/mips/isa/decoder.isa:
    Fix readMiscReg access
    Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants
    of the sll instruction so I may need to make a separte class of instructions to handle thse better
arch/mips/isa/includes.isa:
    add isa_traits.hh and MipsISA included into every auto-gen file
arch/mips/isa_traits.cc:
    create copyMiscRegs function...
    delete useless code
arch/mips/isa_traits.hh:
    clean up for build
arch/mips/linux_process.cc:
    mem is now getMemPort(), linux process objects now take in a system argument
arch/mips/linux_process.hh:
    new argument for linux process
arch/mips/process.cc:
    add system
arch/mips/process.hh:
    add system variable
cpu/cpu_exec_context.cc:
    Change AlphaISA to TheISA
cpu/exec_context.hh:
    add readNextNPC and setNextNPC functions
cpu/simple/cpu.cc:
    include isa_traits for namespace declariation
cpu/simple/cpu.hh:
    PC & NPC access/modify functions
arch/mips/utility.hh:
    file needed for compile

--HG--
extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535

arch/alpha/isa_traits.hh

@@ -109,4 +109,6 @@ extern const int reg_redir[NumIntRegs];
 #endif
 };
 
+using namespace AlphaISA;
+
 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__

arch/mips/SConscript

@@ -57,9 +57,8 @@ full_system_sources = Split('''
 
 # Syscall emulation (non-full-system) sources
 syscall_emulation_sources = Split('''
-	common_syscall_emul.cc
 	linux_process.cc
-	tru64_process.cc
+        process.cc
 	''')
 
 # Set up complete list of sources based on configuration.

arch/mips/faults.cc

@@ -27,54 +27,105 @@
  */
 
 #include "arch/mips/faults.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/base.hh"
+#include "base/trace.hh"
 
-ResetFaultType * const ResetFault =
+namespace MipsISA
-    new ResetFaultType("reset", 1, 0x0001);
+{
-ArithmeticFaultType * const ArithmeticFault =
-    new ArithmeticFaultType("arith", 3, 0x0501);
-InterruptFaultType * const InterruptFault =
-    new InterruptFaultType("interrupt", 4, 0x0101);
-NDtbMissFaultType * const NDtbMissFault =
-    new NDtbMissFaultType("dtb_miss_single", 5, 0x0201);
-PDtbMissFaultType * const PDtbMissFault =
-    new PDtbMissFaultType("dtb_miss_double", 6, 0x0281);
-DtbPageFaultType * const DtbPageFault =
-    new DtbPageFaultType("dfault", 8, 0x0381);
-DtbAcvFaultType * const DtbAcvFault =
-    new DtbAcvFaultType("dfault", 9, 0x0381);
-ItbMissFaultType * const ItbMissFault =
-    new ItbMissFaultType("itbmiss", 10, 0x0181);
-ItbPageFaultType * const ItbPageFault =
-    new ItbPageFaultType("itbmiss", 11, 0x0181);
-ItbAcvFaultType * const ItbAcvFault =
-    new ItbAcvFaultType("iaccvio", 12, 0x0081);
-UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault =
-    new UnimplementedOpcodeFaultType("opdec", 13, 0x0481);
-FloatEnableFaultType * const FloatEnableFault =
-    new FloatEnableFaultType("fen", 14, 0x0581);
-PalFaultType * const PalFault =
-    new PalFaultType("pal", 15, 0x2001);
-IntegerOverflowFaultType * const IntegerOverflowFault =
-    new IntegerOverflowFaultType("intover", 16, 0x0501);
 
-Fault ** ListOfFaults[] = {
+FaultName MachineCheckFault::_name = "mchk";
-        (Fault **)&NoFault,
+FaultVect MachineCheckFault::_vect = 0x0401;
-        (Fault **)&ResetFault,
+FaultStat MachineCheckFault::_count;
-        (Fault **)&MachineCheckFault,
+
-        (Fault **)&ArithmeticFault,
+FaultName AlignmentFault::_name = "unalign";
-        (Fault **)&InterruptFault,
+FaultVect AlignmentFault::_vect = 0x0301;
-        (Fault **)&NDtbMissFault,
+FaultStat AlignmentFault::_count;
-        (Fault **)&PDtbMissFault,
+
-        (Fault **)&AlignmentFault,
+FaultName ResetFault::_name = "reset";
-        (Fault **)&DtbPageFault,
+FaultVect ResetFault::_vect = 0x0001;
-        (Fault **)&DtbAcvFault,
+FaultStat ResetFault::_count;
-        (Fault **)&ItbMissFault,
+
-        (Fault **)&ItbPageFault,
+FaultName ArithmeticFault::_name = "arith";
-        (Fault **)&ItbAcvFault,
+FaultVect ArithmeticFault::_vect = 0x0501;
-        (Fault **)&UnimplementedOpcodeFault,
+FaultStat ArithmeticFault::_count;
-        (Fault **)&FloatEnableFault,
+
-        (Fault **)&PalFault,
+FaultName InterruptFault::_name = "interrupt";
-        (Fault **)&IntegerOverflowFault,
+FaultVect InterruptFault::_vect = 0x0101;
-        };
+FaultStat InterruptFault::_count;
+
+FaultName NDtbMissFault::_name = "dtb_miss_single";
+FaultVect NDtbMissFault::_vect = 0x0201;
+FaultStat NDtbMissFault::_count;
+
+FaultName PDtbMissFault::_name = "dtb_miss_double";
+FaultVect PDtbMissFault::_vect = 0x0281;
+FaultStat PDtbMissFault::_count;
+
+FaultName DtbPageFault::_name = "dfault";
+FaultVect DtbPageFault::_vect = 0x0381;
+FaultStat DtbPageFault::_count;
+
+FaultName DtbAcvFault::_name = "dfault";
+FaultVect DtbAcvFault::_vect = 0x0381;
+FaultStat DtbAcvFault::_count;
+
+FaultName ItbMissFault::_name = "itbmiss";
+FaultVect ItbMissFault::_vect = 0x0181;
+FaultStat ItbMissFault::_count;
+
+FaultName ItbPageFault::_name = "itbmiss";
+FaultVect ItbPageFault::_vect = 0x0181;
+FaultStat ItbPageFault::_count;
+
+FaultName ItbAcvFault::_name = "iaccvio";
+FaultVect ItbAcvFault::_vect = 0x0081;
+FaultStat ItbAcvFault::_count;
+
+FaultName UnimplementedOpcodeFault::_name = "opdec";
+FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
+FaultStat UnimplementedOpcodeFault::_count;
+
+FaultName FloatEnableFault::_name = "fen";
+FaultVect FloatEnableFault::_vect = 0x0581;
+FaultStat FloatEnableFault::_count;
+
+FaultName PalFault::_name = "pal";
+FaultVect PalFault::_vect = 0x2001;
+FaultStat PalFault::_count;
+
+FaultName IntegerOverflowFault::_name = "intover";
+FaultVect IntegerOverflowFault::_vect = 0x0501;
+FaultStat IntegerOverflowFault::_count;
+
+#if FULL_SYSTEM
+
+void MipsFault::invoke(ExecContext * xc)
+{
+    FaultBase::invoke(xc);
+    countStat()++;
+
+    // exception restart address
+    if (setRestartAddress() || !xc->inPalMode())
+        xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC());
+
+    if (skipFaultingInstruction()) {
+        // traps...  skip faulting instruction.
+        xc->setMiscReg(MipsISA::IPR_EXC_ADDR,
+                   xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
+    }
+
+    xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
+    xc->setNextPC(xc->readPC() + sizeof(MachInst));
+}
+
+void ArithmeticFault::invoke(ExecContext * xc)
+{
+    FaultBase::invoke(xc);
+    panic("Arithmetic traps are unimplemented!");
+}
+
+#endif
+
+} // namespace MipsISA
 
-int NumFaults = sizeof(ListOfFaults) / sizeof(Fault **);

arch/mips/faults.hh

@@ -30,131 +30,240 @@
 #define __MIPS_FAULTS_HH__
 
 #include "sim/faults.hh"
-#include "arch/isa_traits.hh" //For the Addr type
+
+// The design of the "name" and "vect" functions is in sim/faults.hh
+
+namespace MipsISA
+{
+
+typedef const Addr FaultVect;
 
 class MipsFault : public FaultBase
 {
+  protected:
+    virtual bool skipFaultingInstruction() {return false;}
+    virtual bool setRestartAddress() {return true;}
   public:
-    MipsFault(char * newName, int newId, Addr newVect)
+#if FULL_SYSTEM
-        : FaultBase(newName, newId), vect(newVect)
+    void invoke(ExecContext * xc);
-    {;}
+#endif
-
+    virtual FaultVect vect() = 0;
-    Addr vect;
+    virtual FaultStat & countStat() = 0;
 };
 
-extern class ResetFaultType : public MipsFault
+class MachineCheckFault : public MipsFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    ResetFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const ResetFault;
+    bool isMachineCheckFault() {return true;}
+};
 
-extern class ArithmeticFaultType : public MipsFault
+class AlignmentFault : public MipsFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    ArithmeticFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const ArithmeticFault;
+    bool isAlignmentFault() {return true;}
+};
 
-extern class InterruptFaultType : public MipsFault
+static inline Fault genMachineCheckFault()
 {
-  public:
+    return new MachineCheckFault;
-    InterruptFaultType(char * newName, int newId, Addr newVect)
+}
-        : MipsFault(newName, newId, newVect)
-    {;}
-} * const InterruptFault;
 
-extern class NDtbMissFaultType : public MipsFault
+static inline Fault genAlignmentFault()
 {
-  public:
+    return new AlignmentFault;
-    NDtbMissFaultType(char * newName, int newId, Addr newVect)
+}
-        : MipsFault(newName, newId, newVect)
-    {;}
-} * const NDtbMissFault;
 
-extern class PDtbMissFaultType : public MipsFault
+class ResetFault : public MipsFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    PDtbMissFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const PDtbMissFault;
+};
 
-extern class DtbPageFaultType : public MipsFault
+class ArithmeticFault : public MipsFault
 {
+  protected:
+    bool skipFaultingInstruction() {return true;}
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    DtbPageFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const DtbPageFault;
+#if FULL_SYSTEM
+    void invoke(ExecContext * xc);
+#endif
+};
 
-extern class DtbAcvFaultType : public MipsFault
+class InterruptFault : public MipsFault
 {
+  protected:
+    bool setRestartAddress() {return false;}
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    DtbAcvFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const DtbAcvFault;
+};
 
-extern class ItbMissFaultType : public MipsFault
+class NDtbMissFault : public MipsFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    ItbMissFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const ItbMissFault;
+};
 
-extern class ItbPageFaultType : public MipsFault
+class PDtbMissFault : public MipsFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    ItbPageFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const ItbPageFault;
+};
 
-extern class ItbAcvFaultType : public MipsFault
+class DtbPageFault : public MipsFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    ItbAcvFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const ItbAcvFault;
+};
 
-extern class UnimplementedOpcodeFaultType : public MipsFault
+class DtbAcvFault : public MipsFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const UnimplementedOpcodeFault;
+};
 
-extern class FloatEnableFaultType : public MipsFault
+class ItbMissFault : public MipsFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    FloatEnableFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const FloatEnableFault;
+};
 
-extern class PalFaultType : public MipsFault
+class ItbPageFault : public MipsFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    PalFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const PalFault;
+};
 
-extern class IntegerOverflowFaultType : public MipsFault
+class ItbAcvFault : public MipsFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
   public:
-    IntegerOverflowFaultType(char * newName, int newId, Addr newVect)
+    FaultName name() {return _name;}
-        : MipsFault(newName, newId, newVect)
+    FaultVect vect() {return _vect;}
-    {;}
+    FaultStat & countStat() {return _count;}
-} * const IntegerOverflowFault;
+};
 
-extern Fault ** ListOfFaults[];
+class UnimplementedOpcodeFault : public MipsFault
-extern int NumFaults;
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+};
+
+class FloatEnableFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+};
+
+class PalFault : public MipsFault
+{
+  protected:
+    bool skipFaultingInstruction() {return true;}
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+};
+
+class IntegerOverflowFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+};
+
+} // MipsISA namespace
 
 #endif // __FAULTS_HH__

arch/mips/isa/decoder.isa

@@ -20,8 +20,8 @@ decode OPCODE_HI default Unknown::unknown() {
             0x0: decode FUNCTION_LO {
                 0x1: decode MOVCI {
                     format BasicOp {
-                        0: movf({{ if (xc->readMiscReg(FPCR,0) != CC) Rd = Rs}});
+                        0: movf({{ if (xc->readMiscReg(FPCR) != CC) Rd = Rs}});
-                        1: movt({{ if (xc->readMiscReg(FPCR,0) == CC) Rd = Rs}});
+                        1: movt({{ if (xc->readMiscReg(FPCR) == CC) Rd = Rs}});
                     }
                 }
 
@@ -31,15 +31,10 @@ decode OPCODE_HI default Unknown::unknown() {
                     //are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
 
                     0x0: decode RS {
-                        0x0: decode RT default BasicOp::sll({{ Rd = Rt.uw << SA; }}) {
+                        0x0: sll({{ Rd = Rt.uw << SA; }});
-                            0x0: decode RD{
+                        //0x0:nop({{ ; }});  //really sll r0,r0,0
-                                0x0: decode HINT {
+                        //	    0x1:ssnop({{ ; }});//really sll r0,r0,1
-                                    0x0:nop({{}});  //really sll r0,r0,0
+                        //    0x3:ehb({{ ; }});  //really sll r0,r0,3
-                                    0x1:ssnop({{}});//really sll r0,r0,1
-                                    0x3:ehb({{}});  //really sll r0,r0,3
-                                }
-                            }
-                        }
                     }
 
                     0x2: decode SRL {
@@ -283,55 +278,37 @@ decode OPCODE_HI default Unknown::unknown() {
 
                         0x0: decode SC {
                             0x0: dvpe({{
-                                int idx;
+                                Rt.sw = xc->readMiscReg(MVPControl);
-                                int sel;
+                                xc->setMiscReg(MVPControl,0);
-                                getMiscRegIdx(MVPControl,idx,sel);
-                                Rt.sw = xc->readMiscReg(idx,sel);
-                                xc->setMiscReg(idx,sel);
                             }});
 
                             0x1: evpe({{
-                                int idx;
+                                Rt.sw = xc->readMiscReg(MVPControl);
-                                int sel;
+                                xc->setMiscReg(MVPControl,1);
-                                getMiscRegIdx(MVPControl,idx,sel);
-                                Rt.sw = xc->readMiscReg(idx,sel);
-                                xc->setMiscReg(idx,sel,1);
                             }});
                         }
 
                         0x1: decode SC {
                             0x0: dmt({{
-                                int idx;
+                                Rt.sw = xc->readMiscReg(VPEControl);
-                                int sel;
+                                xc->setMiscReg(VPEControl,0);
-                                getMiscRegIdx(VPEControl,idx,sel);
-                                Rt.sw = xc->readMiscReg(idx,sel);
-                                xc->setMiscReg(idx,sel);
                             }});
 
                             0x1: emt({{
-                                int idx;
+                                Rt.sw = xc->readMiscReg(VPEControl);
-                                int sel;
+                                xc->setMiscReg(VPEControl,1);
-                                getMiscRegIdx(VPEControl,idx,sel);
-                                Rt.sw = xc->readMiscReg(idx,sel);
-                                xc->setMiscReg(idx,sel,1);
                             }});
                         }
 
                         0xC: decode SC {
                             0x0: di({{
-                                int idx;
+                                Rt.sw = xc->readMiscReg(Status);
-                                int sel;
+                                xc->setMiscReg(Status,0);
-                                getMiscRegIdx(Status,idx,sel);
-                                Rt.sw = xc->readMiscReg(idx,sel);
-                                xc->setMiscReg(idx,sel);
                             }});
 
                             0x1: ei({{
-                                int idx;
+                                Rt.sw = xc->readMiscReg(Status);
-                                int sel;
+                                xc->setMiscReg(Status,1);
-                                getMiscRegIdx(Status,idx,sel);
-                                Rt.sw = xc->readMiscReg(idx,sel);
-                                xc->setMiscReg(idx,sel,1);
                             }});
                         }
                     }

arch/mips/isa/formats/unimp.isa

@@ -111,7 +111,7 @@ output exec {{
     {
         panic("attempt to execute unimplemented instruction '%s' "
               "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
     }
 
     Fault

arch/mips/isa/formats/unknown.isa

@@ -42,7 +42,7 @@ output exec {{
     {
         panic("attempt to execute unknown instruction "
               "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
     }
 }};
 

arch/mips/isa/includes.isa

@@ -9,10 +9,11 @@ output header {{
 #include <iomanip>
 
 #include "cpu/static_inst.hh"
-#include "mem/mem_req.hh"  // some constructors use MemReq flags
+#include "arch/mips/isa_traits.hh"
 }};
 
 output decoder {{
+#include "arch/mips/isa_traits.hh"
 #include "base/cprintf.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/exec_context.hh"  // for Jump::branchTarget()
@@ -21,9 +22,12 @@ output decoder {{
 #if defined(linux)
 #include <fenv.h>
 #endif
+
+using namespace MipsISA;
 }};
 
 output exec {{
+#include "arch/mips/isa_traits.hh"
 #include <math.h>
 #if defined(linux)
 #include <fenv.h>
@@ -35,5 +39,7 @@ output exec {{
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "sim/sim_exit.hh"
+
+using namespace MipsISA;
 }};
 

arch/mips/isa_traits.cc

@@ -34,97 +34,25 @@
 using namespace MipsISA;
 
 
-//Function now Obsolete in current state.
-//If anyting this should return the correct miscreg index
-//but that is handled implicitly with enums anyway
 void
-MipsISA::getMiscRegIdx(int reg_name,int &idx, int &sel)
+MipsISA::MiscRegFile::copyMiscRegs(ExecContext *xc)
 {
-    switch(reg_name)
+    /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
-    {
+    uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
-      case Index: idx = 0; sel = 0; break;           //0-0 Index into the TLB array
+    lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
-      case MVPControl:    idx = 0; sel = 1; break;   //0-1 Per-processor register containing global
+    lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
-      case MVPConf0:     idx = 0; sel = 2; break;    //0-2 Per-processor register containing global
-      case MVPConf1:     idx = 0; sel = 3; break;    //0-3 Per-processor register containing global
-      case Random:       idx = 1; sel = 3; break;    //1-0 Randomly generated index into the TLB array
-      case VPEControl:  idx = 1; sel = 1; break;     //1-1 Per-VPE register containing relatively volatile
-        //thread configuration data
-      case VPEConf0:     idx = 1; sel = 2; break;    //1-2 Per-VPE multi-thread configuration
-        //information
-      case VPEConf1:     idx = 1; sel = 3; break;    //1-3 Per-VPE multi-thread configuration
-        //information
-      case YQMask:       idx = 1; sel = 4; break;    //Per-VPE register defining which YIELD
-        //qualifier bits may be used without generating
-        //an exception
-      case VPESchedule:   idx = 1; sel = 5; break;
-      case VPEScheFBack:  idx = 1; sel = 6; break;
-      case VPEOpt:        idx = 1; sel = 7; break;
-      case EntryLo0:  idx = 1; sel = 5; break;
-      case TCStatus:  idx = 1; sel = 5; break;
-      case TCBind:  idx = 1; sel = 5; break;
-      case TCRestart:  idx = 1; sel = 5; break;
-      case TCHalt:  idx = 1; sel = 5; break;
-      case TCContext:  idx = 1; sel = 5; break;
-      case TCSchedule:  idx = 1; sel = 5; break;
-      case TCScheFBack: panic("Accessing Unimplemented CP0 Register"); break;
-      case EntryLo1: panic("Accessing Unimplemented CP0 Register"); break;
-      case Context: panic("Accessing Unimplemented CP0 Register"); break;
-      case ContextConfig: panic("Accessing Unimplemented CP0 Register"); break;
-        //case PageMask: panic("Accessing Unimplemented CP0 Register"); break;
-      case PageGrain: panic("Accessing Unimplemented CP0 Register"); break;
-      case Wired: panic("Accessing Unimplemented CP0 Register"); break;
-      case SRSConf0: panic("Accessing Unimplemented CP0 Register"); break;
-      case SRSConf1: panic("Accessing Unimplemented CP0 Register"); break;
-      case SRSConf2: panic("Accessing Unimplemented CP0 Register"); break;
-      case SRSConf3: panic("Accessing Unimplemented CP0 Register"); break;
-      case SRSConf4: panic("Accessing Unimplemented CP0 Register"); break;
-      case BadVAddr: panic("Accessing Unimplemented CP0 Register"); break;
-      case Count: panic("Accessing Unimplemented CP0 Register"); break;
-      case EntryHi: panic("Accessing Unimplemented CP0 Register"); break;
-      case Compare: panic("Accessing Unimplemented CP0 Register"); break;
-      case Status:  idx = 12; sel = 0; break;      //12-0 Processor status and control
-      case IntCtl:  idx = 12; sel = 1; break;      //12-1 Interrupt system status and control
-      case SRSCtl:  idx = 12; sel = 2; break;      //12-2 Shadow register set status and control
-      case SRSMap:  idx = 12; sel = 3; break;      //12-3 Shadow set IPL mapping
-      case Cause:  idx = 13; sel = 0; break;       //13-0 Cause of last general exception
-      case EPC:  idx = 14; sel = 0; break;         //14-0 Program counter at last exception
-      case PrId:  idx = 15; sel = 0; break;        //15-0 Processor identification and revision
-      case EBase:  idx = 15; sel = 1; break;       //15-1 Exception vector base register
-      case Config: panic("Accessing Unimplemented CP0 Register"); break;
-      case Config1: panic("Accessing Unimplemented CP0 Register"); break;
-      case Config2: panic("Accessing Unimplemented CP0 Register"); break;
-      case Config3: panic("Accessing Unimplemented CP0 Register"); break;
-      case LLAddr: panic("Accessing Unimplemented CP0 Register"); break;
-      case WatchLo: panic("Accessing Unimplemented CP0 Register"); break;
-      case WatchHi: panic("Accessing Unimplemented CP0 Register"); break;
-      case Debug: panic("Accessing Unimplemented CP0 Register"); break;
-      case TraceControl1: panic("Accessing Unimplemented CP0 Register"); break;
-      case TraceControl2: panic("Accessing Unimplemented CP0 Register"); break;
-      case UserTraceData: panic("Accessing Unimplemented CP0 Register"); break;
-      case TraceBPC: panic("Accessing Unimplemented CP0 Register"); break;
-      case DEPC: panic("Accessing Unimplemented CP0 Register"); break;
-      case PerfCnt: panic("Accessing Unimplemented CP0 Register"); break;
-      case ErrCtl: panic("Accessing Unimplemented CP0 Register"); break;
-      case CacheErr0: panic("Accessing Unimplemented CP0 Register"); break;
-      case CacheErr1: panic("Accessing Unimplemented CP0 Register"); break;
-      case CacheErr2: panic("Accessing Unimplemented CP0 Register"); break;
-      case CacheErr3: panic("Accessing Unimplemented CP0 Register"); break;
-      case TagLo: panic("Accessing Unimplemented CP0 Register"); break;
-      case DataLo: panic("Accessing Unimplemented CP0 Register"); break;
-      case TagHi: panic("Accessing Unimplemented CP0 Register"); break;
-      case DataHi: panic("Accessing Unimplemented CP0 Register"); break;
-      case ErrorEPC: panic("Accessing Unimplemented CP0 Register"); break;
 
-      default:
+#if FULL_SYSTEM
-        panic("Accessing Unimplemented Misc. Register");
+    copyIprs(xc);
-    }
+    #endif*/
 }
 
-void RegFile::coldReset()
+
+void MipsISA::RegFile::coldReset()
 {
     //CP0 Random Reg:
     //Randomly generated index into the TLB array
-    miscRegs[Random] = 0x0000003f;
+    /*miscRegs[Random] = 0x0000003f;
 
     //CP0 Wired Reg.
     miscRegs[Wired] = 0x0000000;
@@ -175,7 +103,7 @@ void RegFile::coldReset()
     miscRegs[PerfCnt0] = 0x0000000;
 
    //CP0 PERFCNTL2
-    miscRegs[PerfCnt1] = 0x0000000;
+   miscRegs[PerfCnt1] = 0x0000000;*/
 
 }
 
@@ -247,6 +175,10 @@ void RegFile::createCP0Regs()
 
     //Cop-0 Regs. Bank 20:
     miscRegs[20].resize(1);
+      case PerfCnt0: panic("Accessing Unimplemented CP0 Register"); break;
+      case PerfCnt1: panic("Accessing Unimplemented CP0 Register"); break;
+      case PerfCnt2: panic("Accessing Unimplemented CP0 Register"); break;
+      case PerfCnt3: panic("Accessing Unimplemented CP0 Register"); break;
 
     //Cop-0 Regs. Bank 21:
     //miscRegs[21].resize(1);

arch/mips/isa_traits.hh

@@ -54,12 +54,48 @@ int DTB_ASN_ASN(uint64_t reg);
 int ITB_ASN_ASN(uint64_t reg);
 };
 
+#if !FULL_SYSTEM
+class SyscallReturn {
+        public:
+           template <class T>
+           SyscallReturn(T v, bool s)
+           {
+               retval = (uint64_t)v;
+               success = s;
+           }
+
+           template <class T>
+           SyscallReturn(T v)
+           {
+               success = (v >= 0);
+               retval = (uint64_t)v;
+           }
+
+           ~SyscallReturn() {}
+
+           SyscallReturn& operator=(const SyscallReturn& s) {
+               retval = s.retval;
+               success = s.success;
+               return *this;
+           }
+
+           bool successful() { return success; }
+           uint64_t value() { return retval; }
+
+
+       private:
+           uint64_t retval;
+           bool success;
+};
+#endif
+
 namespace MipsISA
 {
     typedef uint32_t MachInst;
-//  typedef uint64_t Addr;
+    typedef uint32_t MachInst;
+    typedef uint64_t ExtMachInst;
     typedef uint8_t  RegIndex;
-
+//  typedef uint64_t Addr;
     enum {
         MemoryEnd = 0xffffffffffffffffULL,
 
@@ -87,7 +123,9 @@ namespace MipsISA
         ArgumentReg3 = 19,
         ArgumentReg4 = 20,
         ArgumentReg5 = 21,
-
+        SyscallNumReg = ReturnValueReg,
+        SyscallPseudoReturnReg = ArgumentReg4,
+        SyscallSuccessReg = 19,
         LogVMPageSize = 13,	// 8K bytes
         VMPageSize = (1 << LogVMPageSize),
 
@@ -129,8 +167,7 @@ namespace MipsISA
     typedef uint64_t MiscReg;
 //typedef MiscReg MiscRegFile[NumMiscRegs];
     class MiscRegFile {
-      public:
+
-        MiscReg
       protected:
         uint64_t	fpcr;		// floating point condition codes
         uint64_t	uniq;		// process-unique register
@@ -145,6 +182,8 @@ namespace MipsISA
         int getInstAsid();
         int getDataAsid();
 
+        void copyMiscRegs(ExecContext *xc);
+
         MiscReg readReg(int misc_reg)
         { return miscRegFile[misc_reg]; }
 
@@ -159,7 +198,7 @@ namespace MipsISA
         { miscRegFile[misc_reg] = val; return NoFault; }
 
 #if FULL_SYSTEM
-        void clearIprs() { };
+        void clearIprs() { }
 
       protected:
         InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
@@ -249,7 +288,7 @@ namespace MipsISA
 
         EPC = 105,//105-112        //14-0 Program counter at last exception
 
-        PRId = 113//113-120,       //15-0 Processor identification and revision
+        PRId = 113,//113-120,       //15-0 Processor identification and revision
         EBase = 114,      //15-1 Exception vector base register
 
         Config = 121,//Bank 16: 121-128
@@ -411,7 +450,7 @@ extern const Addr PageOffset;
         void coldReset();
     };
 
-    StaticInstPtr decodeInst(MachInst);
+    StaticInstPtr decodeInst(ExtMachInst);
 
     // return a no-op instruction... used for instruction fetch faults
     extern const MachInst NoopMachInst;
@@ -422,8 +461,20 @@ extern const Addr PageOffset;
         ITOUCH_ANNOTE = 0xffffffff,
     };
 
-   void getMiscRegIdx(int reg_name,int &idx, int &sel);
+//void getMiscRegIdx(int reg_name,int &idx, int &sel);
 
+    static inline ExtMachInst
+    makeExtMI(MachInst inst, const uint64_t &pc) {
+#if FULL_SYSTEM
+        ExtMachInst ext_inst = inst;
+        if (pc && 0x1)
+            return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
+        else
+            return ext_inst;
+#else
+        return ExtMachInst(inst);
+#endif
+    }
 
     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
         panic("register classification not implemented");
@@ -470,6 +521,22 @@ extern const Addr PageOffset;
         return 0;
     }
 
+    static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
+    {
+        // check for error condition.  SPARC syscall convention is to
+        // indicate success/failure in reg the carry bit of the ccr
+        // and put the return value itself in the standard return value reg ().
+        if (return_value.successful()) {
+            // no error
+            //regs->miscRegFile.ccrFields.iccFields.c = 0;
+            regs->intRegFile[ReturnValueReg] = return_value.value();
+        } else {
+            // got an error, return details
+            //regs->miscRegFile.ccrFields.iccFields.c = 1;
+            regs->intRegFile[ReturnValueReg] = -return_value.value();
+        }
+    }
+
     // Machine operations
 
     void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
@@ -498,43 +565,6 @@ extern const Addr PageOffset;
     const Addr MaxAddr = (Addr)-1;
 };
 
-#if !FULL_SYSTEM
-class SyscallReturn {
-        public:
-           template <class T>
-           SyscallReturn(T v, bool s)
-           {
-               retval = (uint64_t)v;
-               success = s;
-           }
-
-           template <class T>
-           SyscallReturn(T v)
-           {
-               success = (v >= 0);
-               retval = (uint64_t)v;
-           }
-
-           ~SyscallReturn() {}
-
-           SyscallReturn& operator=(const SyscallReturn& s) {
-               retval = s.retval;
-               success = s.success;
-               return *this;
-           }
-
-           bool successful() { return success; }
-           uint64_t value() { return retval; }
-
-
-       private:
-           uint64_t retval;
-           bool success;
-};
-
-#endif
-
-
 #if FULL_SYSTEM
 //typedef TheISA::InternalProcReg InternalProcReg;
 //const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
@@ -543,4 +573,6 @@ class SyscallReturn {
 #include "arch/mips/mips34k.hh"
 #endif
 
+using namespace MipsISA;
+
 #endif // __ARCH_MIPS_ISA_TRAITS_HH__

arch/mips/linux_process.cc

@@ -33,7 +33,6 @@
 #include "base/trace.hh"
 #include "cpu/exec_context.hh"
 #include "kern/linux/linux.hh"
-#include "mem/functional/functional.hh"
 
 #include "sim/process.hh"
 #include "sim/syscall_emul.hh"
@@ -54,7 +53,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "mips");
 
-    name.copyOut(xc->mem);
+    name.copyOut(xc->getMemPort());
     return 0;
 }
 
@@ -74,7 +73,7 @@ osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
           TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
           // I don't think this exactly matches the HW FPCR
           *fpcr = 0;
-          fpcr.copyOut(xc->mem);
+          fpcr.copyOut(xc->getMemPort());
           return 0;
       }
 
@@ -100,7 +99,7 @@ osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
       case 14: { // SSI_IEEE_FP_CONTROL
           TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
           // I don't think this exactly matches the HW FPCR
-          fpcr.copyIn(xc->mem);
+          fpcr.copyIn(xc->getMemPort());
           DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
                    " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
           return 0;
@@ -566,15 +565,16 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
 
 MipsLinuxProcess::MipsLinuxProcess(const std::string &name,
                                      ObjectFile *objFile,
+                                     System *system,
                                      int stdin_fd,
                                      int stdout_fd,
                                      int stderr_fd,
                                      std::vector<std::string> &argv,
                                      std::vector<std::string> &envp)
-    : LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp),
+    : LiveProcess(name, objFile, system, stdin_fd, stdout_fd, stderr_fd, argv, envp),
      Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
 {
-    init_regs->intRegFile[0] = 0;
+    //init_regs->intRegFile[0] = 0;
 }
 
 

arch/mips/linux_process.hh

@@ -39,6 +39,7 @@ class MipsLinuxProcess : public LiveProcess
     /// Constructor.
     MipsLinuxProcess(const std::string &name,
                       ObjectFile *objFile,
+                      System *system,
                       int stdin_fd, int stdout_fd, int stderr_fd,
                       std::vector<std::string> &argv,
                       std::vector<std::string> &envp);

arch/mips/process.cc

@@ -28,11 +28,13 @@
 
 #include "arch/mips/process.hh"
 
+using namespace std;
+
 namespace MipsISA
 {
 
 LiveProcess *
-createProcess(const string &nm, ObjectFile * objFile,
+createProcess(const string &nm, ObjectFile * objFile, System * system,
         int stdin_fd, int stdout_fd, int stderr_fd,
         vector<string> &argv, vector<string> &envp)
 {
@@ -41,7 +43,7 @@ createProcess(const string &nm, ObjectFile * objFile,
         fatal("Object file does not match architecture.");
     switch (objFile->getOpSys()) {
       case ObjectFile::Linux:
-        process = new MipsLinuxProcess(nm, objFile,
+        process = new MipsLinuxProcess(nm, objFile,system,
                                         stdin_fd, stdout_fd, stderr_fd,
                                         argv, envp);
         break;

arch/mips/process.hh

@@ -32,11 +32,13 @@
 #include "arch/mips/linux_process.hh"
 #include "base/loader/object_file.hh"
 
+using namespace std;
+
 namespace MipsISA
 {
 
 LiveProcess *
-createProcess(const string &nm, ObjectFile * objFile,
+createProcess(const string &nm, ObjectFile * objFile,System * system,
         int stdin_fd, int stdout_fd, int stderr_fd,
         vector<string> &argv, vector<string> &envp);
 

arch/mips/utility.hh

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_MIPS_UTILITY_HH__
+#define __ARCH_MIPS_UTILITY_HH__
+
+//Placeholder file for now
+
+#endif

cpu/cpu_exec_context.cc

@@ -270,12 +270,12 @@ void
 CPUExecContext::copyArchRegs(ExecContext *xc)
 {
     // First loop through the integer registers.
-    for (int i = 0; i < AlphaISA::NumIntRegs; ++i) {
+    for (int i = 0; i < TheISA::NumIntRegs; ++i) {
         setIntReg(i, xc->readIntReg(i));
     }
 
     // Then loop through the floating point registers.
-    for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) {
+    for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
         setFloatRegDouble(i, xc->readFloatRegDouble(i));
         setFloatRegInt(i, xc->readFloatRegInt(i));
     }
@@ -286,5 +286,6 @@ CPUExecContext::copyArchRegs(ExecContext *xc)
     // Lastly copy PC/NPC
     setPC(xc->readPC());
     setNextPC(xc->readNextPC());
+    setNextNPC(xc->readNextNPC());
 }
 

cpu/exec_context.hh

@@ -189,6 +189,10 @@ class ExecContext
 
     virtual void setNextPC(uint64_t val) = 0;
 
+    virtual uint64_t readNextNPC() = 0;
+
+    virtual void setNextNPC(uint64_t val) = 0;
+
     virtual MiscReg readMiscReg(int misc_reg) = 0;
 
     virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
@@ -362,6 +366,10 @@ class ProxyExecContext : public ExecContext
 
     void setNextPC(uint64_t val) { actualXC->setNextPC(val); }
 
+    uint64_t readNextNPC() { return actualXC->readNextNPC(); }
+
+    void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); }
+
     MiscReg readMiscReg(int misc_reg)
     { return actualXC->readMiscReg(misc_reg); }
 

cpu/simple/cpu.cc

@@ -75,9 +75,11 @@
 #endif // FULL_SYSTEM
 
 using namespace std;
-//The SimpleCPU does alpha only
-using namespace AlphaISA;
 
+//The SimpleCPU does alpha only
+//Change this to include arch/isa_traits.hh?
+//using namespace AlphaISA;
+#include "arch/isa_traits.hh"
 
 SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
     : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)

cpu/simple/cpu.hh

@@ -364,7 +364,12 @@ class SimpleCPU : public BaseCPU
     }
 
     uint64_t readPC() { return cpuXC->readPC(); }
+    uint64_t readNextPC() { return cpuXC->readNextPC(); }
+    uint64_t readNextNPC() { return cpuXC->readNextNPC(); }
+
+    void setPC(uint64_t val) { cpuXC->setPC(val); }
     void setNextPC(uint64_t val) { cpuXC->setNextPC(val); }
+    void setNextNPC(uint64_t val) { cpuXC->setNextNPC(val); }
 
     MiscReg readMiscReg(int misc_reg)
     {