4d19bbeeeb
arch/alpha/isa_traits.hh:
used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs
so other archs. can use SimpleCPU
arch/mips/SConscript:
dont include common_syscall or tru64
arch/mips/faults.cc:
arch/mips/faults.hh:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
Change Faults to new format
arch/mips/isa/decoder.isa:
Fix readMiscReg access
Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants
of the sll instruction so I may need to make a separte class of instructions to handle thse better
arch/mips/isa/includes.isa:
add isa_traits.hh and MipsISA included into every auto-gen file
arch/mips/isa_traits.cc:
create copyMiscRegs function...
delete useless code
arch/mips/isa_traits.hh:
clean up for build
arch/mips/linux_process.cc:
mem is now getMemPort(), linux process objects now take in a system argument
arch/mips/linux_process.hh:
new argument for linux process
arch/mips/process.cc:
add system
arch/mips/process.hh:
add system variable
cpu/cpu_exec_context.cc:
Change AlphaISA to TheISA
cpu/exec_context.hh:
add readNextNPC and setNextNPC functions
cpu/simple/cpu.cc:
include isa_traits for namespace declariation
cpu/simple/cpu.hh:
PC & NPC access/modify functions
arch/mips/utility.hh:
file needed for compile
--HG--
extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535
131 lines
4.3 KiB
C++
131 lines
4.3 KiB
C++
/*
|
|
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
#include "arch/mips/faults.hh"
|
|
#include "cpu/exec_context.hh"
|
|
#include "cpu/base.hh"
|
|
#include "base/trace.hh"
|
|
|
|
namespace MipsISA
|
|
{
|
|
|
|
FaultName MachineCheckFault::_name = "mchk";
|
|
FaultVect MachineCheckFault::_vect = 0x0401;
|
|
FaultStat MachineCheckFault::_count;
|
|
|
|
FaultName AlignmentFault::_name = "unalign";
|
|
FaultVect AlignmentFault::_vect = 0x0301;
|
|
FaultStat AlignmentFault::_count;
|
|
|
|
FaultName ResetFault::_name = "reset";
|
|
FaultVect ResetFault::_vect = 0x0001;
|
|
FaultStat ResetFault::_count;
|
|
|
|
FaultName ArithmeticFault::_name = "arith";
|
|
FaultVect ArithmeticFault::_vect = 0x0501;
|
|
FaultStat ArithmeticFault::_count;
|
|
|
|
FaultName InterruptFault::_name = "interrupt";
|
|
FaultVect InterruptFault::_vect = 0x0101;
|
|
FaultStat InterruptFault::_count;
|
|
|
|
FaultName NDtbMissFault::_name = "dtb_miss_single";
|
|
FaultVect NDtbMissFault::_vect = 0x0201;
|
|
FaultStat NDtbMissFault::_count;
|
|
|
|
FaultName PDtbMissFault::_name = "dtb_miss_double";
|
|
FaultVect PDtbMissFault::_vect = 0x0281;
|
|
FaultStat PDtbMissFault::_count;
|
|
|
|
FaultName DtbPageFault::_name = "dfault";
|
|
FaultVect DtbPageFault::_vect = 0x0381;
|
|
FaultStat DtbPageFault::_count;
|
|
|
|
FaultName DtbAcvFault::_name = "dfault";
|
|
FaultVect DtbAcvFault::_vect = 0x0381;
|
|
FaultStat DtbAcvFault::_count;
|
|
|
|
FaultName ItbMissFault::_name = "itbmiss";
|
|
FaultVect ItbMissFault::_vect = 0x0181;
|
|
FaultStat ItbMissFault::_count;
|
|
|
|
FaultName ItbPageFault::_name = "itbmiss";
|
|
FaultVect ItbPageFault::_vect = 0x0181;
|
|
FaultStat ItbPageFault::_count;
|
|
|
|
FaultName ItbAcvFault::_name = "iaccvio";
|
|
FaultVect ItbAcvFault::_vect = 0x0081;
|
|
FaultStat ItbAcvFault::_count;
|
|
|
|
FaultName UnimplementedOpcodeFault::_name = "opdec";
|
|
FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
|
|
FaultStat UnimplementedOpcodeFault::_count;
|
|
|
|
FaultName FloatEnableFault::_name = "fen";
|
|
FaultVect FloatEnableFault::_vect = 0x0581;
|
|
FaultStat FloatEnableFault::_count;
|
|
|
|
FaultName PalFault::_name = "pal";
|
|
FaultVect PalFault::_vect = 0x2001;
|
|
FaultStat PalFault::_count;
|
|
|
|
FaultName IntegerOverflowFault::_name = "intover";
|
|
FaultVect IntegerOverflowFault::_vect = 0x0501;
|
|
FaultStat IntegerOverflowFault::_count;
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
void MipsFault::invoke(ExecContext * xc)
|
|
{
|
|
FaultBase::invoke(xc);
|
|
countStat()++;
|
|
|
|
// exception restart address
|
|
if (setRestartAddress() || !xc->inPalMode())
|
|
xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC());
|
|
|
|
if (skipFaultingInstruction()) {
|
|
// traps... skip faulting instruction.
|
|
xc->setMiscReg(MipsISA::IPR_EXC_ADDR,
|
|
xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
|
|
}
|
|
|
|
xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
|
|
xc->setNextPC(xc->readPC() + sizeof(MachInst));
|
|
}
|
|
|
|
void ArithmeticFault::invoke(ExecContext * xc)
|
|
{
|
|
FaultBase::invoke(xc);
|
|
panic("Arithmetic traps are unimplemented!");
|
|
}
|
|
|
|
#endif
|
|
|
|
} // namespace MipsISA
|
|
|