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Minor differences apparently from recent changes
This commit is contained in:
Steve Reinhardt 2015-03-07 13:55:56 -05:00
parent 8909843a76
commit 4b048901cf
18 changed files with 2664 additions and 2559 deletions
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9
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -110,6 +111,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@ -135,11 +137,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port

11
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
View file

@ -3,6 +3,7 @@
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"slave": {
@ -15,10 +16,10 @@
},
"name": "membus",
"snoop_filter": null,
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"header_cycles": 1,
"system": "system",
"width": 8,
"width": 16,
"eventq_index": 0,
"master": {
"peer": [
@ -26,10 +27,13 @@
],
"role": "MASTER"
},
"response_latency": 2,
"cxx_class": "CoherentXBar",
"path": "system.membus",
"snoop_response_latency": 4,
"type": "CoherentXBar",
"use_default_range": false
"use_default_range": false,
"frontend_latency": 3
},
"symbolfile": "",
"readfile": "",
@ -177,6 +181,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
"kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,

6
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2014 15:53:23
gem5 started Sep 21 2014 16:10:49
gem5 executing on zizzer
gem5 compiled Mar 7 2015 13:46:57
gem5 started Mar 7 2015 13:47:23
gem5 executing on zizzer2
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

52
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2577407 # Simulator instruction rate (inst/s)
host_op_rate 2577191 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1288569274 # Simulator tick rate (ticks/s)
host_mem_usage 218888 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
host_inst_rate 1781493 # Simulator instruction rate (inst/s)
host_op_rate 1781360 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 890669168 # Simulator tick rate (ticks/s)
host_mem_usage 214316 # Number of bytes of host memory used
host_seconds 0.28 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -35,27 +35,6 @@ system.physmem.bw_write::total 1670144451 # Wr
system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 624454 # Transaction distribution
system.membus.trans_dist::ReadResp 624454 # Transaction distribution
system.membus.trans_dist::WriteReq 56340 # Transaction distribution
system.membus.trans_dist::WriteResp 56340 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1000038 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 361550 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1361588 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2000076 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1290162 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 3290238 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 680794 # Request fanout histogram
system.membus.snoop_fanout::mean 0.734464 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.441618 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 180775 26.55% 26.55% # Request fanout histogram
system.membus.snoop_fanout::1 500019 73.45% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 680794 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@ -148,5 +127,26 @@ system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 500019 # Class of executed instruction
system.membus.trans_dist::ReadReq 624454 # Transaction distribution
system.membus.trans_dist::ReadResp 624454 # Transaction distribution
system.membus.trans_dist::WriteReq 56340 # Transaction distribution
system.membus.trans_dist::WriteResp 56340 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1000038 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 361550 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1361588 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2000076 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1290162 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 3290238 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 680794 # Request fanout histogram
system.membus.snoop_fanout::mean 0.734464 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.441618 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 180775 26.55% 26.55% # Request fanout histogram
system.membus.snoop_fanout::1 500019 73.45% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 680794 # Request fanout histogram
---------- End Simulation Statistics ----------

17
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -82,6 +83,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -122,6 +124,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -171,6 +174,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@ -204,8 +208,11 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
@ -223,6 +230,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@ -248,11 +256,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side

21
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
View file

@ -3,6 +3,7 @@
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"slave": {
@ -14,10 +15,10 @@
},
"name": "membus",
"snoop_filter": null,
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"header_cycles": 1,
"system": "system",
"width": 8,
"width": 16,
"eventq_index": 0,
"master": {
"peer": [
@ -25,10 +26,13 @@
],
"role": "MASTER"
},
"response_latency": 2,
"cxx_class": "CoherentXBar",
"path": "system.membus",
"snoop_response_latency": 4,
"type": "CoherentXBar",
"use_default_range": false
"use_default_range": false,
"frontend_latency": 3
},
"symbolfile": "",
"readfile": "",
@ -154,8 +158,8 @@
},
"name": "toL2Bus",
"snoop_filter": null,
"forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
"header_cycles": 1,
"system": "system",
"width": 32,
"eventq_index": 0,
@ -165,10 +169,13 @@
],
"role": "MASTER"
},
"response_latency": 1,
"cxx_class": "CoherentXBar",
"path": "system.cpu.toL2Bus",
"snoop_response_latency": 1,
"type": "CoherentXBar",
"use_default_range": false
"use_default_range": false,
"frontend_latency": 1
},
"do_quiesce": true,
"type": "TimingSimpleCPU",
@ -208,6 +215,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -268,6 +276,7 @@
"mshrs": 20,
"forward_snoops": true,
"hit_latency": 20,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [
"0:18446744073709551615"
@ -293,6 +302,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
"kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@ -348,6 +358,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"

8
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2014 15:53:23
gem5 started Sep 21 2014 16:10:49
gem5 executing on zizzer
gem5 compiled Mar 7 2015 13:46:57
gem5 started Mar 7 2015 13:47:12
gem5 executing on zizzer2
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
49508 bytes wasted
>Exiting @ tick 727072000 because a thread reached the max instruction count
>Exiting @ tick 727072500 because a thread reached the max instruction count

534
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000727 # Number of seconds simulated
sim_ticks 727072000 # Number of ticks simulated
final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 727072500 # Number of ticks simulated
final_tick 727072500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1546280 # Simulator instruction rate (inst/s)
host_op_rate 1546201 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2248282899 # Simulator tick rate (ticks/s)
host_mem_usage 227720 # Number of bytes of host memory used
host_seconds 0.32 # Real time elapsed on the host
host_inst_rate 639322 # Simulator instruction rate (inst/s)
host_op_rate 639300 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 929601467 # Simulator tick rate (ticks/s)
host_mem_usage 223596 # Number of bytes of host memory used
host_seconds 0.78 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 25792 # Nu
system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 857 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 35473791 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39963030 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 75436821 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 35473791 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 35473791 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 35473791 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39963030 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 75436821 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 718 # Transaction distribution
system.membus.trans_dist::ReadResp 718 # Transaction distribution
system.membus.trans_dist::ReadExReq 139 # Transaction distribution
system.membus.trans_dist::ReadExResp 139 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 857 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 857 # Request fanout histogram
system.membus.reqLayer0.occupancy 857000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 7713000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
system.physmem.bw_read::cpu.inst 35473766 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39963002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 75436769 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 35473766 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 35473766 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 35473766 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39963002 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 75436769 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 1454144 # number of cpu cycles simulated
system.cpu.numCycles 1454145 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 500001 # Number of instructions committed
@ -105,7 +82,7 @@ system.cpu.num_mem_refs 180793 # nu
system.cpu.num_load_insts 124443 # Number of load instructions
system.cpu.num_store_insts 56350 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1454144 # Number of busy cycles
system.cpu.num_busy_cycles 1454145 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 59023 # Number of branches fetched
@ -144,222 +121,13 @@ system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 500019 # Class of executed instruction
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.196777 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1000443 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1000443 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 499617 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 499617 # number of overall hits
system.cpu.icache.overall_hits::total 499617 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 403 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses
system.cpu.icache.overall_misses::total 403 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 22165000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 22165000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 22165000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 22165000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 22165000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 22165000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 500020 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000806 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_latency::total 21359000 # number of overall MSHR miss cycles
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@ -433,14 +201,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 454
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system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55001.240695 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55001.240695 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55001.240695 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55001.240695 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55001.240695 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55001.240695 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21561000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 21561000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21561000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 21561000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21561000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 21561000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53501.240695 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53501.240695 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 481.541188 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019216 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 216.521972 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 718 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 714 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021912 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 7713 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 7713 # Number of data accesses
system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 454 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 857 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses
system.cpu.l2cache.overall_misses::total 857 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21158000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16537500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 37695500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7297500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7297500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 21158000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 23835000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 44993000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 21158000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 23835000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 44993000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 403 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 315 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 139 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 139 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 403 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 454 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 857 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 403 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 454 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.240695 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.696379 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.240695 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52500.583431 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.240695 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52500.583431 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 718 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 857 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16321500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12757500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 29079000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5629500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5629500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16321500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18387000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 34708500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16321500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18387000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 34708500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 718 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
@ -486,5 +463,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 604500 # La
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.trans_dist::ReadReq 718 # Transaction distribution
system.membus.trans_dist::ReadResp 718 # Transaction distribution
system.membus.trans_dist::ReadExReq 139 # Transaction distribution
system.membus.trans_dist::ReadExResp 139 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 857 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 857 # Request fanout histogram
system.membus.reqLayer0.occupancy 857500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 4285500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------

28
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -86,6 +87,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -126,6 +128,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -180,6 +183,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@ -228,6 +232,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -268,6 +273,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -322,6 +328,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@ -370,6 +377,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -410,6 +418,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -464,6 +473,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@ -512,6 +522,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -552,6 +563,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -606,6 +618,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@ -633,6 +646,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@ -666,11 +680,14 @@ size=4194304
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port
slave=system.system_port system.l2c.mem_side
@ -691,11 +708,14 @@ port=system.membus.master[0]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=8
width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side

82
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json
View file

@ -3,6 +3,38 @@
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"slave": {
"peer": [
"system.system_port",
"system.l2c.mem_side"
],
"role": "SLAVE"
},
"name": "membus",
"snoop_filter": null,
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"system": "system",
"width": 16,
"eventq_index": 0,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"response_latency": 2,
"cxx_class": "CoherentXBar",
"path": "system.membus",
"snoop_response_latency": 4,
"type": "CoherentXBar",
"use_default_range": false,
"frontend_latency": 3
},
"symbolfile": "",
"l2c": {
"is_top_level": false,
"prefetcher": null,
@ -34,6 +66,7 @@
"mshrs": 20,
"forward_snoops": true,
"hit_latency": 20,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [
"0:18446744073709551615"
@ -50,34 +83,6 @@
},
"two_queue": false
},
"kernel_addr_check": true,
"membus": {
"slave": {
"peer": [
"system.system_port",
"system.l2c.mem_side"
],
"role": "SLAVE"
},
"name": "membus",
"snoop_filter": null,
"clk_domain": "system.clk_domain",
"header_cycles": 1,
"system": "system",
"width": 8,
"eventq_index": 0,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"cxx_class": "CoherentXBar",
"path": "system.membus",
"type": "CoherentXBar",
"use_default_range": false
},
"symbolfile": "",
"readfile": "",
"cxx_class": "System",
"load_offset": 0,
@ -177,10 +182,10 @@
},
"name": "toL2Bus",
"snoop_filter": null,
"forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
"header_cycles": 1,
"system": "system",
"width": 8,
"width": 32,
"eventq_index": 0,
"master": {
"peer": [
@ -188,10 +193,13 @@
],
"role": "MASTER"
},
"response_latency": 1,
"cxx_class": "CoherentXBar",
"path": "system.toL2Bus",
"snoop_response_latency": 1,
"type": "CoherentXBar",
"use_default_range": false
"use_default_range": false,
"frontend_latency": 1
},
"mem_mode": "atomic",
"name": "system",
@ -264,6 +272,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -302,6 +311,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
"kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@ -358,6 +368,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -454,6 +465,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -492,6 +504,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
"kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@ -548,6 +561,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -644,6 +658,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -682,6 +697,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
"kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@ -738,6 +754,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -834,6 +851,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -872,6 +890,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
"kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@ -928,6 +947,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"

5
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
View file

@ -3,8 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
stdout: Broken pipe

6
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2014 15:53:23
gem5 started Sep 21 2014 16:10:49
gem5 executing on zizzer
gem5 compiled Mar 7 2015 13:46:57
gem5 started Mar 7 2015 13:47:23
gem5 executing on zizzer2
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

1632
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
View file

File diff suppressed because it is too large Load diff

28
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
View file

@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@ -82,6 +83,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -122,6 +124,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -176,6 +179,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@ -220,6 +224,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -260,6 +265,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -314,6 +320,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@ -358,6 +365,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -398,6 +406,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -452,6 +461,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@ -496,6 +506,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -536,6 +547,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@ -590,6 +602,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@ -617,6 +630,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@ -650,11 +664,14 @@ size=4194304
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port
slave=system.system_port system.l2c.mem_side
@ -675,11 +692,14 @@ port=system.membus.master[0]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=8
width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side

82
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json
View file

@ -3,6 +3,38 @@
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"slave": {
"peer": [
"system.system_port",
"system.l2c.mem_side"
],
"role": "SLAVE"
},
"name": "membus",
"snoop_filter": null,
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"system": "system",
"width": 16,
"eventq_index": 0,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"response_latency": 2,
"cxx_class": "CoherentXBar",
"path": "system.membus",
"snoop_response_latency": 4,
"type": "CoherentXBar",
"use_default_range": false,
"frontend_latency": 3
},
"symbolfile": "",
"l2c": {
"is_top_level": false,
"prefetcher": null,
@ -34,6 +66,7 @@
"mshrs": 20,
"forward_snoops": true,
"hit_latency": 20,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [
"0:18446744073709551615"
@ -50,34 +83,6 @@
},
"two_queue": false
},
"kernel_addr_check": true,
"membus": {
"slave": {
"peer": [
"system.system_port",
"system.l2c.mem_side"
],
"role": "SLAVE"
},
"name": "membus",
"snoop_filter": null,
"clk_domain": "system.clk_domain",
"header_cycles": 1,
"system": "system",
"width": 8,
"eventq_index": 0,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"cxx_class": "CoherentXBar",
"path": "system.membus",
"type": "CoherentXBar",
"use_default_range": false
},
"symbolfile": "",
"readfile": "",
"cxx_class": "System",
"load_offset": 0,
@ -177,10 +182,10 @@
},
"name": "toL2Bus",
"snoop_filter": null,
"forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
"header_cycles": 1,
"system": "system",
"width": 8,
"width": 32,
"eventq_index": 0,
"master": {
"peer": [
@ -188,10 +193,13 @@
],
"role": "MASTER"
},
"response_latency": 1,
"cxx_class": "CoherentXBar",
"path": "system.toL2Bus",
"snoop_response_latency": 1,
"type": "CoherentXBar",
"use_default_range": false
"use_default_range": false,
"frontend_latency": 1
},
"mem_mode": "timing",
"name": "system",
@ -261,6 +269,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -299,6 +308,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
"kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@ -354,6 +364,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -447,6 +458,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -485,6 +497,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
"kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@ -540,6 +553,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -633,6 +647,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -671,6 +686,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
"kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@ -726,6 +742,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -819,6 +836,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@ -857,6 +875,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
"kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@ -912,6 +931,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"

6
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
View file

@ -3,7 +3,5 @@ warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
stdout: Broken pipe
stdout: Broken pipe

8
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2014 15:53:23
gem5 started Sep 21 2014 16:10:49
gem5 executing on zizzer
gem5 compiled Mar 7 2015 13:46:57
gem5 started Mar 7 2015 13:47:11
gem5 executing on zizzer2
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -15,4 +15,4 @@ main dictionary has 1245 entries
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
>>>>Exiting @ tick 729024000 because a thread reached the max instruction count
>>>>Exiting @ tick 727903500 because a thread reached the max instruction count

2688
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
View file

File diff suppressed because it is too large Load diff