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gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt

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cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
sim_seconds 0.559962 # Number of seconds simulated
sim_ticks 559961514500 # Number of ticks simulated
final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
host_inst_rate 216839 # Simulator instruction rate (inst/s)
host_op_rate 216839 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 130731039 # Simulator tick rate (ticks/s)
host_mem_usage 291560 # Number of bytes of host memory used
host_seconds 4283.31 # Real time elapsed on the host
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_insts 928789150 # Number of instructions simulated
sim_ops 928789150 # Number of ops (including micro ops) simulated
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.voltage_domain.voltage 1 # Voltage in Volts
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.clk_domain.clock 1000 # Clock period in ticks
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.physmem.bytes_read::cpu.inst 186816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18470400 # Number of bytes read from this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_read::total 18657216 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.physmem.num_reads::cpu.inst 2919 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 288600 # Number of read requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.physmem.bw_read::cpu.inst 333623 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 32985124 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 7621438 # Total bandwidth to/from this memory (bytes/s)
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.physmem.bw_total::cpu.inst 333623 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 32985124 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bw_total::total 40940185 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.readReqs 291519 # Number of read requests accepted
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.writeReqs 66683 # Number of write requests accepted
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 17152 # Total number of bytes read from write queue
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.servicedByWrQ 268 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankRdBursts::0 17935 # Per bank write bursts
system.physmem.perBankRdBursts::1 18289 # Per bank write bursts
system.physmem.perBankRdBursts::2 18306 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::3 18250 # Per bank write bursts
system.physmem.perBankRdBursts::4 18167 # Per bank write bursts
system.physmem.perBankRdBursts::5 18240 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankRdBursts::6 18320 # Per bank write bursts
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.perBankRdBursts::7 18299 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankRdBursts::8 18230 # Per bank write bursts
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.perBankRdBursts::9 18226 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankRdBursts::10 18219 # Per bank write bursts
system.physmem.perBankRdBursts::11 18391 # Per bank write bursts
system.physmem.perBankRdBursts::12 18259 # Per bank write bursts
system.physmem.perBankRdBursts::13 18042 # Per bank write bursts
system.physmem.perBankRdBursts::14 17977 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::15 18101 # Per bank write bursts
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
system.physmem.perBankWrBursts::3 4160 # Per bank write bursts
system.physmem.perBankWrBursts::4 4142 # Per bank write bursts
system.physmem.perBankWrBursts::5 4099 # Per bank write bursts
system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankWrBursts::9 4189 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankWrBursts::10 4150 # Per bank write bursts
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4100 # Per bank write bursts
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.totGap 559961438500 # Total gap between requests
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.readPktSize::6 291519 # Read request sizes (log2)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.writePktSize::6 66683 # Write request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::0 290737 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 486 # What read queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::15 996 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 996 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::29 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesPerActivate::samples 104680 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 218.802598 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 140.854989 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 269.267896 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 39513 37.75% 37.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 43924 41.96% 79.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 8711 8.32% 88.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 724 0.69% 88.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 705 0.67% 89.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 815 0.78% 90.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1323 1.26% 91.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 784 0.75% 92.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8181 7.82% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 104680 # Bytes accessed per row activation
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdPerTurnAround::mean 71.196932 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 36.193109 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 784.958037 # Reads before turning the bus around for writes
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.rdPerTurnAround::16384-18431 1 0.02% 99.98% # Reads before turning the bus around for writes
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdPerTurnAround::total 4042 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4042 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.493073 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.471357 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.863386 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3047 75.38% 75.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 992 24.54% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.totQLat 2985206750 # Total ticks spent queuing
system.physmem.totMemAccLat 8446163000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10249.60 # Average queueing delay per DRAM burst
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgMemAccLat 28999.60 # Average memory access latency per DRAM burst
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgRdBW 33.29 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 7.62 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 33.32 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 7.62 # Average system write bandwidth in MiByte/s
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.busUtil 0.32 # Data bus utilization in percentage
system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readRowHits 202789 # Number of row buffer hits during reads
system.physmem.writeRowHits 50437 # Number of row buffer hits during writes
system.physmem.readRowHitRate 69.63 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes
system.physmem.avgGap 1563256.04 # Average gap between requests
system.physmem.pageHitRate 70.75 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 394057440 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 215011500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1136889000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 108420572385 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 240867963750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 387824533515 # Total energy per rank (pJ)
system.physmem_0.averagePower 692.597962 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 400029552000 # Time in different power states
system.physmem_0.memoryStateTime::REF 18698160000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 141228516750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 397232640 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 216744000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1134299400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 108773347950 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 240558511500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 387869287170 # Total energy per rank (pJ)
system.physmem_1.averagePower 692.677886 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 399509975000 # Time in different power states
system.physmem_1.memoryStateTime::REF 18698160000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 141748516500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.branchPred.lookups 125749069 # Number of BP lookups
system.cpu.branchPred.condPredicted 81144276 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 12157130 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 103970439 # Number of BTB lookups
system.cpu.branchPred.BTBHits 83513487 # Number of BTB hits
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.branchPred.BTBHitPct 80.324261 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 18691097 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 9450 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.read_hits 237537681 # DTB read hits
system.cpu.dtb.read_misses 198468 # DTB read misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.read_accesses 237736149 # DTB read accesses
system.cpu.dtb.write_hits 98305023 # DTB write hits
system.cpu.dtb.write_misses 7212 # DTB write misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.write_accesses 98312235 # DTB write accesses
system.cpu.dtb.data_hits 335842704 # DTB hits
system.cpu.dtb.data_misses 205680 # DTB misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.data_acv 0 # DTB access violations
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.data_accesses 336048384 # DTB accesses
system.cpu.itb.fetch_hits 317138761 # ITB hits
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.itb.fetch_misses 120 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.itb.fetch_accesses 317138881 # ITB accesses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.workload.num_syscalls 37 # Number of system calls
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.numCycles 1119923029 # number of cpu cycles simulated
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedInsts 928789150 # Number of instructions committed
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.discardedOps 27043480 # Number of ops (including micro ops) which were discarded before commit
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.cpi 1.205788 # CPI: cycles per instruction
system.cpu.ipc 0.829333 # IPC: instructions per cycle
system.cpu.tickCycles 1060170406 # Number of cycles that the object actually ticked
system.cpu.idleCycles 59752623 # Total number of cycles that the object has spent stopped
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.replacements 776532 # number of replacements
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.tagsinuse 4092.890165 # Cycle average of tags in use
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.total_refs 323503178 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit.
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.890165 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999241 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 949 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1244 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1640 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 649485148 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 649485148 # Number of data accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_hits::cpu.data 225339131 # number of ReadReq hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_hits::total 225339131 # number of ReadReq hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_hits::cpu.data 323503178 # number of demand (read+write) hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.demand_hits::total 323503178 # number of demand (read+write) hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_hits::cpu.data 323503178 # number of overall hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.overall_hits::total 323503178 # number of overall hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.overall_misses::total 849082 # number of overall misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_miss_latency::cpu.data 23417135750 # number of ReadReq miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_miss_latency::total 23417135750 # number of ReadReq miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9028767000 # number of WriteReq miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_miss_latency::total 9028767000 # number of WriteReq miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_miss_latency::cpu.data 32445902750 # number of demand (read+write) miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_miss_latency::total 32445902750 # number of demand (read+write) miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_miss_latency::cpu.data 32445902750 # number of overall miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_miss_latency::total 32445902750 # number of overall miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 226051060 # number of ReadReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses)
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_accesses::cpu.data 324352260 # number of demand (read+write) accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.demand_accesses::total 324352260 # number of demand (read+write) accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_accesses::cpu.data 324352260 # number of overall (read+write) accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.overall_accesses::total 324352260 # number of overall (read+write) accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003149 # miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_miss_rate::total 0.003149 # miss rate for ReadReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.002618 # miss rate for demand accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_miss_rate::cpu.data 0.002618 # miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32892.515616 # average ReadReq miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616 # average ReadReq miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65829.890706 # average WriteReq miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706 # average WriteReq miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_avg_miss_latency::total 38212.920248 # average overall miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_avg_miss_latency::total 38212.920248 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks
system.cpu.dcache.writebacks::total 91489 # number of writebacks
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 68454 # number of demand (read+write) MSHR hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.demand_mshr_hits::total 68454 # number of demand (read+write) MSHR hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_mshr_hits::cpu.data 68454 # number of overall MSHR hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.overall_mshr_hits::total 68454 # number of overall MSHR hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 780628 # number of demand (read+write) MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21915650000 # number of ReadReq MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21915650000 # number of ReadReq MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4445743250 # number of WriteReq MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4445743250 # number of WriteReq MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26361393250 # number of demand (read+write) MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_mshr_miss_latency::total 26361393250 # number of demand (read+write) MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26361393250 # number of overall MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_mshr_miss_latency::total 26361393250 # number of overall MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003148 # mshr miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for demand accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30796.973653 # average ReadReq mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653 # average ReadReq mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64420.791613 # average WriteReq mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613 # average WriteReq mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 10606 # number of replacements
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.tagsinuse 1687.447497 # Cycle average of tags in use
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.total_refs 317126411 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 12349 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 25680.331282 # Average number of references to valid blocks.
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447497 # Average occupied blocks per requestor
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.823949 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.823949 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.851074 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 634289871 # Number of tag accesses
system.cpu.icache.tags.data_accesses 634289871 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 317126411 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 317126411 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 317126411 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 317126411 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 317126411 # number of overall hits
system.cpu.icache.overall_hits::total 317126411 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 12350 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 12350 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 12350 # number of overall misses
system.cpu.icache.overall_misses::total 12350 # number of overall misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 333924000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 333924000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 333924000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 333924000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 333924000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 333924000 # number of overall miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.ReadReq_accesses::cpu.inst 317138761 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 317138761 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 317138761 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 317138761 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 317138761 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 317138761 # number of overall (read+write) accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27038.380567 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 27038.380567 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 27038.380567 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 27038.380567 # average overall miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12350 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 12350 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 12350 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 12350 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 12350 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 12350 # number of overall MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307968000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 307968000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307968000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 307968000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307968000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 307968000 # number of overall MSHR miss cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24936.680162 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24936.680162 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.replacements 258740 # number of replacements
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.tagsinuse 32601.451844 # Cycle average of tags in use
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.total_refs 523849 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 291476 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.797229 # Average number of references to valid blocks.
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 2865.934205 # Average occupied blocks per requestor
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 83.731537 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29651.786103 # Average occupied blocks per requestor
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.087461 # Average percentage of cache occupancy
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002555 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.904901 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.occ_percent::total 0.994917 # Average percentage of cache occupancy
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2657 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29474 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.tag_accesses 7436223 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 7436223 # Number of data accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 9430 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 489662 # number of ReadReq hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadReq_hits::total 499092 # number of ReadReq hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 91489 # number of Writeback hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 9430 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 492028 # number of demand (read+write) hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.demand_hits::total 501458 # number of demand (read+write) hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_hits::cpu.inst 9430 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 492028 # number of overall hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.overall_hits::total 501458 # number of overall hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 2920 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 221955 # number of ReadReq misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_misses::total 224875 # number of ReadReq misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 2920 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 288600 # number of demand (read+write) misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.demand_misses::total 291520 # number of demand (read+write) misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 2920 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 288600 # number of overall misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.overall_misses::total 291520 # number of overall misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 201319000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16307399500 # number of ReadReq miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_miss_latency::total 16508718500 # number of ReadReq miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4353044250 # number of ReadExReq miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::total 4353044250 # number of ReadExReq miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 201319000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 20660443750 # number of demand (read+write) miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_miss_latency::total 20861762750 # number of demand (read+write) miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 201319000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 20660443750 # number of overall miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_miss_latency::total 20861762750 # number of overall miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 12350 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 711617 # number of ReadReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadReq_accesses::total 723967 # number of ReadReq accesses(hits+misses)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 91489 # number of Writeback accesses(hits+misses)
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses)
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_accesses::cpu.inst 12350 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 780628 # number of demand (read+write) accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.demand_accesses::total 792978 # number of demand (read+write) accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_accesses::cpu.inst 12350 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 780628 # number of overall (read+write) accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.overall_accesses::total 792978 # number of overall (read+write) accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236437 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311902 # miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.310615 # miss rate for ReadReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236437 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.369702 # miss rate for demand accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.demand_miss_rate::total 0.367627 # miss rate for demand accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236437 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.369702 # miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.overall_miss_rate::total 0.367627 # miss rate for overall accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68944.863014 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73471.647406 # average ReadReq miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73412.867148 # average ReadReq miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65316.891740 # average ReadExReq miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65316.891740 # average ReadExReq miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_avg_miss_latency::total 71562.029192 # average overall miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_avg_miss_latency::total 71562.029192 # average overall miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2920 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221955 # number of ReadReq MSHR misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::total 224875 # number of ReadReq MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2920 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 288600 # number of demand (read+write) MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.demand_mshr_misses::total 291520 # number of demand (read+write) MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2920 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 288600 # number of overall MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164600500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13505684500 # number of ReadReq MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13670285000 # number of ReadReq MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3519774750 # number of ReadExReq MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519774750 # number of ReadExReq MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164600500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17025459250 # number of demand (read+write) MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::total 17190059750 # number of demand (read+write) MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164600500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17025459250 # number of overall MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::total 17190059750 # number of overall MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56370.034247 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60848.750873 # average ReadReq mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775 # average ReadReq mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52813.785730 # average ReadExReq mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730 # average ReadExReq mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 723966 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24699 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1677444 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790336 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 56605824 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 884467 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 884467 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 884467 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 533722500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 19152500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 1222191750 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadReq 224874 # Transaction distribution
system.membus.trans_dist::ReadResp 224874 # Transaction distribution
system.membus.trans_dist::Writeback 66683 # Transaction distribution
system.membus.trans_dist::ReadExReq 66645 # Transaction distribution
system.membus.trans_dist::ReadExResp 66645 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649721 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 649721 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924928 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22924928 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 358202 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 358202 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 358202 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.occupancy 975503000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.respLayer1.occupancy 2745267250 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
---------- End Simulation Statistics ----------
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