gem5/dev/sinic.hh

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/*
Many files: Update copyright dates and author list SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: build/SConstruct: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/pc_event.cc: cpu/pc_event.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/memtest/memtest.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunamireg.h: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/linux_threadinfo.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: python/SConscript: python/m5/__init__.py: python/m5/config.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/genini.py: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/ccdrv/devtime.c: util/m5/m5.c: util/oprofile-top.py: util/rundiff: util/m5/m5op.h: util/m5/m5op.s: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: util/tap/tap.cc: Update copyright dates and author list --HG-- extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
2005-06-05 11:16:00 +02:00
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DEV_SINIC_HH__
#define __DEV_SINIC_HH__
#include "base/inet.hh"
#include "base/statistics.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "dev/io_device.hh"
#include "dev/pcidev.hh"
#include "dev/pktfifo.hh"
#include "dev/sinicreg.hh"
#include "mem/bus/bus.hh"
#include "sim/eventq.hh"
namespace Sinic {
class Interface;
class Base : public PciDev
{
protected:
bool rxEnable;
bool txEnable;
Tick clock;
inline Tick cycles(int numCycles) const { return numCycles * clock; }
protected:
Tick intrDelay;
Tick intrTick;
bool cpuIntrEnable;
bool cpuPendingIntr;
void cpuIntrPost(Tick when);
void cpuInterrupt();
void cpuIntrClear();
typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent;
Fixes so m5 compiles on gcc 3.4, which has much stricter syntax. Most changes come from templated code, which is evaluated slightly differently than in previous versions of gcc. arch/alpha/alpha_linux_process.cc: Alphabetize includes. arch/alpha/vptr.hh: Change the constants that are being used for alpha pagebytes to come from the ISA. base/random.hh: cpu/static_inst.cc: sim/param.cc: Fix up template syntax. base/range.hh: Include iostream for << operator. base/res_list.hh: base/statistics.hh: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.hh: sim/eventq.hh: sim/param.hh: Fixup for templated code to resolve different scope lookup in gcc 3.4. This defers the lookup of the function/variable until actual instantiation time by making it dependent on the templated class/function. base/trace.cc: Fix call to new. base/trace.hh: Fix up #define to have full path. cpu/base_cpu.cc: Fix up call to new. dev/etherlink.hh: dev/ns_gige.hh: dev/sinic.hh: Fixup for friend class/function declaration. g++ 3.4 no longer allows typedefs to be declared as a friend class. dev/pcidev.hh: Fix up re-definition of access level to params. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Fix up header. Fix up template syntax. sim/serialize.cc: Include errno.h. sim/startup.cc: Change startupq. queue was getting destructed before all things had called ~StartupCallback(), which lead to a segfault. This puts startupq in global space, and we allocate it ourselves. Other code may be similar to this and may need changing in the future. sim/syscall_emul.hh: Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient. sim/universe.cc: Include errno.h --HG-- extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af
2005-01-15 00:34:56 +01:00
friend void IntrEvent::process();
IntrEvent *intrEvent;
Interface *interface;
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }
/**
* Serialization stuff
*/
public:
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
/**
* Construction/Destruction/Parameters
*/
public:
struct Params : public PciDev::Params
{
Tick clock;
Tick intr_delay;
};
Base(Params *p);
};
class Device : public Base
{
protected:
Platform *plat;
PhysicalMemory *physmem;
protected:
/** Receive State Machine States */
enum RxState {
rxIdle,
rxFifoBlock,
rxBeginCopy,
rxCopy,
rxCopyDone
};
/** Transmit State Machine states */
enum TxState {
txIdle,
txFifoBlock,
txBeginCopy,
txCopy,
txCopyDone
};
/** device register file */
struct {
Major changes to sinic device model. Rearrage read/write, better interrupts. dev/sinic.cc: - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. Includes RxDone, RxWait, TxDone, and TxWait - Use the new register information accessor functions to grab validity and size information for the read and write functions - read all registers directly from the register space by offset and size, not by actual name (less code) - The side effect of reading the interrupt status (clearing it) now happens outside the actual chunk of code where the value is loaded. - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - When RxData or TxData are written, their busy flag is set to indicate that they have an outstanding transaction. - The RxHigh and TxLow interrupts are special, they only interrupt if the rxEmpty or txFull limits were hit - Move reset to the command register - Update more registers on reset, clear rxEmpty and txFull - Data dumps only happen if EthernetData trace flag set - When a DMA completes, kick the other engine if it was waiting - implement all of the new interrupts - serialize the new stuff dev/sinic.hh: - Put all registers with their proper size and alignment into the regs struct so that we can copy multiple at a time. - Provide accessor functions for accessing the registers with different sizes. - Flags to track when the rx fifo hit empty and the tx fifo became full. These flags are used to determine what to do when below the watermarks, and are reset when crossing the watermark. - the txDmaEvent should actually trigger the txDmaDone function - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. - add rx_max_intr and dedicated (for dedicated thread) config params dev/sinicreg.hh: Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize, rename XxThreshold to XxFifoMark Move Reset to the Command register Add Thread to the Config register New interrupts, better names More info in RxDone and TxDone Easier access to information on each register (size, read, write, name) python/m5/objects/Ethernet.py: Both sinic and nsgige have the dedicated thread Add a parameter to configure the maximum number for receive packets per interrupt --HG-- extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
uint32_t Config; // 0x00
uint32_t Command; // 0x04
uint32_t IntrStatus; // 0x08
uint32_t IntrMask; // 0x0c
uint32_t RxMaxCopy; // 0x10
uint32_t TxMaxCopy; // 0x14
uint32_t RxMaxIntr; // 0x18
uint32_t Reserved0; // 0x1c
uint32_t RxFifoSize; // 0x20
uint32_t TxFifoSize; // 0x24
uint32_t RxFifoMark; // 0x28
uint32_t TxFifoMark; // 0x2c
uint64_t RxData; // 0x30
uint64_t RxDone; // 0x38
uint64_t RxWait; // 0x40
uint64_t TxData; // 0x48
uint64_t TxDone; // 0x50
uint64_t TxWait; // 0x58
uint64_t HwAddr; // 0x60
} regs;
struct VirtualReg {
uint64_t RxData;
uint64_t RxDone;
uint64_t TxData;
uint64_t TxDone;
PacketFifo::iterator rxPacket;
int rxPacketOffset;
int rxPacketBytes;
uint64_t rxDoneData;
VirtualReg()
: RxData(0), RxDone(0), TxData(0), TxDone(0),
rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0)
{ }
};
typedef std::vector<VirtualReg> VirtualRegs;
typedef std::list<int> VirtualList;
VirtualRegs virtualRegs;
VirtualList rxList;
VirtualList txList;
Major changes to sinic device model. Rearrage read/write, better interrupts. dev/sinic.cc: - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. Includes RxDone, RxWait, TxDone, and TxWait - Use the new register information accessor functions to grab validity and size information for the read and write functions - read all registers directly from the register space by offset and size, not by actual name (less code) - The side effect of reading the interrupt status (clearing it) now happens outside the actual chunk of code where the value is loaded. - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - When RxData or TxData are written, their busy flag is set to indicate that they have an outstanding transaction. - The RxHigh and TxLow interrupts are special, they only interrupt if the rxEmpty or txFull limits were hit - Move reset to the command register - Update more registers on reset, clear rxEmpty and txFull - Data dumps only happen if EthernetData trace flag set - When a DMA completes, kick the other engine if it was waiting - implement all of the new interrupts - serialize the new stuff dev/sinic.hh: - Put all registers with their proper size and alignment into the regs struct so that we can copy multiple at a time. - Provide accessor functions for accessing the registers with different sizes. - Flags to track when the rx fifo hit empty and the tx fifo became full. These flags are used to determine what to do when below the watermarks, and are reset when crossing the watermark. - the txDmaEvent should actually trigger the txDmaDone function - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. - add rx_max_intr and dedicated (for dedicated thread) config params dev/sinicreg.hh: Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize, rename XxThreshold to XxFifoMark Move Reset to the Command register Add Thread to the Config register New interrupts, better names More info in RxDone and TxDone Easier access to information on each register (size, read, write, name) python/m5/objects/Ethernet.py: Both sinic and nsgige have the dedicated thread Add a parameter to configure the maximum number for receive packets per interrupt --HG-- extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
uint8_t &regData8(Addr daddr) { return *((uint8_t *)&regs + daddr); }
uint32_t &regData32(Addr daddr) { return *(uint32_t *)&regData8(daddr); }
uint64_t &regData64(Addr daddr) { return *(uint64_t *)&regData8(daddr); }
private:
Addr addr;
static const Addr size = Regs::Size;
protected:
RxState rxState;
PacketFifo rxFifo;
PacketFifo::iterator rxFifoPtr;
Major changes to sinic device model. Rearrage read/write, better interrupts. dev/sinic.cc: - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. Includes RxDone, RxWait, TxDone, and TxWait - Use the new register information accessor functions to grab validity and size information for the read and write functions - read all registers directly from the register space by offset and size, not by actual name (less code) - The side effect of reading the interrupt status (clearing it) now happens outside the actual chunk of code where the value is loaded. - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - When RxData or TxData are written, their busy flag is set to indicate that they have an outstanding transaction. - The RxHigh and TxLow interrupts are special, they only interrupt if the rxEmpty or txFull limits were hit - Move reset to the command register - Update more registers on reset, clear rxEmpty and txFull - Data dumps only happen if EthernetData trace flag set - When a DMA completes, kick the other engine if it was waiting - implement all of the new interrupts - serialize the new stuff dev/sinic.hh: - Put all registers with their proper size and alignment into the regs struct so that we can copy multiple at a time. - Provide accessor functions for accessing the registers with different sizes. - Flags to track when the rx fifo hit empty and the tx fifo became full. These flags are used to determine what to do when below the watermarks, and are reset when crossing the watermark. - the txDmaEvent should actually trigger the txDmaDone function - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. - add rx_max_intr and dedicated (for dedicated thread) config params dev/sinicreg.hh: Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize, rename XxThreshold to XxFifoMark Move Reset to the Command register Add Thread to the Config register New interrupts, better names More info in RxDone and TxDone Easier access to information on each register (size, read, write, name) python/m5/objects/Ethernet.py: Both sinic and nsgige have the dedicated thread Add a parameter to configure the maximum number for receive packets per interrupt --HG-- extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
bool rxEmpty;
Addr rxDmaAddr;
uint8_t *rxDmaData;
int rxDmaLen;
TxState txState;
PacketFifo txFifo;
Major changes to sinic device model. Rearrage read/write, better interrupts. dev/sinic.cc: - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. Includes RxDone, RxWait, TxDone, and TxWait - Use the new register information accessor functions to grab validity and size information for the read and write functions - read all registers directly from the register space by offset and size, not by actual name (less code) - The side effect of reading the interrupt status (clearing it) now happens outside the actual chunk of code where the value is loaded. - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - When RxData or TxData are written, their busy flag is set to indicate that they have an outstanding transaction. - The RxHigh and TxLow interrupts are special, they only interrupt if the rxEmpty or txFull limits were hit - Move reset to the command register - Update more registers on reset, clear rxEmpty and txFull - Data dumps only happen if EthernetData trace flag set - When a DMA completes, kick the other engine if it was waiting - implement all of the new interrupts - serialize the new stuff dev/sinic.hh: - Put all registers with their proper size and alignment into the regs struct so that we can copy multiple at a time. - Provide accessor functions for accessing the registers with different sizes. - Flags to track when the rx fifo hit empty and the tx fifo became full. These flags are used to determine what to do when below the watermarks, and are reset when crossing the watermark. - the txDmaEvent should actually trigger the txDmaDone function - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. - add rx_max_intr and dedicated (for dedicated thread) config params dev/sinicreg.hh: Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize, rename XxThreshold to XxFifoMark Move Reset to the Command register Add Thread to the Config register New interrupts, better names More info in RxDone and TxDone Easier access to information on each register (size, read, write, name) python/m5/objects/Ethernet.py: Both sinic and nsgige have the dedicated thread Add a parameter to configure the maximum number for receive packets per interrupt --HG-- extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
bool txFull;
PacketPtr txPacket;
int txPacketOffset;
int txPacketBytes;
Addr txDmaAddr;
uint8_t *txDmaData;
int txDmaLen;
protected:
void reset();
void rxKick();
Tick rxKickTick;
typedef EventWrapper<Device, &Device::rxKick> RxKickEvent;
Fixes so m5 compiles on gcc 3.4, which has much stricter syntax. Most changes come from templated code, which is evaluated slightly differently than in previous versions of gcc. arch/alpha/alpha_linux_process.cc: Alphabetize includes. arch/alpha/vptr.hh: Change the constants that are being used for alpha pagebytes to come from the ISA. base/random.hh: cpu/static_inst.cc: sim/param.cc: Fix up template syntax. base/range.hh: Include iostream for << operator. base/res_list.hh: base/statistics.hh: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.hh: sim/eventq.hh: sim/param.hh: Fixup for templated code to resolve different scope lookup in gcc 3.4. This defers the lookup of the function/variable until actual instantiation time by making it dependent on the templated class/function. base/trace.cc: Fix call to new. base/trace.hh: Fix up #define to have full path. cpu/base_cpu.cc: Fix up call to new. dev/etherlink.hh: dev/ns_gige.hh: dev/sinic.hh: Fixup for friend class/function declaration. g++ 3.4 no longer allows typedefs to be declared as a friend class. dev/pcidev.hh: Fix up re-definition of access level to params. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Fix up header. Fix up template syntax. sim/serialize.cc: Include errno.h. sim/startup.cc: Change startupq. queue was getting destructed before all things had called ~StartupCallback(), which lead to a segfault. This puts startupq in global space, and we allocate it ourselves. Other code may be similar to this and may need changing in the future. sim/syscall_emul.hh: Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient. sim/universe.cc: Include errno.h --HG-- extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af
2005-01-15 00:34:56 +01:00
friend void RxKickEvent::process();
void txKick();
Tick txKickTick;
typedef EventWrapper<Device, &Device::txKick> TxKickEvent;
Fixes so m5 compiles on gcc 3.4, which has much stricter syntax. Most changes come from templated code, which is evaluated slightly differently than in previous versions of gcc. arch/alpha/alpha_linux_process.cc: Alphabetize includes. arch/alpha/vptr.hh: Change the constants that are being used for alpha pagebytes to come from the ISA. base/random.hh: cpu/static_inst.cc: sim/param.cc: Fix up template syntax. base/range.hh: Include iostream for << operator. base/res_list.hh: base/statistics.hh: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.hh: sim/eventq.hh: sim/param.hh: Fixup for templated code to resolve different scope lookup in gcc 3.4. This defers the lookup of the function/variable until actual instantiation time by making it dependent on the templated class/function. base/trace.cc: Fix call to new. base/trace.hh: Fix up #define to have full path. cpu/base_cpu.cc: Fix up call to new. dev/etherlink.hh: dev/ns_gige.hh: dev/sinic.hh: Fixup for friend class/function declaration. g++ 3.4 no longer allows typedefs to be declared as a friend class. dev/pcidev.hh: Fix up re-definition of access level to params. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Fix up header. Fix up template syntax. sim/serialize.cc: Include errno.h. sim/startup.cc: Change startupq. queue was getting destructed before all things had called ~StartupCallback(), which lead to a segfault. This puts startupq in global space, and we allocate it ourselves. Other code may be similar to this and may need changing in the future. sim/syscall_emul.hh: Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient. sim/universe.cc: Include errno.h --HG-- extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af
2005-01-15 00:34:56 +01:00
friend void TxKickEvent::process();
/**
* Retransmit event
*/
void transmit();
void txEventTransmit()
{
transmit();
if (txState == txFifoBlock)
txKick();
}
typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent;
Fixes so m5 compiles on gcc 3.4, which has much stricter syntax. Most changes come from templated code, which is evaluated slightly differently than in previous versions of gcc. arch/alpha/alpha_linux_process.cc: Alphabetize includes. arch/alpha/vptr.hh: Change the constants that are being used for alpha pagebytes to come from the ISA. base/random.hh: cpu/static_inst.cc: sim/param.cc: Fix up template syntax. base/range.hh: Include iostream for << operator. base/res_list.hh: base/statistics.hh: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.hh: sim/eventq.hh: sim/param.hh: Fixup for templated code to resolve different scope lookup in gcc 3.4. This defers the lookup of the function/variable until actual instantiation time by making it dependent on the templated class/function. base/trace.cc: Fix call to new. base/trace.hh: Fix up #define to have full path. cpu/base_cpu.cc: Fix up call to new. dev/etherlink.hh: dev/ns_gige.hh: dev/sinic.hh: Fixup for friend class/function declaration. g++ 3.4 no longer allows typedefs to be declared as a friend class. dev/pcidev.hh: Fix up re-definition of access level to params. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Fix up header. Fix up template syntax. sim/serialize.cc: Include errno.h. sim/startup.cc: Change startupq. queue was getting destructed before all things had called ~StartupCallback(), which lead to a segfault. This puts startupq in global space, and we allocate it ourselves. Other code may be similar to this and may need changing in the future. sim/syscall_emul.hh: Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient. sim/universe.cc: Include errno.h --HG-- extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af
2005-01-15 00:34:56 +01:00
friend void TxEvent::process();
TxEvent txEvent;
void txDump() const;
void rxDump() const;
/**
* receive address filter
*/
bool rxFilter(const PacketPtr &packet);
/**
* device configuration
*/
void changeConfig(uint32_t newconfig);
Major changes to sinic device model. Rearrage read/write, better interrupts. dev/sinic.cc: - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. Includes RxDone, RxWait, TxDone, and TxWait - Use the new register information accessor functions to grab validity and size information for the read and write functions - read all registers directly from the register space by offset and size, not by actual name (less code) - The side effect of reading the interrupt status (clearing it) now happens outside the actual chunk of code where the value is loaded. - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - When RxData or TxData are written, their busy flag is set to indicate that they have an outstanding transaction. - The RxHigh and TxLow interrupts are special, they only interrupt if the rxEmpty or txFull limits were hit - Move reset to the command register - Update more registers on reset, clear rxEmpty and txFull - Data dumps only happen if EthernetData trace flag set - When a DMA completes, kick the other engine if it was waiting - implement all of the new interrupts - serialize the new stuff dev/sinic.hh: - Put all registers with their proper size and alignment into the regs struct so that we can copy multiple at a time. - Provide accessor functions for accessing the registers with different sizes. - Flags to track when the rx fifo hit empty and the tx fifo became full. These flags are used to determine what to do when below the watermarks, and are reset when crossing the watermark. - the txDmaEvent should actually trigger the txDmaDone function - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. - add rx_max_intr and dedicated (for dedicated thread) config params dev/sinicreg.hh: Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize, rename XxThreshold to XxFifoMark Move Reset to the Command register Add Thread to the Config register New interrupts, better names More info in RxDone and TxDone Easier access to information on each register (size, read, write, name) python/m5/objects/Ethernet.py: Both sinic and nsgige have the dedicated thread Add a parameter to configure the maximum number for receive packets per interrupt --HG-- extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
void command(uint32_t command);
/**
* device ethernet interface
*/
public:
bool recvPacket(PacketPtr packet);
void transferDone();
void setInterface(Interface *i) { assert(!interface); interface = i; }
/**
* DMA parameters
*/
protected:
void rxDmaCopy();
void rxDmaDone();
friend class EventWrapper<Device, &Device::rxDmaDone>;
EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent;
void txDmaCopy();
void txDmaDone();
friend class EventWrapper<Device, &Device::txDmaDone>;
Major changes to sinic device model. Rearrage read/write, better interrupts. dev/sinic.cc: - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. Includes RxDone, RxWait, TxDone, and TxWait - Use the new register information accessor functions to grab validity and size information for the read and write functions - read all registers directly from the register space by offset and size, not by actual name (less code) - The side effect of reading the interrupt status (clearing it) now happens outside the actual chunk of code where the value is loaded. - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - When RxData or TxData are written, their busy flag is set to indicate that they have an outstanding transaction. - The RxHigh and TxLow interrupts are special, they only interrupt if the rxEmpty or txFull limits were hit - Move reset to the command register - Update more registers on reset, clear rxEmpty and txFull - Data dumps only happen if EthernetData trace flag set - When a DMA completes, kick the other engine if it was waiting - implement all of the new interrupts - serialize the new stuff dev/sinic.hh: - Put all registers with their proper size and alignment into the regs struct so that we can copy multiple at a time. - Provide accessor functions for accessing the registers with different sizes. - Flags to track when the rx fifo hit empty and the tx fifo became full. These flags are used to determine what to do when below the watermarks, and are reset when crossing the watermark. - the txDmaEvent should actually trigger the txDmaDone function - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. - add rx_max_intr and dedicated (for dedicated thread) config params dev/sinicreg.hh: Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize, rename XxThreshold to XxFifoMark Move Reset to the Command register Add Thread to the Config register New interrupts, better names More info in RxDone and TxDone Easier access to information on each register (size, read, write, name) python/m5/objects/Ethernet.py: Both sinic and nsgige have the dedicated thread Add a parameter to configure the maximum number for receive packets per interrupt --HG-- extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
EventWrapper<Device, &Device::txDmaDone> txDmaEvent;
Tick dmaReadDelay;
Tick dmaReadFactor;
Tick dmaWriteDelay;
Tick dmaWriteFactor;
/**
* Interrupt management
*/
protected:
void devIntrPost(uint32_t interrupts);
void devIntrClear(uint32_t interrupts = Regs::Intr_All);
void devIntrChangeMask(uint32_t newmask);
/**
* PCI Configuration interface
*/
public:
Changes for getting FreeBSD to run. SConscript: Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc. arch/alpha/isa_traits.hh: Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks(). cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: Replaced htoa()s with gtoh() and htog(). cpu/o3/fetch_impl.hh: cpu/simple/cpu.cc: Replaced htoa() with gtoh(). dev/disk_image.cc: Replaced htoa()s with letoh()s. dev/ide_ctrl.cc: Got rid of magic numbers. Added IdeChannel and IdeRegType type names where necessary. dev/ide_ctrl.hh: Got rid of unnecessary macros. Changed RegType_t to IdeRegType. Changed bmi_regs to allow accessing registers by name instead of just by array index. Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel. dev/ide_disk.cc: Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array. dev/ide_disk.hh: Updated command register struct. dev/ns_gige.cc: dev/ns_gige.hh: Made ReadConfig and WriteConfig begin with a lower-case letter. writeConfig() now takes a pointer to data as a parameter instead of a copy of data. dev/pciconfigall.cc: writeConfig() now takes a pointer to data as a parameter instead of a copy of data. dev/pcidev.cc: Cleaned up readConfig() and writeConfig() functions. dev/pcidev.hh: Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data. dev/pcireg.h: Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used. dev/rtcreg.h: Added macros for bit fields in RTC status registers A & B. dev/sinic.cc: Function name change: WriteConfig --> writeConfig. writeConfig() now takes a pointer to data instead of a copy of data. The accessing of elements of PCIConfig structure is updated. dev/sinic.hh: Function name change: WriteConfig --> writeConfig. writeConfig() now takes a pointer to data instead of a copy of data. dev/tsunami_io.cc: Added implementation of new RTC and PIT classes. dev/tsunami_io.hh: Added classes for RTC and PIT modules. dev/tsunamireg.h: Added macros for DMA ports used by Tsunami-Tru64. dev/uart8250.cc: Got rid of a magic number. Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register. dev/uart8250.hh: Added comments and macros dealing with the UART Interrupt ID register. kern/linux/linux_system.cc: Replaced htoa() with htog(). python/m5/objects/Pci.py: PciFake is a python class for Pci Devices that do nothing. python/m5/objects/Tsunami.py: TsunamiFake was renamed as IsaFake. sim/system.cc: Replaced htoa()s with htog()s. dev/isa_fake.cc: New BitKeeper file ``dev/isa_fake.cc'' TsunamiFake was renamed as IsaFake. dev/isa_fake.hh: New BitKeeper file ``dev/isa_fake.hh'' TsunmaiFake was renamed as IsaFake. dev/pitreg.h: New BitKeeper file ``dev/pitreg.h'' Useful macros for working with PIT (Periodic Interval Timer) registers. --HG-- extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
2005-08-15 22:59:58 +02:00
virtual void writeConfig(int offset, int size, const uint8_t *data);
/**
* Memory Interface
*/
public:
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
void prepareIO(int cpu, int index);
void prepareRead(int cpu, int index);
void prepareWrite(int cpu, int index);
Fault iprRead(Addr daddr, int cpu, uint64_t &result);
Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
void regWrite(Addr daddr, int cpu, const uint8_t *data);
Tick cacheAccess(MemReqPtr &req);
/**
* Statistics
*/
private:
Stats::Scalar<> rxBytes;
Stats::Formula rxBandwidth;
Stats::Scalar<> rxPackets;
Stats::Formula rxPacketRate;
Stats::Scalar<> rxIpPackets;
Stats::Scalar<> rxTcpPackets;
Stats::Scalar<> rxUdpPackets;
Stats::Scalar<> rxIpChecksums;
Stats::Scalar<> rxTcpChecksums;
Stats::Scalar<> rxUdpChecksums;
Stats::Scalar<> txBytes;
Stats::Formula txBandwidth;
Stats::Formula totBandwidth;
Stats::Formula totPackets;
Stats::Formula totBytes;
Stats::Formula totPacketRate;
Stats::Scalar<> txPackets;
Stats::Formula txPacketRate;
Stats::Scalar<> txIpPackets;
Stats::Scalar<> txTcpPackets;
Stats::Scalar<> txUdpPackets;
Stats::Scalar<> txIpChecksums;
Stats::Scalar<> txTcpChecksums;
Stats::Scalar<> txUdpChecksums;
public:
virtual void regStats();
/**
* Serialization stuff
*/
public:
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
/**
* Construction/Destruction/Parameters
*/
public:
struct Params : public Base::Params
{
IntrControl *i;
PhysicalMemory *pmem;
Tick tx_delay;
Tick rx_delay;
HierParams *hier;
Bus *pio_bus;
Bus *header_bus;
Bus *payload_bus;
Tick pio_latency;
PhysicalMemory *physmem;
IntrControl *intctrl;
bool rx_filter;
Net::EthAddr eaddr;
uint32_t rx_max_copy;
uint32_t tx_max_copy;
Major changes to sinic device model. Rearrage read/write, better interrupts. dev/sinic.cc: - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. Includes RxDone, RxWait, TxDone, and TxWait - Use the new register information accessor functions to grab validity and size information for the read and write functions - read all registers directly from the register space by offset and size, not by actual name (less code) - The side effect of reading the interrupt status (clearing it) now happens outside the actual chunk of code where the value is loaded. - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - When RxData or TxData are written, their busy flag is set to indicate that they have an outstanding transaction. - The RxHigh and TxLow interrupts are special, they only interrupt if the rxEmpty or txFull limits were hit - Move reset to the command register - Update more registers on reset, clear rxEmpty and txFull - Data dumps only happen if EthernetData trace flag set - When a DMA completes, kick the other engine if it was waiting - implement all of the new interrupts - serialize the new stuff dev/sinic.hh: - Put all registers with their proper size and alignment into the regs struct so that we can copy multiple at a time. - Provide accessor functions for accessing the registers with different sizes. - Flags to track when the rx fifo hit empty and the tx fifo became full. These flags are used to determine what to do when below the watermarks, and are reset when crossing the watermark. - the txDmaEvent should actually trigger the txDmaDone function - Add an iprRead function for when we may want speculative access to device registers through an ipr or special instruction. - The prepareRead function sets all the variables in the register file that depend on various state bits that change on the fly. - add rx_max_intr and dedicated (for dedicated thread) config params dev/sinicreg.hh: Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize, rename XxThreshold to XxFifoMark Move Reset to the Command register Add Thread to the Config register New interrupts, better names More info in RxDone and TxDone Easier access to information on each register (size, read, write, name) python/m5/objects/Ethernet.py: Both sinic and nsgige have the dedicated thread Add a parameter to configure the maximum number for receive packets per interrupt --HG-- extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
uint32_t rx_max_intr;
uint32_t rx_fifo_size;
uint32_t tx_fifo_size;
uint32_t rx_fifo_threshold;
uint32_t tx_fifo_threshold;
Tick dma_read_delay;
Tick dma_read_factor;
Tick dma_write_delay;
Tick dma_write_factor;
bool dma_no_allocate;
bool rx_thread;
bool tx_thread;
};
protected:
const Params *params() const { return (const Params *)_params; }
public:
Device(Params *params);
~Device();
};
/*
* Ethernet Interface for an Ethernet Device
*/
class Interface : public EtherInt
{
private:
Device *dev;
public:
Interface(const std::string &name, Device *d)
: EtherInt(name), dev(d) { dev->setInterface(this); }
virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
virtual void sendDone() { dev->transferDone(); }
};
/* namespace Sinic */ }
#endif // __DEV_SINIC_HH__