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gem5/src/arch/arm/insts/macromem.cc

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ARM: Move the macro mem constructor out of the isa desc. This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
2010-06-02 19:58:03 +02:00
/*
* Copyright (c) 2010 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Stephen Hines
*/
#include "arch/arm/insts/macromem.hh"
#include "arch/arm/decoder.hh"
using namespace ArmISAInst;
namespace ArmISA
{
MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
OpClass __opClass, IntRegIndex rn,
bool index, bool up, bool user, bool writeback,
bool load, uint32_t reglist) :
PredMacroOp(mnem, machInst, __opClass)
{
uint32_t regs = reglist;
uint32_t ones = number_of_ones(reglist);
// Remember that writeback adds a uop
numMicroops = ones + (writeback ? 1 : 0) + 1;
microOps = new StaticInstPtr[numMicroops];
uint32_t addr = 0;
if (!up)
addr = (ones << 2) - 4;
if (!index)
addr += 4;
ARM: Make sure ldm exception return writes back its base in the right mode. This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end.
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StaticInstPtr *uop = microOps;
StaticInstPtr wbUop;
if (writeback) {
if (up) {
wbUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
} else {
wbUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
}
}
ARM: Move the macro mem constructor out of the isa desc. This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
2010-06-02 19:58:03 +02:00
// Add 0 to Rn and stick it in ureg0.
// This is equivalent to a move.
ARM: Make sure ldm exception return writes back its base in the right mode. This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end.
2010-06-02 19:58:04 +02:00
*uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
// Write back at the start for loads. This covers the ldm exception return
// case where the base needs to be written in the old mode. Stores may need
// the original value of the base, but they don't change mode and can
// write back at the end like before.
if (load && writeback) {
*++uop = wbUop;
}
ARM: Move the macro mem constructor out of the isa desc. This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
2010-06-02 19:58:03 +02:00
unsigned reg = 0;
bool force_user = user & !bits(reglist, 15);
bool exception_ret = user & bits(reglist, 15);
ARM: Make sure ldm exception return writes back its base in the right mode. This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end.
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for (int i = 0; i < ones; i++) {
ARM: Move the macro mem constructor out of the isa desc. This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
2010-06-02 19:58:03 +02:00
// Find the next register.
while (!bits(regs, reg))
reg++;
replaceBits(regs, reg, 0);
unsigned regIdx = reg;
if (force_user) {
ARM: Allow flattening into any mode.
2010-06-02 19:58:11 +02:00
regIdx = intRegInMode(MODE_USER, regIdx);
ARM: Move the macro mem constructor out of the isa desc. This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
2010-06-02 19:58:03 +02:00
}
if (load) {
if (reg == INTREG_PC && exception_ret) {
// This must be the exception return form of ldm.
ARM: Make sure ldm exception return writes back its base in the right mode. This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end.
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*++uop = new MicroLdrRetUop(machInst, regIdx,
INTREG_UREG0, up, addr);
ARM: Move the macro mem constructor out of the isa desc. This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
2010-06-02 19:58:03 +02:00
} else {
ARM: Make sure ldm exception return writes back its base in the right mode. This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end.
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*++uop = new MicroLdrUop(machInst, regIdx,
INTREG_UREG0, up, addr);
ARM: Move the macro mem constructor out of the isa desc. This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
2010-06-02 19:58:03 +02:00
}
} else {
ARM: Make sure ldm exception return writes back its base in the right mode. This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end.
2010-06-02 19:58:04 +02:00
*++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
ARM: Move the macro mem constructor out of the isa desc. This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
2010-06-02 19:58:03 +02:00
}
if (up)
addr += 4;
else
addr -= 4;
}
ARM: Make sure ldm exception return writes back its base in the right mode. This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end.
2010-06-02 19:58:04 +02:00
if (!load && writeback) {
*++uop = wbUop;
ARM: Move the macro mem constructor out of the isa desc. This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
2010-06-02 19:58:03 +02:00
}
ARM: Make sure ldm exception return writes back its base in the right mode. This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end.
2010-06-02 19:58:04 +02:00
(*uop)->setLastMicroop();
ARM: Make sure macroops aren't interrupted midinstruction. Do this by setting the delayed commit flag for all but the last microop.
2010-06-02 19:58:12 +02:00
for (StaticInstPtr *curUop = microOps;
!(*curUop)->isLastMicroop(); curUop++) {
MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
assert(uopPtr);
uopPtr->setDelayedCommit();
}
ARM: Move the macro mem constructor out of the isa desc. This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
2010-06-02 19:58:03 +02:00
}
ARM: Add base classes for VFP load/store multiple.
2010-06-02 19:58:04 +02:00
MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
OpClass __opClass, IntRegIndex rn,
RegIndex vd, bool single, bool up,
bool writeback, bool load, uint32_t offset) :
PredMacroOp(mnem, machInst, __opClass)
{
int i = 0;
// The lowest order bit selects fldmx (set) or fldmd (clear). These seem
// to be functionally identical except that fldmx is deprecated. For now
// we'll assume they're otherwise interchangable.
int count = (single ? offset : (offset / 2));
if (count == 0 || count > NumFloatArchRegs)
warn_once("Bad offset field for VFP load/store multiple.\n");
if (count == 0) {
// Force there to be at least one microop so the macroop makes sense.
writeback = true;
}
if (count > NumFloatArchRegs)
count = NumFloatArchRegs;
ARM: Fix the implementation of the VFP ldm and stm macroops. There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02 19:58:12 +02:00
numMicroops = count * (single ? 1 : 2) + (writeback ? 1 : 0);
microOps = new StaticInstPtr[numMicroops];
ARM: Fix double precision load/store multiple decrement. When decrementing, the higher addressed half of a double word is at a 4 byte smaller displacement.
2010-06-02 19:58:15 +02:00
int64_t addr = 0;
ARM: Add base classes for VFP load/store multiple.
2010-06-02 19:58:04 +02:00
ARM: Fix the implementation of the VFP ldm and stm macroops. There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02 19:58:12 +02:00
if (!up)
addr = 4 * offset;
ARM: Add base classes for VFP load/store multiple.
2010-06-02 19:58:04 +02:00
ARM: Fix the implementation of the VFP ldm and stm macroops. There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02 19:58:12 +02:00
bool tempUp = up;
ARM: Add base classes for VFP load/store multiple.
2010-06-02 19:58:04 +02:00
for (int j = 0; j < count; j++) {
if (load) {
microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn,
ARM: Fix the implementation of the VFP ldm and stm macroops. There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02 19:58:12 +02:00
tempUp, addr);
ARM: Add base classes for VFP load/store multiple.
2010-06-02 19:58:04 +02:00
if (!single)
ARM: Fix double precision load/store multiple decrement. When decrementing, the higher addressed half of a double word is at a 4 byte smaller displacement.
2010-06-02 19:58:15 +02:00
microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn, tempUp,
addr + (up ? 4 : -4));
ARM: Add base classes for VFP load/store multiple.
2010-06-02 19:58:04 +02:00
} else {
microOps[i++] = new MicroStrFpUop(machInst, vd++, rn,
ARM: Fix the implementation of the VFP ldm and stm macroops. There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02 19:58:12 +02:00
tempUp, addr);
ARM: Add base classes for VFP load/store multiple.
2010-06-02 19:58:04 +02:00
if (!single)
ARM: Fix double precision load/store multiple decrement. When decrementing, the higher addressed half of a double word is at a 4 byte smaller displacement.
2010-06-02 19:58:15 +02:00
microOps[i++] = new MicroStrFpUop(machInst, vd++, rn, tempUp,
addr + (up ? 4 : -4));
ARM: Fix the implementation of the VFP ldm and stm macroops. There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02 19:58:12 +02:00
}
if (!tempUp) {
addr -= (single ? 4 : 8);
// The microops don't handle negative displacement, so turn if we
// hit zero, flip polarity and start adding.
ARM: Fix double precision load/store multiple decrement. When decrementing, the higher addressed half of a double word is at a 4 byte smaller displacement.
2010-06-02 19:58:15 +02:00
if (addr <= 0) {
ARM: Fix the implementation of the VFP ldm and stm macroops. There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02 19:58:12 +02:00
tempUp = true;
ARM: Fix double precision load/store multiple decrement. When decrementing, the higher addressed half of a double word is at a 4 byte smaller displacement.
2010-06-02 19:58:15 +02:00
addr = -addr;
ARM: Fix the implementation of the VFP ldm and stm macroops. There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02 19:58:12 +02:00
}
} else {
addr += (single ? 4 : 8);
ARM: Add base classes for VFP load/store multiple.
2010-06-02 19:58:04 +02:00
}
}
if (writeback) {
if (up) {
microOps[i++] =
new MicroAddiUop(machInst, rn, rn, 4 * offset);
} else {
microOps[i++] =
new MicroSubiUop(machInst, rn, rn, 4 * offset);
}
}
ARM: Fix the implementation of the VFP ldm and stm macroops. There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.
2010-06-02 19:58:12 +02:00
assert(numMicroops == i);
ARM: Add base classes for VFP load/store multiple.
2010-06-02 19:58:04 +02:00
microOps[numMicroops - 1]->setLastMicroop();
ARM: Make sure macroops aren't interrupted midinstruction. Do this by setting the delayed commit flag for all but the last microop.
2010-06-02 19:58:12 +02:00
for (StaticInstPtr *curUop = microOps;
!(*curUop)->isLastMicroop(); curUop++) {
MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
assert(uopPtr);
uopPtr->setDelayedCommit();
}
ARM: Add base classes for VFP load/store multiple.
2010-06-02 19:58:04 +02:00
}
ARM: Improve printing of uop disassembly.
2010-08-23 18:18:42 +02:00
std::string
MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, ura);
ss << ", ";
printReg(ss, urb);
ss << ", ";
ccprintf(ss, "#%d", imm);
return ss.str();
}
std::string
MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, ura);
ss << ", [";
printReg(ss, urb);
ss << ", ";
ccprintf(ss, "#%d", imm);
ss << "]";
return ss.str();
}
ARM: Move the macro mem constructor out of the isa desc. This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.
2010-06-02 19:58:03 +02:00
}
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