2010-06-02 19:58:03 +02:00
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#include "arch/arm/insts/macromem.hh"
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#include "arch/arm/decoder.hh"
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using namespace ArmISAInst;
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namespace ArmISA
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{
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MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
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OpClass __opClass, IntRegIndex rn,
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bool index, bool up, bool user, bool writeback,
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bool load, uint32_t reglist) :
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PredMacroOp(mnem, machInst, __opClass)
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{
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uint32_t regs = reglist;
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uint32_t ones = number_of_ones(reglist);
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// Remember that writeback adds a uop
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numMicroops = ones + (writeback ? 1 : 0) + 1;
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microOps = new StaticInstPtr[numMicroops];
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uint32_t addr = 0;
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if (!up)
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addr = (ones << 2) - 4;
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if (!index)
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addr += 4;
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2010-06-02 19:58:04 +02:00
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StaticInstPtr *uop = microOps;
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StaticInstPtr wbUop;
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if (writeback) {
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if (up) {
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wbUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
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} else {
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wbUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
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}
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}
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2010-06-02 19:58:03 +02:00
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// Add 0 to Rn and stick it in ureg0.
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// This is equivalent to a move.
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2010-06-02 19:58:04 +02:00
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*uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
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// Write back at the start for loads. This covers the ldm exception return
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// case where the base needs to be written in the old mode. Stores may need
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// the original value of the base, but they don't change mode and can
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// write back at the end like before.
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if (load && writeback) {
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*++uop = wbUop;
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}
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2010-06-02 19:58:03 +02:00
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unsigned reg = 0;
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bool force_user = user & !bits(reglist, 15);
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bool exception_ret = user & bits(reglist, 15);
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2010-06-02 19:58:04 +02:00
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for (int i = 0; i < ones; i++) {
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2010-06-02 19:58:03 +02:00
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// Find the next register.
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while (!bits(regs, reg))
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reg++;
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replaceBits(regs, reg, 0);
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unsigned regIdx = reg;
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if (force_user) {
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2010-06-02 19:58:11 +02:00
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regIdx = intRegInMode(MODE_USER, regIdx);
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2010-06-02 19:58:03 +02:00
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}
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if (load) {
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if (reg == INTREG_PC && exception_ret) {
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// This must be the exception return form of ldm.
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2010-06-02 19:58:04 +02:00
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*++uop = new MicroLdrRetUop(machInst, regIdx,
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INTREG_UREG0, up, addr);
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2010-06-02 19:58:03 +02:00
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} else {
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2010-06-02 19:58:04 +02:00
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*++uop = new MicroLdrUop(machInst, regIdx,
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INTREG_UREG0, up, addr);
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2010-06-02 19:58:03 +02:00
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}
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} else {
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2010-06-02 19:58:04 +02:00
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*++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
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2010-06-02 19:58:03 +02:00
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}
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if (up)
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addr += 4;
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else
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addr -= 4;
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}
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2010-06-02 19:58:04 +02:00
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if (!load && writeback) {
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*++uop = wbUop;
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2010-06-02 19:58:03 +02:00
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}
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2010-06-02 19:58:04 +02:00
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(*uop)->setLastMicroop();
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2010-06-02 19:58:12 +02:00
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for (StaticInstPtr *curUop = microOps;
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!(*curUop)->isLastMicroop(); curUop++) {
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MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
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assert(uopPtr);
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uopPtr->setDelayedCommit();
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}
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2010-06-02 19:58:03 +02:00
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}
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2010-06-02 19:58:04 +02:00
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MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
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OpClass __opClass, IntRegIndex rn,
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RegIndex vd, bool single, bool up,
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bool writeback, bool load, uint32_t offset) :
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PredMacroOp(mnem, machInst, __opClass)
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{
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int i = 0;
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// The lowest order bit selects fldmx (set) or fldmd (clear). These seem
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// to be functionally identical except that fldmx is deprecated. For now
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// we'll assume they're otherwise interchangable.
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int count = (single ? offset : (offset / 2));
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if (count == 0 || count > NumFloatArchRegs)
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warn_once("Bad offset field for VFP load/store multiple.\n");
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if (count == 0) {
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// Force there to be at least one microop so the macroop makes sense.
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writeback = true;
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}
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if (count > NumFloatArchRegs)
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count = NumFloatArchRegs;
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2010-06-02 19:58:12 +02:00
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numMicroops = count * (single ? 1 : 2) + (writeback ? 1 : 0);
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microOps = new StaticInstPtr[numMicroops];
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2010-06-02 19:58:15 +02:00
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int64_t addr = 0;
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2010-06-02 19:58:04 +02:00
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2010-06-02 19:58:12 +02:00
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if (!up)
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addr = 4 * offset;
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2010-06-02 19:58:04 +02:00
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2010-06-02 19:58:12 +02:00
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bool tempUp = up;
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2010-06-02 19:58:04 +02:00
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for (int j = 0; j < count; j++) {
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if (load) {
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microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn,
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2010-06-02 19:58:12 +02:00
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tempUp, addr);
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2010-06-02 19:58:04 +02:00
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if (!single)
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2010-06-02 19:58:15 +02:00
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microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn, tempUp,
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addr + (up ? 4 : -4));
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2010-06-02 19:58:04 +02:00
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} else {
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microOps[i++] = new MicroStrFpUop(machInst, vd++, rn,
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2010-06-02 19:58:12 +02:00
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tempUp, addr);
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2010-06-02 19:58:04 +02:00
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if (!single)
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2010-06-02 19:58:15 +02:00
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microOps[i++] = new MicroStrFpUop(machInst, vd++, rn, tempUp,
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addr + (up ? 4 : -4));
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2010-06-02 19:58:12 +02:00
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}
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if (!tempUp) {
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addr -= (single ? 4 : 8);
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// The microops don't handle negative displacement, so turn if we
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// hit zero, flip polarity and start adding.
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2010-06-02 19:58:15 +02:00
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if (addr <= 0) {
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2010-06-02 19:58:12 +02:00
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tempUp = true;
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2010-06-02 19:58:15 +02:00
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addr = -addr;
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2010-06-02 19:58:12 +02:00
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}
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} else {
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addr += (single ? 4 : 8);
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2010-06-02 19:58:04 +02:00
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}
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}
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if (writeback) {
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if (up) {
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microOps[i++] =
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new MicroAddiUop(machInst, rn, rn, 4 * offset);
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} else {
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microOps[i++] =
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new MicroSubiUop(machInst, rn, rn, 4 * offset);
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}
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}
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2010-06-02 19:58:12 +02:00
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assert(numMicroops == i);
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2010-06-02 19:58:04 +02:00
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microOps[numMicroops - 1]->setLastMicroop();
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2010-06-02 19:58:12 +02:00
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for (StaticInstPtr *curUop = microOps;
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!(*curUop)->isLastMicroop(); curUop++) {
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MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
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assert(uopPtr);
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uopPtr->setDelayedCommit();
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}
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2010-06-02 19:58:04 +02:00
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}
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2010-06-02 19:58:03 +02:00
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}
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