2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-12-01 09:15:23 +01:00
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sim_seconds 0.033081 # Number of seconds simulated
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sim_ticks 33080569000 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 33080569000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-01-25 18:19:50 +01:00
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host_inst_rate 140676 # Simulator instruction rate (inst/s)
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host_tick_rate 50998874 # Simulator tick rate (ticks/s)
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host_mem_usage 353196 # Number of bytes of host memory used
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host_seconds 648.65 # Real time elapsed on the host
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2011-12-01 09:15:23 +01:00
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sim_insts 91249885 # Number of instructions simulated
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2012-01-25 18:19:50 +01:00
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system.physmem.bytes_read 997440 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 2048 # Number of bytes written to this memory
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system.physmem.num_reads 15585 # Number of read requests responded to by this memory
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system.physmem.num_writes 32 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 30151839 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 1356204 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 61909 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 30213749 # Total bandwidth to/from this memory (bytes/s)
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 442 # Number of system calls
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2011-12-01 09:15:23 +01:00
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system.cpu.numCycles 66161139 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-12-01 09:15:23 +01:00
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system.cpu.BPredUnit.lookups 27503856 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 21975755 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 1408867 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 24498145 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 23511296 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-12-01 09:15:23 +01:00
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system.cpu.BPredUnit.usedRAS 109835 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 10070 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 15373276 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 131330352 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 27503856 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 23621131 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 32575580 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 5466802 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 14146451 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 14 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 14744728 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 369535 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 66131343 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.004854 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.741973 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-12-01 09:15:23 +01:00
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system.cpu.fetch.rateDist::0 33609066 50.82% 50.82% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 6636464 10.04% 60.86% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 5762437 8.71% 69.57% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 4857984 7.35% 76.92% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 2814891 4.26% 81.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 1640731 2.48% 83.65% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 1559267 2.36% 86.01% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 2974436 4.50% 90.51% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 6276067 9.49% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-12-01 09:15:23 +01:00
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system.cpu.fetch.rateDist::total 66131343 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.415710 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.985007 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 17946396 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 12652276 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 30529024 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 996648 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 4006999 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 4433202 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 29411 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 129091755 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 32642 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 4006999 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 19654600 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 1107804 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 8424491 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 29777332 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 3160117 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 124853414 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 254616 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 1879605 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 145685583 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 543523067 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 543516086 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 6981 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 107429439 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 38256144 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 662187 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 664355 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 7619533 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 29336350 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 5741000 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 1194254 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 692979 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 117270516 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 648807 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 106162042 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 30561 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 26211084 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 62748223 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 93963 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 66131343 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.605321 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.761707 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-12-01 09:15:23 +01:00
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system.cpu.iq.issued_per_cycle::0 24322507 36.78% 36.78% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 14238727 21.53% 58.31% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 9857796 14.91% 73.22% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 8080873 12.22% 85.44% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 4216462 6.38% 91.81% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 2267133 3.43% 95.24% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 2478028 3.75% 98.99% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 463113 0.70% 99.69% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 206704 0.31% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-12-01 09:15:23 +01:00
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system.cpu.iq.issued_per_cycle::total 66131343 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-12-01 09:15:23 +01:00
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system.cpu.iq.fu_full::IntAlu 52363 10.31% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 27 0.01% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.31% # attempts to use FU when none available
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|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.31% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 192834 37.95% 48.26% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 262907 51.74% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 74696384 70.36% 70.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 11141 0.01% 70.37% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.37% # Type of FU issued
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 159 0.00% 70.37% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.37% # Type of FU issued
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 260 0.00% 70.37% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.37% # Type of FU issued
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iq.FU_type_0::MemRead 26155378 24.64% 95.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 5298717 4.99% 100.00% # Type of FU issued
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 106162042 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.604598 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 508131 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.004786 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 278993219 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 144129610 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 102521129 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 900 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 1354 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 412 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 106669721 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 452 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 366276 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 6760478 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 42465 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 731 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 994251 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 30282 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 4006999 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 182542 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 28701 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 117958129 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 810273 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 29336350 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 5741000 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 643936 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 9429 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 1050 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 731 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 1288873 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 210071 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 1498944 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 104530426 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 25743276 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 1631616 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iew.exec_nop 38806 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 30946109 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 21214083 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 5202833 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.579937 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 102941811 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 102521541 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 60312663 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 96996327 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iew.wb_rate 1.549573 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 91262494 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 26696986 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 62124345 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.469029 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.224973 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 28387912 45.70% 45.70% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 16565318 26.66% 72.36% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 5280655 8.50% 80.86% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 3908699 6.29% 87.15% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 2045216 3.29% 90.44% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 660602 1.06% 91.51% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 536847 0.86% 92.37% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 207955 0.33% 92.71% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 4531141 7.29% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 62124345 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 91262494 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.refs 27322621 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 22575872 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 3888 # Number of memory barriers committed
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.branches 18722466 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.int_insts 72533302 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 56148 # Number of function calls committed.
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.bw_lim_events 4531141 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.rob.rob_reads 175546950 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 239939834 # The number of ROB writes
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 91249885 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 91249885 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.725054 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.725054 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.379207 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.379207 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 496902731 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 120936097 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 197 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 534 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 184886725 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 11594 # number of misc regfile writes
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.replacements 2 # number of replacements
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.icache.tagsinuse 611.587678 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 14743812 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 20420.792244 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.icache.occ_blocks::0 611.587678 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.298627 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 14743812 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 14743812 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 14743812 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 916 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 916 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 916 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 32376000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 32376000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 32376000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 14744728 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 14744728 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 14744728 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 35344.978166 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 35344.978166 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 35344.978166 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 194 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 194 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 24887000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 24887000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 24887000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000049 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000049 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000049 # mshr miss rate for overall accesses
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34469.529086 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.replacements 943456 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 3558.808717 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 28819274 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 30.414451 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 3558.808717 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.868850 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 24247443 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 4559242 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 6797 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 5792 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 28806685 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 28806685 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 989267 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 175739 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.demand_misses 1165006 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 1165006 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 5475542500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 4498706928 # number of WriteReq miss cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.demand_miss_latency 9974249428 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 9974249428 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 25236710 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 6804 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 5792 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 29971691 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 29971691 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.039200 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.037115 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.001029 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.038870 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.038870 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 5534.949109 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 25598.796670 # average WriteReq miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 8561.543398 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 8561.543398 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 8123 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.950757 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.writebacks 942907 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 86240 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 131213 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.demand_mshr_hits 217453 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 217453 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 903027 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 44526 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 947553 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 947553 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 2253075000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 1081062556 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 3334137556 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 3334137556 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035782 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009404 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.031615 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.031615 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.025066 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.354894 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 3518.681864 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 3518.681864 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.l2cache.replacements 744 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 9229.669539 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1596774 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::0 392.792284 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 8836.877255 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.011987 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.269680 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 901413 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 942907 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 31267 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 932680 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 932680 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 1057 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 14538 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 15595 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 15595 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 36209000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 498763000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 534972000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 534972000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 902470 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 942907 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 45805 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 948275 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 948275 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.001171 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.317389 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.016446 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.016446 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34256.385998 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34307.538864 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34304.071818 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34304.071818 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.writebacks 32 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
|
2011-05-14 00:29:27 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 1047 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 14538 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 15585 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 15585 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 32560500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451777500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 484338000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 484338000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001160 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317389 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.016435 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.016435 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.853868 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.629385 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
