2007-05-28 04:21:17 +02:00
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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2006-09-05 02:14:07 +02:00
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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2006-07-06 20:41:01 +02:00
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from Device import BasicPioDevice, DmaDevice, PioDevice
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2005-01-15 10:12:25 +01:00
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2007-08-16 22:49:05 +02:00
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class PciConfigAll(PioDevice):
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type = 'PciConfigAll'
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pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
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bus = Param.UInt8(0x00, "PCI bus to act as config space for")
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size = Param.MemorySize32('16MB', "Size of config space")
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class PciDevice(DmaDevice):
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type = 'PciDevice'
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abstract = True
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config = Port(Self.pio.peerObj.port, "PCI configuration space port")
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pci_bus = Param.Int("PCI bus")
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pci_dev = Param.Int("PCI device number")
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pci_func = Param.Int("PCI function code")
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pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
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config_latency = Param.Latency('20ns', "Config read or write latency")
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2005-01-15 10:12:25 +01:00
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VendorID = Param.UInt16("Vendor ID")
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DeviceID = Param.UInt16("Device ID")
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Command = Param.UInt16(0, "Command")
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Status = Param.UInt16(0, "Status")
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Revision = Param.UInt8(0, "Device")
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ProgIF = Param.UInt8(0, "Programming Interface")
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SubClassCode = Param.UInt8(0, "Sub-Class Code")
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ClassCode = Param.UInt8(0, "Class Code")
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CacheLineSize = Param.UInt8(0, "System Cacheline Size")
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LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
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HeaderType = Param.UInt8(0, "PCI Header Type")
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BIST = Param.UInt8(0, "Built In Self Test")
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BAR0 = Param.UInt32(0x00, "Base Address Register 0")
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BAR1 = Param.UInt32(0x00, "Base Address Register 1")
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BAR2 = Param.UInt32(0x00, "Base Address Register 2")
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BAR3 = Param.UInt32(0x00, "Base Address Register 3")
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BAR4 = Param.UInt32(0x00, "Base Address Register 4")
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BAR5 = Param.UInt32(0x00, "Base Address Register 5")
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2005-11-21 06:02:39 +01:00
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BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
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BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
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BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
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BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
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BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
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BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
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2009-02-01 09:02:21 +01:00
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BAR0LegacyIO = Param.Bool(False, "Whether BAR0 is hardwired legacy IO")
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BAR1LegacyIO = Param.Bool(False, "Whether BAR1 is hardwired legacy IO")
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BAR2LegacyIO = Param.Bool(False, "Whether BAR2 is hardwired legacy IO")
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BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO")
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BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO")
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BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
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2005-01-15 10:12:25 +01:00
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CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
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SubsystemID = Param.UInt16(0x00, "Subsystem ID")
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SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
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ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
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InterruptLine = Param.UInt8(0x00, "Interrupt Line")
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InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
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MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
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MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
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