2007-03-03 17:01:48 +01:00
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/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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2010-05-24 07:44:15 +02:00
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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2007-03-03 17:01:48 +01:00
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*
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2010-05-24 07:44:15 +02:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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2007-03-03 17:01:48 +01:00
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* contributors may be used to endorse or promote products derived from
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2010-05-24 07:44:15 +02:00
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* this software without specific prior written permission.
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2007-03-03 17:01:48 +01:00
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_TLB_HH__
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#define __ARCH_X86_TLB_HH__
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2007-10-03 08:00:37 +02:00
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#include <list>
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2007-11-12 23:38:24 +01:00
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#include <string>
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2011-04-15 19:44:06 +02:00
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#include <vector>
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2007-09-25 02:39:56 +02:00
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2010-08-24 01:14:24 +02:00
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#include "arch/x86/regs/segment.hh"
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2011-04-15 19:44:06 +02:00
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#include "arch/x86/pagetable.hh"
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2012-04-15 08:24:18 +02:00
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#include "base/trie.hh"
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2007-11-12 23:38:24 +01:00
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#include "mem/mem_object.hh"
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#include "mem/request.hh"
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2009-04-09 07:21:27 +02:00
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#include "params/X86TLB.hh"
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2011-02-04 06:47:58 +01:00
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#include "sim/fault_fwd.hh"
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2007-09-25 02:39:56 +02:00
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#include "sim/sim_object.hh"
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2011-04-15 19:44:06 +02:00
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#include "sim/tlb.hh"
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class ThreadContext;
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class Packet;
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namespace X86ISA
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{
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2007-11-13 03:06:57 +01:00
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class Walker;
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2008-02-27 05:38:51 +01:00
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class TLB : public BaseTLB
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{
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protected:
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2009-02-25 19:16:21 +01:00
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friend class Walker;
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2007-11-12 23:38:24 +01:00
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2008-02-27 05:39:53 +01:00
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typedef std::list<TlbEntry *> EntryList;
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2008-02-27 05:38:01 +01:00
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uint32_t configAddress;
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2007-11-12 23:38:31 +01:00
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2007-10-03 08:00:37 +02:00
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public:
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typedef X86TLBParams Params;
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TLB(const Params *p);
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TlbEntry *lookup(Addr va, bool update_lru = true);
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2008-02-27 05:38:01 +01:00
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void setConfigAddress(uint32_t addr);
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2008-02-27 05:39:53 +01:00
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protected:
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EntryList::iterator lookupIt(Addr va, bool update_lru = true);
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2007-11-13 03:06:57 +01:00
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Walker * walker;
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2011-10-13 11:22:23 +02:00
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2011-02-07 07:14:18 +01:00
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public:
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Walker *getWalker();
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2007-11-12 23:38:31 +01:00
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2013-01-07 19:05:40 +01:00
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void flushAll();
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2007-11-12 23:39:07 +01:00
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2013-01-07 19:05:40 +01:00
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void flushNonGlobal();
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2007-11-12 23:39:07 +01:00
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2008-02-27 05:38:51 +01:00
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void demapPage(Addr va, uint64_t asn);
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2007-11-12 23:39:07 +01:00
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2007-10-03 08:00:37 +02:00
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protected:
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2013-08-07 21:51:17 +02:00
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uint32_t size;
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TlbEntry * tlb;
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2007-08-27 05:33:57 +02:00
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2007-10-03 08:00:37 +02:00
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EntryList freeList;
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2007-03-03 17:01:48 +01:00
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2012-04-15 08:24:18 +02:00
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TlbEntryTrie trie;
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uint64_t lruSeq;
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2009-04-27 01:48:44 +02:00
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Fault translateInt(RequestPtr req, ThreadContext *tc);
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2009-02-25 19:16:21 +01:00
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Fault translate(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode,
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bool &delayedResponse, bool timing);
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2007-10-08 03:18:39 +02:00
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2007-10-03 08:00:37 +02:00
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public:
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2007-11-13 03:06:57 +01:00
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2012-04-15 08:24:18 +02:00
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void evictLRU();
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uint64_t
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nextSeq()
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{
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return ++lruSeq;
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}
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2009-04-09 07:21:27 +02:00
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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2009-02-25 19:16:15 +01:00
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void translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode);
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2012-03-09 15:59:28 +01:00
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/** Stub function for compilation support of CheckerCPU. x86 ISA does
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* not support Checker model at the moment
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*/
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Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
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2013-06-03 13:55:41 +02:00
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/**
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* Do post-translation physical address finalization.
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*
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* Some addresses, for example requests going to the APIC,
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* need post-translation updates. Such physical addresses are
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* remapped into a "magic" part of the physical address space
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* by this method.
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*
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* @param req Request to updated in-place.
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* @param tc Thread context that created the request.
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* @param mode Request type (read/write/execute).
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* @return A fault on failure, NoFault otherwise.
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*/
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Fault finalizePhysical(RequestPtr req, ThreadContext *tc,
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Mode mode) const;
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2009-04-09 07:21:27 +02:00
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TlbEntry * insert(Addr vpn, TlbEntry &entry);
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2007-10-03 08:00:37 +02:00
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// Checkpointing
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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2012-03-01 18:37:03 +01:00
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MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
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/**
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* Get the table walker master port. This is used for
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* migrating port connections during a CPU takeOverFrom()
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* call. For architectures that do not have a table walker,
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* NULL is returned, hence the use of a pointer rather than a
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* reference. For X86 this method will always return a valid
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* port pointer.
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*
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* @return A pointer to the walker master port
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*/
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2012-10-15 14:12:35 +02:00
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virtual BaseMasterPort *getMasterPort();
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};
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}
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2007-03-03 17:01:48 +01:00
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#endif // __ARCH_X86_TLB_HH__
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